From c5853fbbf53627e5ca00095a86d548e845d8828c Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 27 Feb 2014 14:53:20 +0100 Subject: [PATCH] ARM: i.MX: edmqmx6: correct MMDC init This is a squashed commit of the following downstream commits: - Set CS0_END in MMDC0_MDASP to 32Gb (4GB)T - Fix writes to MMDC0_MDSCR - Enable bank interleaving (BI_ON) and set write additional latency (WALAT) to 1 cycle in MMDC0_MDMISC - Set ARCR_DYN_JMP=1 and ARCR_DYN_MAX=15 in MMDC0_MAARCR Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach Signed-off-by: Sascha Hauer --- arch/arm/boards/datamodul-edm-qmx6/lowlevel.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c index 33e0152bc..81b6ac4cb 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c +++ b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c @@ -99,24 +99,19 @@ static void sdram_init(void) writel(0x8A8F7934, 0x021b000c); writel(0xDB568E65, 0x021b0010); writel(0x01FF00DB, 0x021b0014); - writel(0x00000740, 0x021b0018); + writel(0x00011740, 0x021b0018); writel(0x00008000, 0x021b001c); writel(0x000026d2, 0x021b002c); writel(0x008F0E21, 0x021b0030); - writel(0x00000047, 0x021b0040); - writel(0x11420000, 0x021b0400); + writel(0x0000007f, 0x021b0040); + writel(0x114201f0, 0x021b0400); writel(0x11420000, 0x021b4400); writel(0x841A0000, 0x021b0000); writel(0x04108032, 0x021b001c); - writel(0x00008033, 0x021b001c); + writel(0x00028033, 0x021b001c); writel(0x00048031, 0x021b001c); writel(0x09308030, 0x021b001c); writel(0x04008040, 0x021b001c); - writel(0x0410803A, 0x021b001c); - writel(0x0000803B, 0x021b001c); - writel(0x00048039, 0x021b001c); - writel(0x09308038, 0x021b001c); - writel(0x04008048, 0x021b001c); writel(0x00005800, 0x021b0020); writel(0x00011117, 0x021b0818); writel(0x00011117, 0x021b4818);