dts: update to v3.18-rc4
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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f271dddb33
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c61cf95d46
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@ -7,7 +7,10 @@ Required properties:
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- "renesas,thermal-r8a73a4" (R-Mobile AP6)
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- "renesas,thermal-r8a7779" (R-Car H1)
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- "renesas,thermal-r8a7790" (R-Car H2)
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- "renesas,thermal-r8a7791" (R-Car M2)
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- "renesas,thermal-r8a7791" (R-Car M2-W)
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- "renesas,thermal-r8a7792" (R-Car V2H)
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- "renesas,thermal-r8a7793" (R-Car M2-N)
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- "renesas,thermal-r8a7794" (R-Car E2)
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- reg : Address range of the thermal registers.
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The 1st reg will be recognized as common register
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if it has "interrupts".
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@ -21,24 +21,24 @@
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#define VF610_CLK_FASK_CLK_SEL 8
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#define VF610_CLK_AUDIO_EXT 9
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#define VF610_CLK_ENET_EXT 10
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#define VF610_CLK_PLL1_MAIN 11
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#define VF610_CLK_PLL1_SYS 11
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#define VF610_CLK_PLL1_PFD1 12
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#define VF610_CLK_PLL1_PFD2 13
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#define VF610_CLK_PLL1_PFD3 14
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#define VF610_CLK_PLL1_PFD4 15
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#define VF610_CLK_PLL2_MAIN 16
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#define VF610_CLK_PLL2_BUS 16
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#define VF610_CLK_PLL2_PFD1 17
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#define VF610_CLK_PLL2_PFD2 18
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#define VF610_CLK_PLL2_PFD3 19
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#define VF610_CLK_PLL2_PFD4 20
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#define VF610_CLK_PLL3_MAIN 21
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#define VF610_CLK_PLL3_USB_OTG 21
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#define VF610_CLK_PLL3_PFD1 22
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#define VF610_CLK_PLL3_PFD2 23
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#define VF610_CLK_PLL3_PFD3 24
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#define VF610_CLK_PLL3_PFD4 25
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#define VF610_CLK_PLL4_MAIN 26
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#define VF610_CLK_PLL5_MAIN 27
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#define VF610_CLK_PLL6_MAIN 28
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#define VF610_CLK_PLL4_AUDIO 26
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#define VF610_CLK_PLL5_ENET 27
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#define VF610_CLK_PLL6_VIDEO 28
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#define VF610_CLK_PLL3_MAIN_DIV 29
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#define VF610_CLK_PLL4_MAIN_DIV 30
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#define VF610_CLK_PLL6_MAIN_DIV 31
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@ -166,9 +166,32 @@
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#define VF610_CLK_DMAMUX3 153
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#define VF610_CLK_FLEXCAN0_EN 154
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#define VF610_CLK_FLEXCAN1_EN 155
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#define VF610_CLK_PLL7_MAIN 156
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#define VF610_CLK_PLL7_USB_HOST 156
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#define VF610_CLK_USBPHY0 157
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#define VF610_CLK_USBPHY1 158
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#define VF610_CLK_END 159
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#define VF610_CLK_LVDS1_IN 159
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#define VF610_CLK_ANACLK1 160
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#define VF610_CLK_PLL1_BYPASS_SRC 161
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#define VF610_CLK_PLL2_BYPASS_SRC 162
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#define VF610_CLK_PLL3_BYPASS_SRC 163
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#define VF610_CLK_PLL4_BYPASS_SRC 164
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#define VF610_CLK_PLL5_BYPASS_SRC 165
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#define VF610_CLK_PLL6_BYPASS_SRC 166
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#define VF610_CLK_PLL7_BYPASS_SRC 167
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#define VF610_CLK_PLL1 168
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#define VF610_CLK_PLL2 169
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#define VF610_CLK_PLL3 170
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#define VF610_CLK_PLL4 171
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#define VF610_CLK_PLL5 172
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#define VF610_CLK_PLL6 173
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#define VF610_CLK_PLL7 174
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#define VF610_PLL1_BYPASS 175
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#define VF610_PLL2_BYPASS 176
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#define VF610_PLL3_BYPASS 177
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#define VF610_PLL4_BYPASS 178
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#define VF610_PLL5_BYPASS 179
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#define VF610_PLL6_BYPASS 180
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#define VF610_PLL7_BYPASS 181
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#define VF610_CLK_END 182
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#endif /* __DT_BINDINGS_CLOCK_VF610_H */
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@ -33,6 +33,13 @@
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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bus-width = <4>;
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status = "okay";
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};
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&fec1 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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@ -42,6 +49,18 @@
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&iomuxc {
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vf610-cosmic {
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
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VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
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VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
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VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
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VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
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VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
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VF610_PAD_PTB28__GPIO_98 0x219d
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
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@ -34,6 +34,10 @@
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};
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};
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&clkc {
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fclk-enable = <0xf>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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@ -39,7 +39,9 @@
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phandle-list-bad-args = <&provider2 1 0>,
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<&provider3 0>;
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empty-property;
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string-property = "foobar";
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unterminated-string = [40 41 42 43];
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unterminated-string-list = "first", "second", [40 41 42 43];
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};
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};
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};
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