mci: add designware mmc controller support
Based on the U-Boot driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
e3ab3078dc
commit
c6c3afb3eb
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@ -34,6 +34,14 @@ config MCI_MMC_BOOT_PARTITIONS
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comment "--- MCI host drivers ---"
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config MCI_DW
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bool "Synopsys DesignWare Memory Card Interface"
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depends on ARM
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help
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This selects support for the Synopsys DesignWare Mobile Storage IP
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block, this provides host support for SD and MMC interfaces, in both
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PIO and external DMA modes.
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config MCI_MXS
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bool "i.MX23/i.MX28"
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depends on ARCH_MXS
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@ -8,3 +8,4 @@ obj-$(CONFIG_MCI_OMAP_HSMMC) += omap_hsmmc.o
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obj-$(CONFIG_MCI_PXA) += pxamci.o
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obj-$(CONFIG_MCI_S3C) += s3c.o
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obj-$(CONFIG_MCI_SPI) += mci_spi.o
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obj-$(CONFIG_MCI_DW) += dw_mmc.o
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@ -0,0 +1,609 @@
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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* Rajeshawari Shinde <rajeshwari.s@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <driver.h>
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#include <malloc.h>
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#include <clock.h>
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#include <init.h>
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#include <mci.h>
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#include <io.h>
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#include <platform_data/dw_mmc.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <asm-generic/errno.h>
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#include <asm/mmu.h>
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#define DWMCI_CTRL 0x000
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#define DWMCI_PWREN 0x004
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#define DWMCI_CLKDIV 0x008
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#define DWMCI_CLKSRC 0x00C
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#define DWMCI_CLKENA 0x010
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#define DWMCI_TMOUT 0x014
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#define DWMCI_CTYPE 0x018
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#define DWMCI_BLKSIZ 0x01C
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#define DWMCI_BYTCNT 0x020
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#define DWMCI_INTMASK 0x024
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#define DWMCI_CMDARG 0x028
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#define DWMCI_CMD 0x02C
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#define DWMCI_RESP0 0x030
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#define DWMCI_RESP1 0x034
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#define DWMCI_RESP2 0x038
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#define DWMCI_RESP3 0x03C
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#define DWMCI_MINTSTS 0x040
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#define DWMCI_RINTSTS 0x044
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#define DWMCI_STATUS 0x048
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#define DWMCI_FIFOTH 0x04C
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#define DWMCI_CDETECT 0x050
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#define DWMCI_WRTPRT 0x054
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#define DWMCI_GPIO 0x058
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#define DWMCI_TCMCNT 0x05C
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#define DWMCI_TBBCNT 0x060
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#define DWMCI_DEBNCE 0x064
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#define DWMCI_USRID 0x068
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#define DWMCI_VERID 0x06C
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#define DWMCI_HCON 0x070
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#define DWMCI_UHS_REG 0x074
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#define DWMCI_BMOD 0x080
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#define DWMCI_PLDMND 0x084
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#define DWMCI_DBADDR 0x088
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#define DWMCI_IDSTS 0x08C
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#define DWMCI_IDINTEN 0x090
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#define DWMCI_DSCADDR 0x094
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#define DWMCI_BUFADDR 0x098
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#define DWMCI_DATA 0x200
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/* Interrupt Mask register */
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#define DWMCI_INTMSK_ALL 0xffffffff
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#define DWMCI_INTMSK_RE (1 << 1)
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#define DWMCI_INTMSK_CDONE (1 << 2)
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#define DWMCI_INTMSK_DTO (1 << 3)
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#define DWMCI_INTMSK_TXDR (1 << 4)
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#define DWMCI_INTMSK_RXDR (1 << 5)
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#define DWMCI_INTMSK_RCRC (1 << 6)
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#define DWMCI_INTMSK_DCRC (1 << 7)
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#define DWMCI_INTMSK_RTO (1 << 8)
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#define DWMCI_INTMSK_DRTO (1 << 9)
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#define DWMCI_INTMSK_HTO (1 << 10)
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#define DWMCI_INTMSK_FRUN (1 << 11)
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#define DWMCI_INTMSK_HLE (1 << 12)
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#define DWMCI_INTMSK_SBE (1 << 13)
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#define DWMCI_INTMSK_ACD (1 << 14)
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#define DWMCI_INTMSK_EBE (1 << 15)
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/* Raw interrupt Register */
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#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
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DWMCI_INTMSK_FRUN | DWMCI_INTMSK_DCRC)
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#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
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/* CTRL register */
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#define DWMCI_CTRL_RESET (1 << 0)
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#define DWMCI_CTRL_FIFO_RESET (1 << 1)
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#define DWMCI_CTRL_DMA_RESET (1 << 2)
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#define DWMCI_DMA_EN (1 << 5)
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#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
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#define DWMCI_IDMAC_EN (1 << 25)
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#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
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DWMCI_CTRL_DMA_RESET)
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/* CMD register */
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#define DWMCI_CMD_RESP_EXP (1 << 6)
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#define DWMCI_CMD_RESP_LENGTH (1 << 7)
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#define DWMCI_CMD_CHECK_CRC (1 << 8)
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#define DWMCI_CMD_DATA_EXP (1 << 9)
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#define DWMCI_CMD_RW (1 << 10)
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#define DWMCI_CMD_SEND_STOP (1 << 12)
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#define DWMCI_CMD_ABORT_STOP (1 << 14)
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#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
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#define DWMCI_CMD_UPD_CLK (1 << 21)
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#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
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#define DWMCI_CMD_START (1 << 31)
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/* CLKENA register */
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#define DWMCI_CLKEN_ENABLE (1 << 0)
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#define DWMCI_CLKEN_LOW_PWR (1 << 16)
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/* Card-type register */
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#define DWMCI_CTYPE_1BIT 0
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#define DWMCI_CTYPE_4BIT (1 << 0)
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#define DWMCI_CTYPE_8BIT (1 << 16)
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/* Status Register */
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#define DWMCI_STATUS_BUSY (1 << 9)
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/* FIFOTH Register */
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#define DWMCI_FIFOTH_MSIZE(x) ((x) << 28)
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#define DWMCI_FIFOTH_RX_WMARK(x) ((x) << 16)
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#define DWMCI_FIFOTH_TX_WMARK(x) (x)
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#define DWMCI_FIFOTH_FIFO_DEPTH(x) ((((x) >> 16) & 0x3ff) + 1)
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#define DWMCI_IDMAC_OWN (1 << 31)
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#define DWMCI_IDMAC_CH (1 << 4)
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#define DWMCI_IDMAC_FS (1 << 3)
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#define DWMCI_IDMAC_LD (1 << 2)
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/* Bus Mode Register */
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#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
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#define DWMCI_BMOD_IDMAC_FB (1 << 1)
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#define DWMCI_BMOD_IDMAC_EN (1 << 7)
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struct dwmci_host {
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struct mci_host mci;
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struct device_d *dev;
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struct clk *clk_biu, *clk_ciu;
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void *ioaddr;
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unsigned int fifo_size_bytes;
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struct dwmci_idmac *idmac;
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unsigned long clkrate;
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int ciu_div;
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};
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struct dwmci_idmac {
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uint32_t flags;
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uint32_t cnt;
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uint32_t addr;
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uint32_t next_addr;
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};
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static inline void dwmci_writel(struct dwmci_host *host, int reg, uint32_t val)
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{
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writel(val, host->ioaddr + reg);
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}
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static inline uint32_t dwmci_readl(struct dwmci_host *host, int reg)
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{
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return readl(host->ioaddr + reg);
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}
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#define DW_MMC_NUM_IDMACS (PAGE_SIZE / sizeof(struct dwmci_idmac))
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static inline struct dwmci_host *to_dwmci_host(struct mci_host *mci)
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{
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return container_of(mci, struct dwmci_host, mci);
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}
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static int dwmci_wait_reset(struct dwmci_host *host, uint32_t value)
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{
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uint64_t start;
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uint32_t ctrl;
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start = get_time_ns();
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dwmci_writel(host, DWMCI_CTRL, value);
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while (!is_timeout(start, SECOND)) {
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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if (!(ctrl & DWMCI_RESET_ALL))
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return 0;
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}
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return -EIO;
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}
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static int dwmci_prepare_data(struct dwmci_host *host,
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struct mci_data *data)
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{
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unsigned long ctrl;
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unsigned int i = 0, flags, cnt, blk_cnt;
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unsigned long data_start, start_addr;
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struct dwmci_idmac *desc = host->idmac;
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blk_cnt = data->blocks;
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if (blk_cnt > DW_MMC_NUM_IDMACS)
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return -EINVAL;
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dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
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data_start = (uint32_t)desc;
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dwmci_writel(host, DWMCI_DBADDR, (uint32_t)desc);
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if (data->flags & MMC_DATA_READ)
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start_addr = (uint32_t)data->dest;
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else
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start_addr = (uint32_t)data->src;
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do {
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flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH;
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flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
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if (blk_cnt <= 8) {
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flags |= DWMCI_IDMAC_LD;
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cnt = data->blocksize * blk_cnt;
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} else {
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cnt = data->blocksize * 8;
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}
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desc->flags = flags;
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desc->cnt = cnt;
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desc->addr = start_addr + (i * PAGE_SIZE);
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desc->next_addr = (uint32_t)(desc + 1);
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dev_dbg(host->dev, "desc@ 0x%p 0x%08x 0x%08x 0x%08x 0x%08x\n",
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desc, flags, cnt, desc->addr, desc->next_addr);
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if (blk_cnt < 8)
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break;
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blk_cnt -= 8;
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desc++;
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i++;
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} while (1);
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
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dwmci_writel(host, DWMCI_CTRL, ctrl);
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ctrl = dwmci_readl(host, DWMCI_BMOD);
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ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
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dwmci_writel(host, DWMCI_BMOD, ctrl);
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dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
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dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
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return 0;
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}
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static int dwmci_set_transfer_mode(struct dwmci_host *host,
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struct mci_data *data)
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{
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unsigned long mode;
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mode = DWMCI_CMD_DATA_EXP;
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if (data->flags & MMC_DATA_WRITE)
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mode |= DWMCI_CMD_RW;
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return mode;
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}
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static int
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dwmci_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
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{
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struct dwmci_host *host = to_dwmci_host(mci);
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int flags = 0;
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uint32_t mask, ctrl;
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uint64_t start;
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int ret;
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unsigned int num_bytes = 0;
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const void *writebuf = NULL;
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start = get_time_ns();
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while (1) {
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if (!(dwmci_readl(host, DWMCI_STATUS) & DWMCI_STATUS_BUSY))
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break;
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if (is_timeout(start, 100 * MSECOND)) {
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dev_dbg(host->dev, "Timeout on data busy\n");
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return -ETIMEDOUT;
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}
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}
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dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
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if (data) {
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num_bytes = data->blocks * data->blocksize;
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if (data->flags & MMC_DATA_WRITE) {
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dma_flush_range((unsigned long)data->src,
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(unsigned long)(data->src + data->blocks * 512));
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writebuf = data->src;
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}
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ret = dwmci_prepare_data(host, data);
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if (ret)
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return ret;
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}
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dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
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if (data)
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flags = dwmci_set_transfer_mode(host, data);
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
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return -EINVAL;
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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flags |= DWMCI_CMD_ABORT_STOP;
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else
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flags |= DWMCI_CMD_PRV_DAT_WAIT;
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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flags |= DWMCI_CMD_RESP_EXP;
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if (cmd->resp_type & MMC_RSP_136)
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flags |= DWMCI_CMD_RESP_LENGTH;
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}
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= DWMCI_CMD_CHECK_CRC;
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flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
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dev_dbg(host->dev, "Sending CMD%d\n", cmd->cmdidx);
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dwmci_writel(host, DWMCI_CMD, flags);
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start = get_time_ns();
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while (1) {
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mask = dwmci_readl(host, DWMCI_RINTSTS);
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if (mask & DWMCI_INTMSK_CDONE) {
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if (!data)
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dwmci_writel(host, DWMCI_RINTSTS, mask);
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break;
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}
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if (is_timeout(start, 100 * MSECOND))
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return -ETIMEDOUT;
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}
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if (mask & DWMCI_INTMSK_RTO) {
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dev_dbg(host->dev, "Response Timeout..\n");
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return -ETIMEDOUT;
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} else if (mask & DWMCI_INTMSK_RE) {
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dev_dbg(host->dev, "Response Error..\n");
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return -EIO;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
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cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
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cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
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cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
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} else {
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cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
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}
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}
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if (data) {
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start = get_time_ns();
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do {
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mask = dwmci_readl(host, DWMCI_RINTSTS);
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if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
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dev_dbg(host->dev, "DATA ERROR!\n");
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return -EIO;
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}
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if (is_timeout(start, SECOND))
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return -ETIMEDOUT;
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} while (!(mask & DWMCI_INTMSK_DTO));
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dwmci_writel(host, DWMCI_RINTSTS, mask);
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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ctrl &= ~(DWMCI_DMA_EN);
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dwmci_writel(host, DWMCI_CTRL, ctrl);
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if (data->flags & MMC_DATA_READ) {
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dma_inv_range((unsigned long)data->dest,
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(unsigned long)(data->dest + data->blocks * 512));
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}
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}
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udelay(100);
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return 0;
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}
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static int dwmci_send_cmd(struct dwmci_host *host, u32 cmd, u32 arg)
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{
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uint64_t start = get_time_ns();
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uint32_t status;
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dwmci_writel(host, DWMCI_CMDARG, arg);
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dwmci_writel(host, DWMCI_CMD, cmd | DWMCI_CMD_START);
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while (1) {
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status = dwmci_readl(host, DWMCI_CMD);
|
||||
if (!(status & DWMCI_CMD_START))
|
||||
return 0;
|
||||
|
||||
if (is_timeout(start, 100 * MSECOND)) {
|
||||
dev_err(host->dev, "TIMEOUT error!!\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int dwmci_setup_bus(struct dwmci_host *host, uint32_t freq)
|
||||
{
|
||||
uint32_t div;
|
||||
unsigned long sclk;
|
||||
|
||||
sclk = host->clkrate / host->ciu_div;
|
||||
|
||||
div = DIV_ROUND_UP(sclk, freq);
|
||||
if (div > 510)
|
||||
div = 510;
|
||||
|
||||
div >>= 1;
|
||||
|
||||
dwmci_writel(host, DWMCI_CLKENA, 0);
|
||||
dwmci_writel(host, DWMCI_CLKSRC, 0);
|
||||
|
||||
dwmci_writel(host, DWMCI_CLKDIV, div);
|
||||
|
||||
dwmci_send_cmd(host, DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK, 0);
|
||||
|
||||
dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE);
|
||||
|
||||
dwmci_send_cmd(host, DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dwmci_set_ios(struct mci_host *mci, struct mci_ios *ios)
|
||||
{
|
||||
struct dwmci_host *host = to_dwmci_host(mci);
|
||||
uint32_t ctype;
|
||||
|
||||
dev_dbg(host->dev, "Buswidth = %d, clock: %d\n", ios->bus_width, ios->clock);
|
||||
|
||||
if (ios->clock)
|
||||
dwmci_setup_bus(host, ios->clock);
|
||||
|
||||
switch (ios->bus_width) {
|
||||
case MMC_BUS_WIDTH_8:
|
||||
ctype = DWMCI_CTYPE_8BIT;
|
||||
break;
|
||||
case MMC_BUS_WIDTH_4:
|
||||
ctype = DWMCI_CTYPE_4BIT;
|
||||
break;
|
||||
default:
|
||||
ctype = DWMCI_CTYPE_1BIT;
|
||||
break;
|
||||
}
|
||||
|
||||
dwmci_writel(host, DWMCI_CTYPE, ctype);
|
||||
}
|
||||
|
||||
static int dwmci_card_present(struct mci_host *mci)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int dwmci_init(struct mci_host *mci, struct device_d *dev)
|
||||
{
|
||||
struct dwmci_host *host = to_dwmci_host(mci);
|
||||
uint32_t fifo_size, fifoth_val;
|
||||
|
||||
dwmci_writel(host, DWMCI_PWREN, 1);
|
||||
|
||||
if (dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
|
||||
dev_err(host->dev, "reset failed\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
dwmci_writel(host, DWMCI_RINTSTS, 0xffffffff);
|
||||
dwmci_writel(host, DWMCI_INTMASK, 0);
|
||||
|
||||
dwmci_writel(host, DWMCI_TMOUT, 0xffffffff);
|
||||
|
||||
dwmci_writel(host, DWMCI_IDINTEN, 0);
|
||||
dwmci_writel(host, DWMCI_BMOD, 1);
|
||||
|
||||
fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
|
||||
|
||||
/*
|
||||
* Use reset default of the rx_wmark field to determine the
|
||||
* fifo depth.
|
||||
*/
|
||||
fifo_size = DWMCI_FIFOTH_FIFO_DEPTH(fifo_size);
|
||||
host->fifo_size_bytes = fifo_size * 4;
|
||||
|
||||
fifoth_val = DWMCI_FIFOTH_MSIZE(0x2) |
|
||||
DWMCI_FIFOTH_RX_WMARK(fifo_size / 2 - 1) |
|
||||
DWMCI_FIFOTH_TX_WMARK(fifo_size / 2);
|
||||
|
||||
dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
|
||||
|
||||
dwmci_writel(host, DWMCI_CLKENA, 0);
|
||||
dwmci_writel(host, DWMCI_CLKSRC, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dw_mmc_detect(struct device_d *dev)
|
||||
{
|
||||
struct dwmci_host *host = dev->priv;
|
||||
|
||||
return mci_detect_card(&host->mci);
|
||||
}
|
||||
|
||||
static int dw_mmc_probe(struct device_d *dev)
|
||||
{
|
||||
struct dwmci_host *host;
|
||||
struct mci_host *mci;
|
||||
struct dw_mmc_platform_data *pdata = dev->platform_data;
|
||||
|
||||
host = xzalloc(sizeof(*host));
|
||||
mci = &host->mci;
|
||||
|
||||
host->clk_biu = clk_get(dev, "biu");
|
||||
if (IS_ERR(host->clk_biu))
|
||||
return PTR_ERR(host->clk_biu);
|
||||
|
||||
host->clk_ciu = clk_get(dev, "ciu");
|
||||
if (IS_ERR(host->clk_ciu))
|
||||
return PTR_ERR(host->clk_ciu);
|
||||
|
||||
clk_enable(host->clk_biu);
|
||||
clk_enable(host->clk_ciu);
|
||||
|
||||
host->dev = dev;
|
||||
host->ioaddr = dev_request_mem_region(dev, 0);
|
||||
if (!host->ioaddr)
|
||||
return -EBUSY;
|
||||
|
||||
if (pdata) {
|
||||
mci->devname = pdata->devname;
|
||||
host->ciu_div = pdata->ciu_div;
|
||||
} else if (dev->device_node) {
|
||||
const char *alias = of_alias_get(dev->device_node);
|
||||
if (alias)
|
||||
mci->devname = xstrdup(alias);
|
||||
of_property_read_u32(dev->device_node, "dw-mshc-ciu-div",
|
||||
&host->ciu_div);
|
||||
}
|
||||
|
||||
/* divider is 0 based in pdata and 1 based in our private struct */
|
||||
host->ciu_div++;
|
||||
|
||||
host->idmac = dma_alloc_coherent(sizeof(*host->idmac) * DW_MMC_NUM_IDMACS);
|
||||
|
||||
host->mci.send_cmd = dwmci_cmd;
|
||||
host->mci.set_ios = dwmci_set_ios;
|
||||
host->mci.init = dwmci_init;
|
||||
host->mci.card_present = dwmci_card_present;
|
||||
host->mci.hw_dev = dev;
|
||||
host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||||
host->mci.host_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
|
||||
|
||||
dev->detect = dw_mmc_detect;
|
||||
|
||||
host->clkrate = clk_get_rate(host->clk_ciu);
|
||||
host->mci.f_min = host->clkrate / 510 / host->ciu_div;
|
||||
if (host->mci.f_min < 200000)
|
||||
host->mci.f_min = 200000;
|
||||
host->mci.f_max = host->clkrate / host->ciu_div;
|
||||
|
||||
mci_of_parse(&host->mci);
|
||||
|
||||
dev->priv = host;
|
||||
|
||||
return mci_register(&host->mci);
|
||||
}
|
||||
|
||||
static __maybe_unused struct of_device_id dw_mmc_compatible[] = {
|
||||
{
|
||||
.compatible = "altr,socfpga-dw-mshc",
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct driver_d dw_mmc_driver = {
|
||||
.name = "dw_mmc",
|
||||
.probe = dw_mmc_probe,
|
||||
.of_compatible = DRV_OF_COMPAT(dw_mmc_compatible),
|
||||
};
|
||||
device_platform_driver(dw_mmc_driver);
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#ifndef __INCLUDE_PLATFORM_DATA_DW_MMC_H
|
||||
#define __INCLUDE_PLATFORM_DATA_DW_MMC_H
|
||||
|
||||
struct dw_mmc_platform_data {
|
||||
char *devname;
|
||||
int ciu_div;
|
||||
};
|
||||
|
||||
#endif /* __INCLUDE_PLATFORM_DATA_DW_MMC_H */
|
||||
Loading…
Reference in New Issue