sysmo-bts
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barebox
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Merge branch 'for-next/omap'

This commit is contained in:
Sascha Hauer 2013-06-02 16:28:34 +02:00
parent 1f23a43924 b6acb2b64a
commit c73638daf5
7 changed files with 90 additions and 6 deletions
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4
arch/arm/boards/pcm049/board.c
View File

@ -48,7 +48,11 @@ console_initcall(pcm049_console_init);
static int pcm049_mem_init(void)
{
#ifdef CONFIG_1024MB_DDR2RAM
omap_add_ram0(SZ_1G);
#else
omap_add_ram0(SZ_512M);
#endif
omap44xx_add_sram0();
return 0;

31
arch/arm/boards/pcm049/lowlevel.c
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@ -30,6 +30,7 @@
void set_muxconf_regs(void);
/* 512MB */
static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
.tim1 = 0x0EEB0662,
.tim2 = 0x20370DD2,
@ -43,6 +44,20 @@ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
.mr2 = 0x4
};
/* 1GB */
static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = {
.tim1 = 0x0EEB0663,
.tim2 = 0x205715D2,
.tim3 = 0x00BFC53F,
.phy_ctrl_1 = 0x849FF408,
.ref_ctrl = 0x00000618,
.config_init = 0x80001AB9,
.config_final = 0x80001AB9,
.zq_config = 0x50093215,
.mr1 = 0x83,
.mr2 = 0x4
};
static void noinline pcm049_init_lowlevel(void)
{
struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
@ -55,7 +70,11 @@ static void noinline pcm049_init_lowlevel(void)
set_muxconf_regs();
omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
#ifdef CONFIG_1024MB_DDR2RAM
omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core);
#else
omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
#endif
/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
omap4_scale_vcores(TPS62361_VSEL0_GPIO);
@ -76,11 +95,11 @@ static void noinline pcm049_init_lowlevel(void)
/* Enable all clocks */
omap4_enable_all_clocks();
sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */
sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */
sr32(0x4A30a31C, 16, 4, 0x0); /* set divisor to 1 */
sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */
sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */
sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1); /* enable software ioreq */
sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */
sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x0); /* set divisor to 1 */
sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1); /* activate clock source */
sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */
}
void barebox_arm_reset_vector(void)

12
arch/arm/mach-omap/Kconfig
View File

@ -214,6 +214,18 @@ endchoice
endif
if MACH_PCM049
choice
prompt "Select DDR2-RAM Size"
config 512MB_DDR2RAM
bool "512MB"
config 1024MB_DDR2RAM
bool "1024MB"
endchoice
endif
config MACH_OMAP_ADVANCED_MUX
bool "Enable advanced pin muxing"
depends on MACH_OMAP343xSDP

8
arch/arm/mach-omap/am33xx_clock.c
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@ -89,6 +89,14 @@ static void per_clocks_enable(void)
__raw_writel(PRCM_MOD_EN, CM_WKUP_UART0_CLKCTRL);
while (__raw_readl(CM_WKUP_UART0_CLKCTRL) != PRCM_MOD_EN);
/* UART1 */
__raw_writel(PRCM_MOD_EN, CM_PER_UART1_CLKCTRL);
while (__raw_readl(CM_PER_UART1_CLKCTRL) != PRCM_MOD_EN);
/* UART2 */
__raw_writel(PRCM_MOD_EN, CM_PER_UART2_CLKCTRL);
while (__raw_readl(CM_PER_UART2_CLKCTRL) != PRCM_MOD_EN);
/* UART3 */
__raw_writel(PRCM_MOD_EN, CM_PER_UART3_CLKCTRL);
while (__raw_readl(CM_PER_UART3_CLKCTRL) != PRCM_MOD_EN);

35
arch/arm/mach-omap/am33xx_mux.c
View File

@ -27,6 +27,12 @@ static const __maybe_unused struct module_pin_mux uart0_pin_mux[] = {
{-1},
};
static const __maybe_unused struct module_pin_mux uart2_pin_mux[] = {
{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART2_RXD */
{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
{-1},
};
static const __maybe_unused struct module_pin_mux uart3_pin_mux[] = {
{OFFSET(spi0_cs1), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART3_RXD */
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
@ -142,6 +148,20 @@ static const __maybe_unused struct module_pin_mux rmii1_pin_mux[] = {
{-1},
};
static const __maybe_unused struct module_pin_mux rmii2_pin_mux[] = {
{OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
{OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
{OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
{OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
{OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRS */
{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXERR */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* RMII2_REFCLK */
{-1},
};
#ifdef CONFIG_NOR
static const __maybe_unused struct module_pin_mux nor_pin_mux[] = {
{OFFSET(lcd_data0), MODE(1) | PULLUDEN}, /* NOR_A0 */
@ -255,6 +275,16 @@ void am33xx_enable_mii1_pin_mux(void)
configure_module_pin_mux(mii1_pin_mux);
}
void am33xx_enable_rmii1_pin_mux(void)
{
configure_module_pin_mux(rmii1_pin_mux);
}
void am33xx_enable_rmii2_pin_mux(void)
{
configure_module_pin_mux(rmii2_pin_mux);
}
void am33xx_enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
@ -275,6 +305,11 @@ void am33xx_enable_uart0_pin_mux(void)
configure_module_pin_mux(uart0_pin_mux);
}
void am33xx_enable_uart2_pin_mux(void)
{
configure_module_pin_mux(uart2_pin_mux);
}
void am33xx_enable_mmc0_pin_mux(void)
{
configure_module_pin_mux(mmc0_pin_mux);

3
arch/arm/mach-omap/include/mach/am33xx-clock.h
View File

@ -136,7 +136,10 @@
#define CM_PER_GPIO1_CLKCTRL (CM_PER + 0xAC) /* GPIO1 */
#define CM_PER_GPIO2_CLKCTRL (CM_PER + 0xB0) /* GPIO2 */
#define CM_PER_GPIO3_CLKCTRL (CM_PER + 0xB4) /* GPIO3 */
#define CM_PER_UART1_CLKCTRL (CM_PER + 0x6C) /* UART1 */
#define CM_PER_UART2_CLKCTRL (CM_PER + 0x70) /* UART2 */
#define CM_PER_UART3_CLKCTRL (CM_PER + 0x74) /* UART3 */
#define CM_PER_UART4_CLKCTRL (CM_PER + 0x78) /* UART4 */
#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */
#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */
#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */

3
arch/arm/mach-omap/include/mach/am33xx-mux.h
View File

@ -248,10 +248,13 @@ extern void configure_module_pin_mux(const struct module_pin_mux *mod_pin_mux);
/* Standard mux settings */
extern void am33xx_enable_mii1_pin_mux(void);
extern void am33xx_enable_rmii1_pin_mux(void);
extern void am33xx_enable_rmii2_pin_mux(void);
extern void am33xx_enable_i2c0_pin_mux(void);
extern void am33xx_enable_i2c1_pin_mux(void);
extern void am33xx_enable_i2c2_pin_mux(void);
extern void am33xx_enable_uart0_pin_mux(void);
extern void am33xx_enable_uart2_pin_mux(void);
extern void am33xx_enable_mmc0_pin_mux(void);
#endif /*__AM33XX_MUX_H__ */