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clk: i.MX7: setup ethernet clocks 

Reparent ethernet clocks so that they can be used by the
fec driver. The values are the same as U-Boot uses.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2017-02-02 12:08:32 +01:00
parent 75cb02078e
commit c82e1f90d2
1 changed files with 11 additions and 0 deletions
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11
drivers/clk/imx/clk-imx7.c
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@ -844,6 +844,17 @@ static int imx7_clk_setup(void)
/* set uart module clock's parent clock source that must be great then 80MHz */
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
clk_set_parent(clks[IMX7D_ENET1_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_125M_CLK]);
clk_set_parent(clks[IMX7D_ENET1_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]);
clk_set_parent(clks[IMX7D_ENET2_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_125M_CLK]);
clk_set_parent(clks[IMX7D_ENET2_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]);
clk_set_rate(clks[IMX7D_PLL_SYS_PFD4_CLK], 392000000);
clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD4_CLK]);
clk_set_rate(clks[IMX7D_ENET_AXI_ROOT_CLK], 197000000);
clk_set_rate(clks[IMX7D_ENET1_TIME_ROOT_CLK], 25000000);
clk_set_rate(clks[IMX7D_ENET2_TIME_ROOT_CLK], 25000000);
return 0;
}
postcore_initcall(imx7_clk_setup);