dts: update to v4.8-rc7
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
1a1fc4fa21
commit
c8b07468de
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@ -10,7 +10,7 @@ Required properties:
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subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
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family).
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- clock-names: Should be "mmc".
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- clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
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See: Documentation/devicetree/bindings/resource-names.txt
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- clocks: Phandle to the clock.
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See: Documentation/devicetree/bindings/clock/clock-bindings.txt
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@ -2,6 +2,7 @@
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/ {
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memory {
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device_type = "memory";
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reg = <0 0x10000000>;
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};
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@ -2,7 +2,6 @@
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#include <dt-bindings/clock/bcm2835.h>
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#include <dt-bindings/clock/bcm2835-aux.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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/* This include file covers the common peripherals and configuration between
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* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
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@ -13,6 +12,8 @@
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compatible = "brcm,bcm2835";
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model = "BCM2835";
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "earlyprintk console=ttyAMA0";
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@ -550,8 +550,9 @@
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interrupt-names = "mmcirq";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mmc0>;
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clock-names = "mmc";
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clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
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clock-names = "mmc", "icn";
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clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
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bus-width = <8>;
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non-removable;
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};
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@ -565,8 +566,9 @@
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interrupt-names = "mmcirq";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sd1>;
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clock-names = "mmc";
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clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
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clock-names = "mmc", "icn";
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clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
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<&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
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resets = <&softreset STIH407_MMC1_SOFTRESET>;
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bus-width = <4>;
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};
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@ -41,7 +41,8 @@
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compatible = "st,st-ohci-300x";
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reg = <0x9a03c00 0x100>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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@ -57,7 +58,8 @@
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interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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@ -71,7 +73,8 @@
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compatible = "st,st-ohci-300x";
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reg = <0x9a83c00 0x100>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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@ -87,7 +90,8 @@
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interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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@ -255,10 +255,10 @@
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/* Local timer */
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xf01>,
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<1 14 0xf01>,
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<1 11 0xf01>,
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<1 10 0xf01>;
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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timer0: timer0@ffc03000 {
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@ -102,13 +102,13 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
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};
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xtal: xtal-clk {
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@ -110,10 +110,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 0 0xff01>, /* Secure Phys IRQ */
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<1 13 0xff01>, /* Non-secure Phys IRQ */
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<1 14 0xff01>, /* Virt IRQ */
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<1 15 0xff01>; /* Hyp IRQ */
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interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
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<1 13 0xff08>, /* Non-secure Phys IRQ */
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<1 14 0xff08>, /* Virt IRQ */
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<1 15 0xff08>; /* Hyp IRQ */
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clock-frequency = <50000000>;
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};
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@ -0,0 +1,86 @@
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#include <dt-bindings/power/raspberrypi-power.h>
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/ {
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memory {
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device_type = "memory";
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reg = <0 0x10000000>;
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};
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leds {
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compatible = "gpio-leds";
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act {
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label = "ACT";
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default-state = "keep";
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linux,default-trigger = "heartbeat";
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};
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};
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soc {
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firmware: firmware {
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compatible = "raspberrypi,bcm2835-firmware";
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mboxes = <&mailbox>;
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};
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power: power {
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compatible = "raspberrypi,bcm2835-power";
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firmware = <&firmware>;
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#power-domain-cells = <1>;
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};
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};
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};
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&gpio {
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pinctrl-names = "default";
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gpioout: gpioout {
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brcm,pins = <6>;
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brcm,function = <BCM2835_FSEL_GPIO_OUT>;
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};
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alt0: alt0 {
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brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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alt3: alt3 {
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brcm,pins = <48 49 50 51 52 53>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&i2c2 {
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status = "okay";
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};
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&sdhci {
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status = "okay";
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bus-width = <4>;
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};
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&pwm {
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status = "okay";
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};
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&usb {
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power-domains = <&power RPI_POWER_DOMAIN_USB>;
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};
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&v3d {
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power-domains = <&power RPI_POWER_DOMAIN_V3D>;
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};
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&hdmi {
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power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
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status = "okay";
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};
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@ -1,7 +1,7 @@
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/dts-v1/;
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#include "bcm2837.dtsi"
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#include "../../../../arm/boot/dts/bcm2835-rpi.dtsi"
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#include "../../../../arm/boot/dts/bcm283x-rpi-smsc9514.dtsi"
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#include "bcm2835-rpi.dtsi"
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#include "bcm283x-rpi-smsc9514.dtsi"
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/ {
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compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
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@ -1,4 +1,4 @@
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#include "../../../../arm/boot/dts/bcm283x.dtsi"
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#include "bcm283x.dtsi"
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/ {
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compatible = "brcm,bcm2836";
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@ -0,0 +1,19 @@
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/ {
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aliases {
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ethernet = ðernet;
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};
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};
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&usb {
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usb1@1 {
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compatible = "usb424,9514";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet: usbether@1 {
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compatible = "usb424,ec00";
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reg = <1>;
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};
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};
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};
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@ -0,0 +1,321 @@
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#include <dt-bindings/pinctrl/bcm2835.h>
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#include <dt-bindings/clock/bcm2835.h>
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#include <dt-bindings/clock/bcm2835-aux.h>
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#include <dt-bindings/gpio/gpio.h>
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/* This include file covers the common peripherals and configuration between
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* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
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* bcm2835.dtsi and bcm2836.dtsi.
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*/
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/ {
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compatible = "brcm,bcm2835";
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model = "BCM2835";
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "earlyprintk console=ttyAMA0";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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timer@7e003000 {
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7e003000 0x1000>;
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interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
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/* This could be a reference to BCM2835_CLOCK_TIMER,
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* but we don't have the driver using the common clock
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* support yet.
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*/
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clock-frequency = <1000000>;
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};
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dma: dma@7e007000 {
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compatible = "brcm,bcm2835-dma";
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reg = <0x7e007000 0xf00>;
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interrupts = <1 16>,
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<1 17>,
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<1 18>,
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<1 19>,
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<1 20>,
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<1 21>,
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<1 22>,
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<1 23>,
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<1 24>,
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<1 25>,
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<1 26>,
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/* dma channel 11-14 share one irq */
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<1 27>,
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<1 27>,
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<1 27>,
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<1 27>,
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/* unused shared irq for all channels */
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<1 28>;
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interrupt-names = "dma0",
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"dma1",
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"dma2",
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"dma3",
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"dma4",
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"dma5",
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"dma6",
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"dma7",
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"dma8",
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"dma9",
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"dma10",
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"dma11",
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"dma12",
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"dma13",
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"dma14",
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"dma-shared-all";
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#dma-cells = <1>;
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brcm,dma-channel-mask = <0x7f35>;
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};
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intc: interrupt-controller@7e00b200 {
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compatible = "brcm,bcm2835-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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watchdog@7e100000 {
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compatible = "brcm,bcm2835-pm-wdt";
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reg = <0x7e100000 0x28>;
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};
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clocks: cprman@7e101000 {
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compatible = "brcm,bcm2835-cprman";
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#clock-cells = <1>;
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reg = <0x7e101000 0x2000>;
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/* CPRMAN derives everything from the platform's
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* oscillator.
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*/
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clocks = <&clk_osc>;
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};
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rng@7e104000 {
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compatible = "brcm,bcm2835-rng";
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reg = <0x7e104000 0x10>;
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};
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mailbox: mailbox@7e00b800 {
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compatible = "brcm,bcm2835-mbox";
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reg = <0x7e00b880 0x40>;
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interrupts = <0 1>;
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#mbox-cells = <0>;
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};
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gpio: gpio@7e200000 {
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compatible = "brcm,bcm2835-gpio";
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reg = <0x7e200000 0xb4>;
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/*
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* The GPIO IP block is designed for 3 banks of GPIOs.
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* Each bank has a GPIO interrupt for itself.
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* There is an overall "any bank" interrupt.
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* In order, these are GIC interrupts 17, 18, 19, 20.
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* Since the BCM2835 only has 2 banks, the 2nd bank
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* interrupt output appears to be mirrored onto the
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* 3rd bank's interrupt signal.
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* So, a bank0 interrupt shows up on 17, 20, and
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* a bank1 interrupt shows up on 18, 19, 20!
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*/
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interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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uart0: serial@7e201000 {
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compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
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reg = <0x7e201000 0x1000>;
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interrupts = <2 25>;
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clocks = <&clocks BCM2835_CLOCK_UART>,
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<&clocks BCM2835_CLOCK_VPU>;
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clock-names = "uartclk", "apb_pclk";
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arm,primecell-periphid = <0x00241011>;
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};
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i2s: i2s@7e203000 {
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compatible = "brcm,bcm2835-i2s";
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reg = <0x7e203000 0x20>,
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<0x7e101098 0x02>;
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dmas = <&dma 2>,
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<&dma 3>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi: spi@7e204000 {
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compatible = "brcm,bcm2835-spi";
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reg = <0x7e204000 0x1000>;
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interrupts = <2 22>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c0: i2c@7e205000 {
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compatible = "brcm,bcm2835-i2c";
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reg = <0x7e205000 0x1000>;
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interrupts = <2 21>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pixelvalve@7e206000 {
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compatible = "brcm,bcm2835-pixelvalve0";
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reg = <0x7e206000 0x100>;
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interrupts = <2 13>; /* pwa0 */
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};
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pixelvalve@7e207000 {
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compatible = "brcm,bcm2835-pixelvalve1";
|
||||
reg = <0x7e207000 0x100>;
|
||||
interrupts = <2 14>; /* pwa1 */
|
||||
};
|
||||
|
||||
aux: aux@0x7e215000 {
|
||||
compatible = "brcm,bcm2835-aux";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x7e215000 0x8>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
};
|
||||
|
||||
uart1: serial@7e215040 {
|
||||
compatible = "brcm,bcm2835-aux-uart";
|
||||
reg = <0x7e215040 0x40>;
|
||||
interrupts = <1 29>;
|
||||
clocks = <&aux BCM2835_AUX_CLOCK_UART>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@7e215080 {
|
||||
compatible = "brcm,bcm2835-aux-spi";
|
||||
reg = <0x7e215080 0x40>;
|
||||
interrupts = <1 29>;
|
||||
clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@7e2150c0 {
|
||||
compatible = "brcm,bcm2835-aux-spi";
|
||||
reg = <0x7e2150c0 0x40>;
|
||||
interrupts = <1 29>;
|
||||
clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@7e20c000 {
|
||||
compatible = "brcm,bcm2835-pwm";
|
||||
reg = <0x7e20c000 0x28>;
|
||||
clocks = <&clocks BCM2835_CLOCK_PWM>;
|
||||
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
|
||||
assigned-clock-rates = <10000000>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci: sdhci@7e300000 {
|
||||
compatible = "brcm,bcm2835-sdhci";
|
||||
reg = <0x7e300000 0x100>;
|
||||
interrupts = <2 30>;
|
||||
clocks = <&clocks BCM2835_CLOCK_EMMC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hvs@7e400000 {
|
||||
compatible = "brcm,bcm2835-hvs";
|
||||
reg = <0x7e400000 0x6000>;
|
||||
interrupts = <2 1>;
|
||||
};
|
||||
|
||||
i2c1: i2c@7e804000 {
|
||||
compatible = "brcm,bcm2835-i2c";
|
||||
reg = <0x7e804000 0x1000>;
|
||||
interrupts = <2 21>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@7e805000 {
|
||||
compatible = "brcm,bcm2835-i2c";
|
||||
reg = <0x7e805000 0x1000>;
|
||||
interrupts = <2 21>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pixelvalve@7e807000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve2";
|
||||
reg = <0x7e807000 0x100>;
|
||||
interrupts = <2 10>; /* pixelvalve */
|
||||
};
|
||||
|
||||
hdmi: hdmi@7e902000 {
|
||||
compatible = "brcm,bcm2835-hdmi";
|
||||
reg = <0x7e902000 0x600>,
|
||||
<0x7e808000 0x100>;
|
||||
interrupts = <2 8>, <2 9>;
|
||||
ddc = <&i2c2>;
|
||||
clocks = <&clocks BCM2835_PLLH_PIX>,
|
||||
<&clocks BCM2835_CLOCK_HSM>;
|
||||
clock-names = "pixel", "hdmi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb: usb@7e980000 {
|
||||
compatible = "brcm,bcm2835-usb";
|
||||
reg = <0x7e980000 0x10000>;
|
||||
interrupts = <1 9>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
v3d: v3d@7ec00000 {
|
||||
compatible = "brcm,bcm2835-v3d";
|
||||
reg = <0x7ec00000 0x1000>;
|
||||
interrupts = <1 10>;
|
||||
};
|
||||
|
||||
vc4: gpu {
|
||||
compatible = "brcm,bcm2835-vc4";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* The oscillator is the root of the clock tree. */
|
||||
clk_osc: clock@3 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "osc";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
|
@ -88,13 +88,13 @@
|
|||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
|
||||
IRQ_TYPE_EDGE_RISING)>,
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
|
||||
IRQ_TYPE_EDGE_RISING)>,
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
|
||||
IRQ_TYPE_EDGE_RISING)>,
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
|
||||
IRQ_TYPE_EDGE_RISING)>;
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
|
|
|
@ -354,10 +354,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xff01>,
|
||||
<1 14 0xff01>,
|
||||
<1 11 0xff01>,
|
||||
<1 10 0xff01>;
|
||||
interrupts = <1 13 4>,
|
||||
<1 14 4>,
|
||||
<1 11 4>,
|
||||
<1 10 4>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
|
|
|
@ -473,10 +473,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xff01>,
|
||||
<1 14 0xff01>,
|
||||
<1 11 0xff01>,
|
||||
<1 10 0xff01>;
|
||||
interrupts = <1 13 0xff08>,
|
||||
<1 14 0xff08>,
|
||||
<1 11 0xff08>,
|
||||
<1 10 0xff08>;
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@105c0000 {
|
||||
|
|
|
@ -119,10 +119,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0x1>, /* Physical Secure PPI */
|
||||
<1 14 0x1>, /* Physical Non-Secure PPI */
|
||||
<1 11 0x1>, /* Virtual PPI */
|
||||
<1 10 0x1>; /* Hypervisor PPI */
|
||||
interrupts = <1 13 0xf08>, /* Physical Secure PPI */
|
||||
<1 14 0xf08>, /* Physical Non-Secure PPI */
|
||||
<1 11 0xf08>, /* Virtual PPI */
|
||||
<1 10 0xf08>; /* Hypervisor PPI */
|
||||
};
|
||||
|
||||
pmu {
|
||||
|
|
|
@ -191,10 +191,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
|
||||
<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
|
||||
<1 11 0x8>, /* Virtual PPI, active-low */
|
||||
<1 10 0x8>; /* Hypervisor PPI, active-low */
|
||||
interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
|
||||
<1 14 4>, /* Physical Non-Secure PPI, active-low */
|
||||
<1 11 4>, /* Virtual PPI, active-low */
|
||||
<1 10 4>; /* Hypervisor PPI, active-low */
|
||||
};
|
||||
|
||||
pmu {
|
||||
|
|
|
@ -122,10 +122,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
odmi: odmi@300000 {
|
||||
|
|
|
@ -129,10 +129,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xf01>,
|
||||
<1 14 0xf01>,
|
||||
<1 11 0xf01>,
|
||||
<1 10 0xf01>;
|
||||
interrupts = <1 13 4>,
|
||||
<1 14 4>,
|
||||
<1 11 4>,
|
||||
<1 10 4>;
|
||||
};
|
||||
|
||||
soc {
|
||||
|
|
|
@ -65,10 +65,10 @@
|
|||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 13 0xf01>,
|
||||
<1 14 0xf01>,
|
||||
<1 11 0xf01>,
|
||||
<1 10 0xf01>;
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
amba_apu {
|
||||
|
|
Loading…
Reference in New Issue