re-enable uart initialization
This commit is contained in:
Sascha Hauer
parent
36b3e1fc5a
commit
ca99316c68
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@ -19,6 +19,7 @@
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <driver.h>
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#include <init.h>
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#include <malloc.h>
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@ -47,9 +48,96 @@
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#define BMPR4(base) __REG( 0xcc +(base)) /* BRM Modulator Register 4 */
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#define UTS(base) __REG( 0xd0 +(base)) /* UART Test Register */
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
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/* UART Control Register Bit Fields.*/
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#define URXD_CHARRDY (1<<15)
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#define URXD_ERR (1<<14)
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#define URXD_OVRRUN (1<<13)
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#define URXD_FRMERR (1<<12)
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#define URXD_BRK (1<<11)
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#define URXD_PRERR (1<<10)
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#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
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#define UCR1_IREN (1<<7) /* Infrared interface enable */
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#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
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#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
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#define UCR2_CTSC (1<<13) /* CTS pin control */
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#define UCR2_CTS (1<<12) /* Clear to send */
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#define UCR2_ESCEN (1<<11) /* Escape enable */
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#define UCR2_PREN (1<<8) /* Parity enable */
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#define UCR2_PROE (1<<7) /* Parity odd/even */
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#define UCR2_STPB (1<<6) /* Stop */
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#define UCR2_WS (1<<5) /* Word size */
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */
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#define UCR2_RXEN (1<<1) /* Receiver enabled */
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#define UCR2_SRST (1<<0) /* SW reset */
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
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#define UCR3_PARERREN (1<<12) /* Parity enable */
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
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#define UCR3_DSR (1<<10) /* Data set ready */
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#define UCR3_DCD (1<<9) /* Data carrier detect */
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#define UCR3_RI (1<<8) /* Ring indicator */
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
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#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
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#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
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#define USR1_RTSD (1<<12) /* RTS delta */
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
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#define USR2_IDLE (1<<12) /* Idle condition */
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
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#define USR2_WAKE (1<<7) /* Wake */
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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#define USR2_BRCD (1<<2) /* Break condition */
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#define USR2_ORE (1<<1) /* Overrun error */
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#define USR2_RDR (1<<0) /* Recv data ready */
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#define UTS_FRCPERR (1<<13) /* Force parity error */
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#define UTS_LOOP (1<<12) /* Loop tx and rx */
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
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#define UTS_RXFULL (1<<3) /* RxFIFO full */
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#define UTS_SOFTRST (1<<0) /* Software reset */
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extern void imx_gpio_mode(int gpio_mode);
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@ -60,51 +148,27 @@ extern void imx_gpio_mode(int gpio_mode);
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*/
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static int imx_serial_init_port(struct console_device *cdev)
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{
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#if 0
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volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
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struct device_d *dev = cdev->dev;
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ulong base = dev->map_base;
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/* Disable UART */
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base->ucr1 &= ~UCR1_UARTEN;
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/* Set to default POR state */
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base->ucr1 = 0x00000004;
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base->ucr2 = 0x00000000;
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base->ucr3 = 0x00000000;
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base->ucr4 = 0x00008040;
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base->uesc = 0x0000002B;
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base->utim = 0x00000000;
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base->ubir = 0x00000000;
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base->ubmr = 0x00000000;
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base->uts = 0x00000000;
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/* Set clocks */
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base->ucr4 |= UCR4_REF16;
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UCR1(base) = UCR1_UARTCLKEN;
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UCR2(base) = UCR2_WS | UCR2_IRTS;
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UCR3(base) = 0;
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UCR4(base) = UCR4_CTSTL_32 | UCR4_REF16;
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UESC(base) = 0x0000002B;
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UTIM(base) = 0;
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UBIR(base) = 0;
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UBMR(base) = 0;
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UTS(base) = 0;
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/* Configure FIFOs */
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base->ufcr = 0xa81;
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/* Set the numerator value minus one of the BRM ratio */
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base->ubir = (CONFIG_BAUDRATE / 100) - 1;
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/* Set the denominator value minus one of the BRM ratio */
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base->ubmr = 10000 - 1;
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/* Set to 8N1 */
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base->ucr2 &= ~UCR2_PREN;
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base->ucr2 |= UCR2_WS;
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base->ucr2 &= ~UCR2_STPB;
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/* Ignore RTS */
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base->ucr2 |= UCR2_IRTS;
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/* Enable UART */
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base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN;
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UFCR(base) = 0xa81;
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/* Enable FIFOs */
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base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
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UCR2(base) |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
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/* Clear status flags */
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base->usr2 |= USR2_ADET |
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USR2(base) |= USR2_ADET |
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USR2_DTRF |
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USR2_IDLE |
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USR2_IRINT |
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@ -115,13 +179,13 @@ static int imx_serial_init_port(struct console_device *cdev)
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USR2_RDR;
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/* Clear status flags */
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base->usr1 |= USR1_PARITYERR |
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USR1(base) |= USR1_PARITYERR |
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USR1_RTSD |
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USR1_ESCF |
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USR1_FRAMERR |
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USR1_AIRINT |
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USR1_AWAKE;
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#endif
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return 0;
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}
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@ -148,16 +212,32 @@ static int imx_serial_tstc(struct console_device *cdev)
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static int imx_serial_getc(struct console_device *cdev)
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{
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struct device_d *dev = cdev->dev;
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unsigned char ch;
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while(UTS(dev->map_base) & UTS_RXEMPTY);
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while (UTS(dev->map_base) & UTS_RXEMPTY);
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ch = URXD0(dev->map_base);
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return ch;
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}
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static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate)
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{
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struct device_d *dev = cdev->dev;
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ulong base = dev->map_base;
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ulong ucr1 = UCR1(base);
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/* disable UART */
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UCR1(base) &= ~UCR1_UARTEN;
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UBIR(base) = 15;
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UBMR(base) = imx_get_perclk1() / baudrate;
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UCR1(base) = ucr1;
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return 0;
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}
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static int imx_serial_probe(struct device_d *dev)
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{
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struct console_device *cdev;
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@ -169,8 +249,13 @@ static int imx_serial_probe(struct device_d *dev)
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cdev->tstc = imx_serial_tstc;
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cdev->putc = imx_serial_putc;
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cdev->getc = imx_serial_getc;
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cdev->setbrg = imx_serial_setbaudrate;
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imx_serial_init_port(cdev);
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imx_serial_setbaudrate(cdev, 115200);
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/* Enable UART */
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UCR1(cdev->dev->map_base) |= UCR1_UARTEN;
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console_register(cdev);
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