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barebox
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Merge branch 'for-next/arm'

This commit is contained in:
Sascha Hauer 2013-09-05 10:11:25 +02:00
parent 7dc1b15e08 20e9bc17d4
commit caeb8a933f
16 changed files with 55 additions and 76 deletions
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2
arch/arm/boards/a9m2410/lowlevel_init.S
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@ -12,7 +12,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
bl s3c24x0_disable_wd

2
arch/arm/boards/a9m2440/lowlevel_init.S
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@ -216,7 +216,7 @@ SDRAMDATA:
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
bl s3c24x0_disable_wd

2
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
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@ -74,7 +74,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)

2
arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
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@ -51,7 +51,7 @@ CCM_BASE_ADDR_W: .word MX25_CCM_BASE_ADDR
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
#define MX25_CCM_MCR 0x64

2
arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
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@ -58,7 +58,7 @@ CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
mrc 15, 0, r1, c1, c0, 0

2
arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S
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@ -13,7 +13,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
bl s3c24x0_disable_wd

2
arch/arm/boards/imx21ads/lowlevel_init.S
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@ -24,7 +24,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
/*
* Initialize the AHB-Lite IP Interface (AIPI) module (to enable access to

2
arch/arm/boards/imx27ads/lowlevel_init.S
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@ -52,7 +52,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)

2
arch/arm/boards/netx/platform.S
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@ -21,7 +21,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
mov r0, #0x80000000
mov r1, #SZ_64M
mov r2, #0

2
arch/arm/boards/pcm027/lowlevel_init.S
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@ -54,7 +54,7 @@
*/
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
@ Preserve r8/r7 i.e. kernel entry values

2
arch/arm/boards/phycard-i.MX27/lowlevel_init.S
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@ -68,7 +68,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)

2
arch/arm/boards/scb9328/lowlevel_init.S
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@ -28,7 +28,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
/* Change PERCLK1DIV to 14 ie 14+1 */
writel(CFG_PCDR_VAL, MX1_CCM_BASE_ADDR + MX1_PCDR)

2
arch/arm/cpu/Makefile
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@ -27,3 +27,5 @@ pbl-$(CONFIG_PBL_MULTI_IMAGES) += start-images.o uncompress.o
obj-y += common.o
pbl-y += common.o
lwl-y += lowlevel.o

39
arch/arm/cpu/lowlevel.S Normal file
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@ -0,0 +1,39 @@
#include <linux/linkage.h>
#include <init.h>
#include <asm/system.h>
.section ".text_bare_init_","ax"
ENTRY(arm_cpu_lowlevel_init)
/* set the cpu to SVC32 mode */
mrs r12, cpsr
bic r12, r12, #0x1f
orr r12, r12, #0xd3
msr cpsr, r12
#if __LINUX_ARM_ARCH__ >= 7
isb
#elif __LINUX_ARM_ARCH__ == 6
mcr p15, 0, r12, c7, c5, 4
#endif
/* disable MMU stuff and caches */
mrc p15, 0, r12, c1, c0, 0
bic r12, r12 , #(CR_M | CR_C | CR_B)
bic r12, r12, #(CR_S | CR_R | CR_V)
orr r12, r12, #CR_I
#if __LINUX_ARM_ARCH__ >= 6
orr r12, r12, #CR_U
bic r12, r12, #CR_A
#else
orr r12, r12, #CR_A
#endif
#ifdef __ARMEB__
orr r12, r12, #CR_B
#endif
mcr p15, 0, r12, c1, c0, 0
mov pc, lr
ENDPROC(arm_cpu_lowlevel_init)

64
arch/arm/include/asm/barebox-arm-head.h
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@ -5,33 +5,7 @@
#ifndef __ASSEMBLY__
static inline void arm_cpu_lowlevel_init(void)
{
uint32_t r;
/* set the cpu to SVC32 mode */
__asm__ __volatile__("mrs %0, cpsr":"=r"(r));
r &= ~0x1f;
r |= 0xd3;
__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
/* disable MMU stuff and caches */
r = get_cr();
r &= ~(CR_M | CR_C | CR_B | CR_S | CR_R | CR_V);
r |= CR_I;
#if __LINUX_ARM_ARCH__ >= 6
r |= CR_U;
r &= ~CR_A;
#else
r |= CR_A;
#endif
#ifdef __ARMEB__
r |= CR_B;
#endif
set_cr(r);
}
void arm_cpu_lowlevel_init(void);
/*
* 32 bytes at this offset is reserved in the barebox head for board/SoC
@ -86,42 +60,6 @@ static inline void barebox_arm_head(void)
}
#endif
#else
.macro arm_cpu_lowlevel_init, scratch
/* set the cpu to SVC32 mode */
mrs \scratch, cpsr
bic \scratch, \scratch, #0x1f
orr \scratch, \scratch, #0xd3
msr cpsr, \scratch
#if __LINUX_ARM_ARCH__ >= 7
isb
#elif __LINUX_ARM_ARCH__ == 6
mcr p15, 0, \scratch, c7, c5, 4
#endif
/* disable MMU stuff and caches */
mrc p15, 0, \scratch, c1, c0, 0
bic \scratch, \scratch , #(CR_M | CR_C | CR_B)
bic \scratch, \scratch, #(CR_S | CR_R | CR_V)
orr \scratch, \scratch, #CR_I
#if __LINUX_ARM_ARCH__ >= 6
orr \scratch, \scratch, #CR_U
bic \scratch, \scratch, #CR_A
#else
orr \scratch, \scratch, #CR_A
#endif
#ifdef __ARMEB__
orr \scratch, \scratch, #CR_B
#endif
mcr p15, 0, \scratch, c1, c0, 0
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_HEAD_H */

2
arch/arm/mach-ep93xx/lowlevel_init.S
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@ -26,7 +26,7 @@
.globl barebox_arm_reset_vector
barebox_arm_reset_vector:
arm_cpu_lowlevel_init r0
bl arm_cpu_lowlevel_init
/* Turn on both LEDs */
bl red_LED_on