dts: update to v4.10-rc6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -15,6 +15,9 @@ Properties:
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Second cell specifies the irq distribution mode to cores
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0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
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The second cell in interrupts property is deprecated and may be ignored by
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the kernel.
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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@ -7,7 +7,7 @@ have dual GMAC each represented by a child node..
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* Ethernet controller node
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Required properties:
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- compatible: Should be "mediatek,mt7623-eth"
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- compatible: Should be "mediatek,mt2701-eth"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the three frame engines interrupts in numeric
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order. These are fe_int0, fe_int1 and fe_int2.
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@ -19,8 +19,9 @@ Optional Properties:
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specifications. If neither of these are specified, the default is to
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assume clause 22.
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If the phy's identifier is known then the list may contain an entry
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of the form: "ethernet-phy-idAAAA.BBBB" where
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If the PHY reports an incorrect ID (or none at all) then the
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"compatible" list may contain an entry with the correct PHY ID in the
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form: "ethernet-phy-idAAAA.BBBB" where
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AAAA - The value of the 16 bit Phy Identifier 1 register as
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4 hex digits. This is the chip vendor OUI bits 3:18
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BBBB - The value of the 16 bit Phy Identifier 2 register as
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