Remove all ARM __raw_* functions. They are mixed all over
the place. This clean up all ARM architectures to use only one set of io functions. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
This commit is contained in:
Juergen Beisert
parent
2148865ac9
commit
cd175ec7d2
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@ -25,7 +25,7 @@
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.section .text.readsb
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ENTRY(__raw_readsb)
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ENTRY(readsb)
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teq r2, #0 @ do we have to check for the zero len?
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moveq pc, lr
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ands ip, r1, #3
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@ -122,4 +122,4 @@ ENTRY(__raw_readsb)
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strgtb r3, [r1]
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(__raw_readsb)
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ENDPROC(readsb)
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@ -26,7 +26,7 @@
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sub r2, r2, #1
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strh ip, [r1], #2
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ENTRY(__raw_readsw)
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ENTRY(readsw)
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teq r2, #0
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moveq pc, lr
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tst r1, #3
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@ -130,4 +130,4 @@ ENTRY(__raw_readsw)
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_BE_ONLY_( movne ip, ip, lsr #24 )
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strneb ip, [r1]
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ldmfd sp!, {r4, pc}
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ENDPROC(__raw_readsw)
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ENDPROC(readsw)
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@ -45,7 +45,7 @@
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subs r2, r2, ip
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bne .Loutsb_aligned
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ENTRY(__raw_writesb)
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ENTRY(writesb)
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teq r2, #0 @ do we have to check for the zero len?
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moveq pc, lr
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ands ip, r1, #3
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@ -93,4 +93,4 @@ ENTRY(__raw_writesb)
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strgtb r3, [r0]
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ldmfd sp!, {r4, r5, pc}
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ENDPROC(__raw_writesb)
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ENDPROC(writesb)
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@ -31,7 +31,7 @@
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sub r2, r2, #1
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strh r3, [r0]
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ENTRY(__raw_writesw)
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ENTRY(writesw)
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teq r2, #0
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moveq pc, lr
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ands r3, r1, #3
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@ -96,4 +96,4 @@ ENTRY(__raw_writesw)
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3: movne ip, r3, lsr #8
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strneh ip, [r0]
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mov pc, lr
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ENDPROC(__raw_writesw)
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ENDPROC(writesw)
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@ -85,10 +85,10 @@ int at91_set_gpio_input(unsigned pin, int use_pullup)
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + OFS_PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? OFS_PIO_PUER : OFS_PIO_PUDR));
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__raw_writel(mask, pio + OFS_PIO_ODR);
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__raw_writel(mask, pio + OFS_PIO_PER);
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writel(mask, pio + OFS_PIO_IDR);
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writel(mask, pio + (use_pullup ? OFS_PIO_PUER : OFS_PIO_PUDR));
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writel(mask, pio + OFS_PIO_ODR);
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writel(mask, pio + OFS_PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_input);
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@ -105,11 +105,11 @@ int at91_set_gpio_output(unsigned pin, int value)
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + OFS_PIO_IDR);
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__raw_writel(mask, pio + OFS_PIO_PUDR);
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__raw_writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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__raw_writel(mask, pio + OFS_PIO_OER);
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__raw_writel(mask, pio + OFS_PIO_PER);
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writel(mask, pio + OFS_PIO_IDR);
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writel(mask, pio + OFS_PIO_PUDR);
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writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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writel(mask, pio + OFS_PIO_OER);
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writel(mask, pio + OFS_PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_output);
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@ -119,9 +119,9 @@ int gpio_direction_input(unsigned pin)
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !(__raw_readl(pio + OFS_PIO_PSR) & mask))
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if (!pio || !(readl(pio + OFS_PIO_PSR) & mask))
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return -EINVAL;
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__raw_writel(mask, pio + OFS_PIO_ODR);
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writel(mask, pio + OFS_PIO_ODR);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_input);
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@ -131,10 +131,10 @@ int gpio_direction_output(unsigned pin, int value)
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio || !(__raw_readl(pio + OFS_PIO_PSR) & mask))
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if (!pio || !(readl(pio + OFS_PIO_PSR) & mask))
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return -EINVAL;
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__raw_writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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__raw_writel(mask, pio + OFS_PIO_OER);
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writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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writel(mask, pio + OFS_PIO_OER);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_output);
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@ -151,7 +151,7 @@ void gpio_set_value(unsigned pin, int value)
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if (!pio)
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return;
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__raw_writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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}
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EXPORT_SYMBOL(gpio_set_value);
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@ -167,7 +167,7 @@ int gpio_get_value(unsigned pin)
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if (!pio)
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return -EINVAL;
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pdsr = __raw_readl(pio + OFS_PIO_PDSR);
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pdsr = readl(pio + OFS_PIO_PDSR);
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return (pdsr & mask) != 0;
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}
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EXPORT_SYMBOL(gpio_get_value);
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@ -54,20 +54,20 @@ void gpmc_generic_init(unsigned int cfg)
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debug("gpmccfg=%x\n", cfg);
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/* Generic Configurations */
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/* No idle, L3 clock free running */
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__raw_writel(0x10, GPMC_REG(SYS_CONFIG));
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writel(0x10, GPMC_REG(SYS_CONFIG));
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/* No Timeout */
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__raw_writel(0x00, GPMC_REG(TIMEOUT_CONTROL));
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writel(0x00, GPMC_REG(TIMEOUT_CONTROL));
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/* No IRQs */
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__raw_writel(0x00, GPMC_REG(IRQ_ENABLE));
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writel(0x00, GPMC_REG(IRQ_ENABLE));
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/* Write the gpmc_config value */
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__raw_writel(cfg, GPMC_REG(CFG));
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writel(cfg, GPMC_REG(CFG));
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/* Disable all CS - prevents remaps
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* But NEVER run me in XIP mode! I will Die!
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*/
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while (x < GPMC_NUM_CS) {
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debug("gpmccs=%d Reg:%x <-0x0\n", x, reg);
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__raw_writel(0x0, reg);
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writel(0x0, reg);
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reg += GPMC_CONFIG_CS_SIZE;
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x++;
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}
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@ -91,14 +91,14 @@ void gpmc_cs_config(char cs, struct gpmc_config *config)
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debug("gpmccs=%x cfg=%x\n", cs, (unsigned int)config);
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/* Disable the CS before reconfiguring */
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__raw_writel(0x0, GPMC_REG(CONFIG7_0) + (cs * GPMC_CONFIG_CS_SIZE));
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writel(0x0, GPMC_REG(CONFIG7_0) + (cs * GPMC_CONFIG_CS_SIZE));
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mdelay(1); /* Settling time */
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/* Write the CFG1-6 regs */
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while (x < 6) {
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debug("gpmccfg=%d Reg:%x <-0x%x\n",
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x, reg, config->cfg[x]);
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__raw_writel(config->cfg[x], reg);
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writel(config->cfg[x], reg);
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reg += GPMC_CONFIG_REG_OFF;
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x++;
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}
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@ -108,7 +108,7 @@ void gpmc_cs_config(char cs, struct gpmc_config *config)
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((config->size & 0xF) << 8) | /* Size */
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((config->base >> 24) & 0x3F));
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__raw_writel((0x1 << 6) | /* CS enable */
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writel((0x1 << 6) | /* CS enable */
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((config->size & 0xF) << 8) | /* Size */
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((config->base >> 24) & 0x3F), /* Address */
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reg);
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@ -67,34 +67,34 @@ static u32 get_osc_clk_speed(void)
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{
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u32 start, cstart, cend, cdiff, val;
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val = __raw_readl(PRM_REG(CLKSRC_CTRL));
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val = readl(PRM_REG(CLKSRC_CTRL));
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/* If SYS_CLK is being divided by 2, remove for now */
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val = (val & (~(0x1 << 7))) | (0x1 << 6);
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__raw_writel(val, PRM_REG(CLKSRC_CTRL));
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writel(val, PRM_REG(CLKSRC_CTRL));
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/* enable timer2 */
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val = __raw_readl(CM_REG(CLKSEL_WKUP)) | (0x1 << 0);
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__raw_writel(val, CM_REG(CLKSEL_WKUP)); /* select sys_clk for GPT1 */
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val = readl(CM_REG(CLKSEL_WKUP)) | (0x1 << 0);
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writel(val, CM_REG(CLKSEL_WKUP)); /* select sys_clk for GPT1 */
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/* Enable I and F Clocks for GPT1 */
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val = __raw_readl(CM_REG(ICLKEN_WKUP)) | (0x1 << 0) | (0x1 << 2);
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__raw_writel(val, CM_REG(ICLKEN_WKUP));
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val = __raw_readl(CM_REG(FCLKEN_WKUP)) | (0x1 << 0);
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__raw_writel(val, CM_REG(FCLKEN_WKUP));
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val = readl(CM_REG(ICLKEN_WKUP)) | (0x1 << 0) | (0x1 << 2);
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writel(val, CM_REG(ICLKEN_WKUP));
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val = readl(CM_REG(FCLKEN_WKUP)) | (0x1 << 0);
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writel(val, CM_REG(FCLKEN_WKUP));
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/* start counting at 0 */
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__raw_writel(0, OMAP_GPTIMER1_BASE + TLDR);
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writel(0, OMAP_GPTIMER1_BASE + TLDR);
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/* enable clock */
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__raw_writel(GPT_EN, OMAP_GPTIMER1_BASE + TCLR);
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writel(GPT_EN, OMAP_GPTIMER1_BASE + TCLR);
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/* enable 32kHz source - enabled out of reset */
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/* determine sys_clk via gauging */
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start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
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while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
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start = 20 + readl(S32K_CR); /* start time in 20 cycles */
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while (readl(S32K_CR) < start) ; /* dead loop till start time */
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/* get start sys_clk count */
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cstart = __raw_readl(OMAP_GPTIMER1_BASE + TCRR);
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while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
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cstart = readl(OMAP_GPTIMER1_BASE + TCRR);
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while (readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
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/* get end sys_clk count */
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cend = __raw_readl(OMAP_GPTIMER1_BASE + TCRR);
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cend = readl(OMAP_GPTIMER1_BASE + TCRR);
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cdiff = cend - cstart; /* get elapsed ticks */
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/* based on number of ticks assign speed */
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@ -219,16 +219,16 @@ void prcm_init(void)
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/* if running from flash,
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* jump to small relocated code area in SRAM.
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*/
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p0 = __raw_readl(CM_REG(CLKEN_PLL));
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p0 = readl(CM_REG(CLKEN_PLL));
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sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
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sr32((u32) &p0, 4, 4, dpll_param_p->fsel);
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p1 = __raw_readl(CM_REG(CLKSEL1_PLL));
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p1 = readl(CM_REG(CLKSEL1_PLL));
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sr32((u32) &p1, 27, 2, dpll_param_p->m2);
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sr32((u32) &p1, 16, 11, dpll_param_p->m);
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sr32((u32) &p1, 8, 7, dpll_param_p->n);
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sr32((u32) &p1, 6, 1, 0); /* set source for 96M */
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p2 = __raw_readl(CM_REG(CLKSEL_CORE));
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p2 = readl(CM_REG(CLKSEL_CORE));
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sr32((u32) &p2, 8, 4, CORE_SSI_DIV);
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sr32((u32) &p2, 4, 2, CORE_FUSB_DIV);
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sr32((u32) &p2, 2, 2, CORE_L4_DIV);
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@ -82,7 +82,7 @@ u32 get_cpu_type(void)
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u32 get_cpu_rev(void)
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{
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u32 idcode_val;
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idcode_val = __raw_readl(IDCODE_REG);
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idcode_val = readl(IDCODE_REG);
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if ((idcode_val & (HAWKEYE_MASK | VERSION_MASK)) == HAWKEYE_ES2_1)
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return CPU_ES2P1;
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if ((idcode_val & HAWKEYE_MASK) == HAWKEYE_ES2)
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@ -102,7 +102,7 @@ u32 get_sdr_cs_size(u32 offset)
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{
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u32 size;
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/* get ram size field */
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size = __raw_readl(SDRC_REG(MCFG_0) + offset) >> 8;
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size = readl(SDRC_REG(MCFG_0) + offset) >> 8;
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size &= 0x3FF; /* remove unwanted bits */
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size *= 2 * (1024 * 1024); /* find size in MB */
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return size;
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@ -117,7 +117,7 @@ u32 get_sdr_cs_size(u32 offset)
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*/
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inline u32 get_sysboot_value(void)
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{
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return (0x0000003F & __raw_readl(CONTROL_REG(STATUS)));
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return (0x0000003F & readl(CONTROL_REG(STATUS)));
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}
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/**
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@ -133,7 +133,7 @@ inline u32 get_sysboot_value(void)
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u32 get_gpmc0_base(void)
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{
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u32 b;
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b = __raw_readl(GPMC_REG(CONFIG7_0));
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b = readl(GPMC_REG(CONFIG7_0));
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b &= 0x1F; /* keep base [5:0] */
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b = b << 24; /* ret 0x0b000000 */
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return b;
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@ -225,7 +225,7 @@ u32 get_boot_type(void)
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u32 get_device_type(void)
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{
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int mode;
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mode = __raw_readl(CONTROL_REG(STATUS)) & (DEVICE_MASK);
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mode = readl(CONTROL_REG(STATUS)) & (DEVICE_MASK);
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return (mode >>= 8);
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}
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@ -243,26 +243,26 @@ static void secure_unlock_mem(void)
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#define UNLOCK_2 0x00000000
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#define UNLOCK_3 0x0000FFFF
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/* Protection Module Register Target APE (PM_RT) */
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__raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
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__raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
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__raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
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__raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
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writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
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writel(UNLOCK_1, RT_READ_PERMISSION_0);
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writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
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writel(UNLOCK_2, RT_ADDR_MATCH_1);
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__raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
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__raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
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__raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
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writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
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writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
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writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
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__raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
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__raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
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__raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
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__raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
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writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
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writel(UNLOCK_3, OCM_READ_PERMISSION_0);
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writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
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writel(UNLOCK_2, OCM_ADDR_MATCH_2);
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/* IVA Changes */
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__raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
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__raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
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__raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
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writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
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writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
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writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
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__raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
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writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
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}
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/**
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@ -314,13 +314,13 @@ static void watchdog_init(void)
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sr32(CM_REG(ICLKEN_WKUP), 5, 1, 1);
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wait_on_value((0x1 << 5), 0x20, CM_REG(IDLEST_WKUP), 5);
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__raw_writel(WDT_DISABLE_CODE1, WDT_REG(WSPR));
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writel(WDT_DISABLE_CODE1, WDT_REG(WSPR));
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do {
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pending = __raw_readl(WDT_REG(WWPS));
|
||||
pending = readl(WDT_REG(WWPS));
|
||||
} while (pending);
|
||||
|
||||
__raw_writel(WDT_DISABLE_CODE2, WDT_REG(WSPR));
|
||||
writel(WDT_DISABLE_CODE2, WDT_REG(WSPR));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -427,7 +427,7 @@ unsigned int omap_uart_read(unsigned long base, unsigned char reg_idx)
|
|||
{
|
||||
unsigned int *reg_addr = (unsigned int *)base;
|
||||
reg_addr += reg_idx;
|
||||
return __raw_readb(reg_addr);
|
||||
return readb(reg_addr);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_uart_read);
|
||||
|
||||
|
|
@ -445,6 +445,6 @@ void omap_uart_write(unsigned int val, unsigned long base,
|
|||
{
|
||||
unsigned int *reg_addr = (unsigned int *)base;
|
||||
reg_addr += reg_idx;
|
||||
__raw_writeb(val, reg_addr);
|
||||
writeb(val, reg_addr);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_uart_write);
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
*/
|
||||
static uint64_t s32k_clocksource_read(void)
|
||||
{
|
||||
return __raw_readl(S32K_CR);
|
||||
return readl(S32K_CR);
|
||||
}
|
||||
|
||||
/* A bit obvious isn't it? */
|
||||
|
|
|
|||
|
|
@ -66,9 +66,9 @@ void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
|
|||
u32 tmp, msk = 0;
|
||||
msk = 1 << num_bits;
|
||||
--msk;
|
||||
tmp = __raw_readl(addr) & ~(msk << start_bit);
|
||||
tmp = readl(addr) & ~(msk << start_bit);
|
||||
tmp |= value << start_bit;
|
||||
__raw_writel(tmp, addr);
|
||||
writel(tmp, addr);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -87,7 +87,7 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
|
|||
u32 i = 0, val;
|
||||
do {
|
||||
++i;
|
||||
val = __raw_readl(read_addr) & read_bit_mask;
|
||||
val = readl(read_addr) & read_bit_mask;
|
||||
if (val == match_value)
|
||||
return 1;
|
||||
if (i == bound)
|
||||
|
|
|
|||
|
|
@ -73,47 +73,47 @@ static void sdrc_init(void)
|
|||
{
|
||||
/* SDRAM software reset */
|
||||
/* No idle ack and RESET enable */
|
||||
__raw_writel(0x1A, SDRC_REG(SYSCONFIG));
|
||||
writel(0x1A, SDRC_REG(SYSCONFIG));
|
||||
sdelay(100);
|
||||
/* No idle ack and RESET disable */
|
||||
__raw_writel(0x18, SDRC_REG(SYSCONFIG));
|
||||
writel(0x18, SDRC_REG(SYSCONFIG));
|
||||
|
||||
/* SDRC Sharing register */
|
||||
/* 32-bit SDRAM on data lane [31:0] - CS0 */
|
||||
/* pin tri-stated = 1 */
|
||||
__raw_writel(0x00000100, SDRC_REG(SHARING));
|
||||
writel(0x00000100, SDRC_REG(SHARING));
|
||||
|
||||
/* ----- SDRC Registers Configuration --------- */
|
||||
/* SDRC_MCFG0 register */
|
||||
__raw_writel(0x02584099, SDRC_REG(MCFG_0));
|
||||
writel(0x02584099, SDRC_REG(MCFG_0));
|
||||
|
||||
/* SDRC_RFR_CTRL0 register */
|
||||
__raw_writel(0x54601, SDRC_REG(RFR_CTRL_0));
|
||||
writel(0x54601, SDRC_REG(RFR_CTRL_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLA0 register */
|
||||
__raw_writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
|
||||
writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLB0 register */
|
||||
__raw_writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
|
||||
writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
|
||||
|
||||
/* Disble Power Down of CKE due to 1 CKE on combo part */
|
||||
__raw_writel(0x00000081, SDRC_REG(POWER));
|
||||
writel(0x00000081, SDRC_REG(POWER));
|
||||
|
||||
/* SDRC_MANUAL command register */
|
||||
/* NOP command */
|
||||
__raw_writel(0x00000000, SDRC_REG(MANUAL_0));
|
||||
writel(0x00000000, SDRC_REG(MANUAL_0));
|
||||
/* Precharge command */
|
||||
__raw_writel(0x00000001, SDRC_REG(MANUAL_0));
|
||||
writel(0x00000001, SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
|
||||
writel(0x00000002, SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
|
||||
writel(0x00000002, SDRC_REG(MANUAL_0));
|
||||
|
||||
/* SDRC MR0 register Burst length=4 */
|
||||
__raw_writel(0x00000032, SDRC_REG(MR_0));
|
||||
writel(0x00000032, SDRC_REG(MR_0));
|
||||
|
||||
/* SDRC DLLA control register */
|
||||
__raw_writel(0x0000000A, SDRC_REG(DLLA_CTRL));
|
||||
writel(0x0000000A, SDRC_REG(DLLA_CTRL));
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -86,54 +86,54 @@ void board_init(void)
|
|||
static void sdrc_init(void)
|
||||
{
|
||||
/* Issue SDRC Soft reset */
|
||||
__raw_writel(0x12, SDRC_REG(SYSCONFIG));
|
||||
writel(0x12, SDRC_REG(SYSCONFIG));
|
||||
/* Wait until Reset complete */
|
||||
while ((__raw_readl(SDRC_REG(STATUS)) & 0x1) == 0);
|
||||
while ((readl(SDRC_REG(STATUS)) & 0x1) == 0);
|
||||
/* SDRC to normal mode */
|
||||
__raw_writel(0x10, SDRC_REG(SYSCONFIG));
|
||||
writel(0x10, SDRC_REG(SYSCONFIG));
|
||||
/* SDRC Sharing register */
|
||||
/* 32-bit SDRAM on data lane [31:0] - CS0 */
|
||||
/* pin tri-stated = 1 */
|
||||
__raw_writel(0x00000100, SDRC_REG(SHARING));
|
||||
writel(0x00000100, SDRC_REG(SHARING));
|
||||
|
||||
/* ----- SDRC_REG(CS0 Configuration --------- */
|
||||
/* SDRC_REG(MCFG0 register */
|
||||
__raw_writel(0x02584019, SDRC_REG(MCFG_0));
|
||||
writel(0x02584019, SDRC_REG(MCFG_0));
|
||||
|
||||
/* SDRC_REG(RFR_CTRL0 register */
|
||||
__raw_writel(0x0003DE01, SDRC_REG(RFR_CTRL_0));
|
||||
writel(0x0003DE01, SDRC_REG(RFR_CTRL_0));
|
||||
|
||||
/* SDRC_REG(ACTIM_CTRLA0 register */
|
||||
__raw_writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0));
|
||||
writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0));
|
||||
|
||||
/* SDRC_REG(ACTIM_CTRLB0 register */
|
||||
__raw_writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0));
|
||||
writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0));
|
||||
|
||||
/* Disble Power Down of CKE cuz of 1 CKE on combo part */
|
||||
__raw_writel(0x00000081, SDRC_REG(POWER));
|
||||
writel(0x00000081, SDRC_REG(POWER));
|
||||
|
||||
/* SDRC_REG(Manual command register */
|
||||
/* NOP command */
|
||||
__raw_writel(0x00000000, SDRC_REG(MANUAL_0));
|
||||
writel(0x00000000, SDRC_REG(MANUAL_0));
|
||||
/* Precharge command */
|
||||
__raw_writel(0x00000001, SDRC_REG(MANUAL_0));
|
||||
writel(0x00000001, SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
|
||||
writel(0x00000002, SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
__raw_writel(0x00000002, SDRC_REG(MANUAL_0));
|
||||
writel(0x00000002, SDRC_REG(MANUAL_0));
|
||||
|
||||
/* SDRC MR0 register */
|
||||
/* CAS latency = 3 */
|
||||
/* Write Burst = Read Burst */
|
||||
/* Serial Mode */
|
||||
__raw_writel(0x00000032, SDRC_REG(MR_0)); /* Burst length =4 */
|
||||
writel(0x00000032, SDRC_REG(MR_0)); /* Burst length =4 */
|
||||
|
||||
/* SDRC DLLA control register */
|
||||
/* Enable DLL A */
|
||||
__raw_writel(0x0000000A, SDRC_REG(DLLA_CTRL));
|
||||
writel(0x0000000A, SDRC_REG(DLLA_CTRL));
|
||||
|
||||
/* wait until DLL is locked */
|
||||
while ((__raw_readl(SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
|
||||
while ((readl(SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -138,9 +138,9 @@ static void pcm037_usb_init(void)
|
|||
u32 tmp;
|
||||
|
||||
/* enable clock */
|
||||
tmp = __raw_readl(0x53f80000);
|
||||
tmp = readl(0x53f80000);
|
||||
tmp |= (1 << 9);
|
||||
__raw_writel(tmp, 0x53f80000);
|
||||
writel(tmp, 0x53f80000);
|
||||
|
||||
/* Host 1 */
|
||||
tmp = readl(IMX_OTG_BASE + 0x600);
|
||||
|
|
|
|||
|
|
@ -50,9 +50,9 @@
|
|||
|
||||
/* Register access macros */
|
||||
#define ecc_readl(add, reg) \
|
||||
__raw_readl(add + ATMEL_ECC_##reg)
|
||||
readl(add + ATMEL_ECC_##reg)
|
||||
#define ecc_writel(add, reg, value) \
|
||||
__raw_writel((value), add + ATMEL_ECC_##reg)
|
||||
writel((value), add + ATMEL_ECC_##reg)
|
||||
|
||||
#include "atmel_nand_ecc.h" /* Hardware ECC registers */
|
||||
|
||||
|
|
@ -150,28 +150,28 @@ static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
|
|||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
|
||||
__raw_readsb(nand_chip->IO_ADDR_R, buf, len);
|
||||
readsb(nand_chip->IO_ADDR_R, buf, len);
|
||||
}
|
||||
|
||||
static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
|
||||
__raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
|
||||
readsw(nand_chip->IO_ADDR_R, buf, len / 2);
|
||||
}
|
||||
|
||||
static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
|
||||
__raw_writesb(nand_chip->IO_ADDR_W, buf, len);
|
||||
writesb(nand_chip->IO_ADDR_W, buf, len);
|
||||
}
|
||||
|
||||
static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
|
||||
__raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
|
||||
writesw(nand_chip->IO_ADDR_W, buf, len / 2);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@ static int omap_dev_ready(struct mtd_info *mtd)
|
|||
}
|
||||
/* if the wait is released, we are good to go */
|
||||
if (comp ==
|
||||
(__raw_readl(oinfo->gpmc_base + GPMC_STATUS) &&
|
||||
(readl(oinfo->gpmc_base + GPMC_STATUS) &&
|
||||
oinfo->wait_mon_mask))
|
||||
break;
|
||||
}
|
||||
|
|
@ -152,7 +152,7 @@ static int omap_dev_ready(struct mtd_info *mtd)
|
|||
*/
|
||||
static void gpmc_nand_wp(struct gpmc_nand_info *oinfo, int mode)
|
||||
{
|
||||
unsigned long config = __raw_readl(oinfo->gpmc_base + GPMC_CFG);
|
||||
unsigned long config = readl(oinfo->gpmc_base + GPMC_CFG);
|
||||
|
||||
gpmcnand_dbg("mode=%x", mode);
|
||||
if (mode)
|
||||
|
|
@ -160,7 +160,7 @@ static void gpmc_nand_wp(struct gpmc_nand_info *oinfo, int mode)
|
|||
else
|
||||
config |= (NAND_WP_BIT); /* WP is OFF */
|
||||
|
||||
__raw_writel(config, oinfo->gpmc_base + GPMC_CFG);
|
||||
writel(config, oinfo->gpmc_base + GPMC_CFG);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -199,7 +199,7 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
|||
}
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
__raw_writeb(cmd, nand->IO_ADDR_W);
|
||||
writeb(cmd, nand->IO_ADDR_W);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -303,14 +303,14 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
|
|||
|
||||
/* Since we smartly tell mtd driver to use eccsize of 512, only
|
||||
* ECC Reg1 will be used.. we just read that */
|
||||
val = __raw_readl(oinfo->gpmc_base + GPMC_ECC1_RESULT);
|
||||
val = readl(oinfo->gpmc_base + GPMC_ECC1_RESULT);
|
||||
ecc_code[0] = val & 0xFF;
|
||||
ecc_code[1] = (val >> 16) & 0xFF;
|
||||
ecc_code[2] = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
|
||||
|
||||
/* Stop reading anymore ECC vals and clear old results
|
||||
* enable will be called if more reads are required */
|
||||
__raw_writel(0x000, oinfo->gpmc_base + GPMC_ECC_CONFIG);
|
||||
writel(0x000, oinfo->gpmc_base + GPMC_ECC_CONFIG);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -330,14 +330,14 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
|
|||
/* Clear the ecc result registers
|
||||
* select ecc reg as 1
|
||||
*/
|
||||
__raw_writel(0x101, oinfo->gpmc_base + GPMC_ECC_CONTROL);
|
||||
writel(0x101, oinfo->gpmc_base + GPMC_ECC_CONTROL);
|
||||
/* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
|
||||
* tell all regs to generate size0 sized regs
|
||||
* we just have a single ECC engine for all CS
|
||||
*/
|
||||
__raw_writel(0x3FCFF000, oinfo->gpmc_base +
|
||||
writel(0x3FCFF000, oinfo->gpmc_base +
|
||||
GPMC_ECC_SIZE_CONFIG);
|
||||
__raw_writel(oinfo->ecc_config, oinfo->gpmc_base +
|
||||
writel(oinfo->ecc_config, oinfo->gpmc_base +
|
||||
GPMC_ECC_CONFIG);
|
||||
break;
|
||||
default:
|
||||
|
|
@ -411,7 +411,7 @@ static int gpmc_nand_probe(struct device_d *pdev)
|
|||
oinfo->gpmc_address, oinfo->gpmc_data, cs_base);
|
||||
|
||||
/* If we are 16 bit dev, our gpmc config tells us that */
|
||||
if ((__raw_readl(cs_base) & 0x3000) == 0x1000) {
|
||||
if ((readl(cs_base) & 0x3000) == 0x1000) {
|
||||
debug("16 bit dev\n");
|
||||
nand->options |= NAND_BUSWIDTH_16;
|
||||
}
|
||||
|
|
@ -492,7 +492,7 @@ static int gpmc_nand_probe(struct device_d *pdev)
|
|||
* Send a reset to the device
|
||||
* 8 bit write will work on 16 and 8 bit devices
|
||||
*/
|
||||
__raw_writeb(NAND_CMD_RESET, oinfo->gpmc_command);
|
||||
writeb(NAND_CMD_RESET, oinfo->gpmc_command);
|
||||
mdelay(1);
|
||||
|
||||
/* In normal mode, we scan to get just the device
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@
|
|||
|
||||
/** Provide the Regoffset, Value */
|
||||
#define MUX_VAL(OFFSET,VALUE)\
|
||||
__raw_writew((VALUE), OMAP_CTRL_BASE + (OFFSET))
|
||||
writew((VALUE), OMAP_CTRL_BASE + (OFFSET))
|
||||
|
||||
/**
|
||||
* macro for Padconfig Registers @see
|
||||
|
|
|
|||
Loading…
Reference in New Issue