OWHW: Add device tree for hardware v2
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2015 Harald Welte <laforge@gnumonks.org>
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* Copyright (C) 2015-2016 Harald Welte <laforge@gnumonks.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -12,7 +12,7 @@
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#include "am335x-phytec-phycore-som.dtsi"
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/ {
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model = "GSMK OWHW";
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model = "GSMK OWHW v2";
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compatible = "gsmk,owhw", "phytec,phycore-am335x-som", "phytec,am335x-som", "ti,am33xx";
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buttons: user_buttons {
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@ -123,6 +123,71 @@
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default_attempts = <3>;
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};
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};
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i2c_gpio {
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compatible = "i2c-gpio";
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gpios = <&gpio1 31 GPIO_ACTIVE_HIGH /* sda */
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&gpio1 16 GPIO_ACTIVE_HIGH /* scl */
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>;
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i2c-gpio,sda-open-drain;
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i2c-gpio,scl-open-drain;
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i2c-gpio,delay-us = <20>; /* ~10 kHz */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_gpio_pins>;
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status = "okay";
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ltc4274@20 {
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compatible = "ltc4275";
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reg = <0x20>;
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};
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};
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switch_mdio {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&switch_mdio_pins>;
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/* order: MDC, MDIO */
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gpios = <&gpio1 19
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&gpio1 21>;
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status = "okay";
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};
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spi_gpio {
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compatible = "spi-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_gpio_pins>;
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status = "okay";
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gpio-sck = <&gpio3 14 0>;
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gpio-mosi = <&gpio3 16 0>;
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gpio-miso = <&gpio3 15 0>;
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cs-gpios = <&gpio3 21 0>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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eeprom_baseboard: m95m02@0 {
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compatible = "st,m95m02", "atmel,at25";
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size = <262144>;
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pagesize = <256>;
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address-width = <24>;
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spi-max-frequency = <5000000>;
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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partition@0 {
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label = "state";
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reg = <0xc0 0x40>; /* last 0x40 bytes for eeprom */
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};
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};
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};
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};
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&nand {
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@ -140,8 +205,6 @@
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&i2c0_pins {
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pinctrl-single,pins = <
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/* EEPROM_WP */
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0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.gpio1_19 */
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0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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@ -211,8 +274,6 @@
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pse_pins: pinmux_pse_pins {
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pinctrl-single,pins = <
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/* PSE_I2C_BUF_EN: 1_16 */
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0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* (R13) gpmc_a0.gpio1[16] */
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/* !PSE_INT: 1_20 */
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0x50 (PIN_INPUT | MUX_MODE7) /* (R14) gpmc_a4.gpio1[20] */
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>;
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@ -238,22 +299,34 @@
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0x64 (PIN_INPUT_PULLUP | MUX_MODE7) /* (U16) gpmc_a9.gpio1[25] */
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>;
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};
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};
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&i2c0 {
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eeprom_baseboard: 24cm02@50 {
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status = "okay";
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compatible = "atmel,24cm02";
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pagesize = <256>;
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reg = <0x50>;
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wp-gpios = <&gpio1 19 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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i2c_gpio_pins: pinmux_i2c_gpio {
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pinctrl-single,pins = <
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/* I2C_S_SCL: 1_16 */
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0x40 (PIN_OUTPUT_PULLUP | PIN_INPUT_PULLUP | MUX_MODE7) /* (R13) gpmc_a0.gpio1[16] */
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/* I2C_S_SDA: 1_31 */
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0x84 (PIN_OUTPUT_PULLUP | PIN_INPUT_PULLUP | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */
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>;
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};
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partition@0 {
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label = "state";
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reg = <0xc0 0x40>; /* last 0x40 bytes for eeprom */
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};
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spi1_gpio_pins: pinmux_spi1_gpio {
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pinctrl-single,pins = <
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/* EEPROM_WP */
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0x1a8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* (D13) mcasp0_axr1.gpio3_20 */
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0x190 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (A13) mcasp0_aclkx.spi1_sclk */
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0x194 (PIN_INPUT_PULLUP | MUX_MODE7) /* (B13) mcasp0_fsx.spi1_d0 */
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0x198 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (D12) mcasp0_axr0.spi1_d1 */
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0x1AC (PIN_OUTPUT_PULLUP | MUX_MODE7) /* (A14) mcasp0_ahclkx.gpio3_21 */
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>;
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};
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switch_mdio_pins: pinmux_mdio_gpio {
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pinctrl-single,pins = <
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/* ETH_MDC: 1_19 */
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0x4c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* (T14) gpmc_a3.gpio1[19] */
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/* ETH_MDIO: 1_21 */
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0x54 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] */
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>;
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};
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};
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@ -265,3 +338,7 @@
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&usb0_phy {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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