MX28: add FEC support
The i.MX28 comes with an extended ethernet controller (ENET/FEC) which is backwards compatible to the FEC known from other i.MX CPUs. Add a few adaptions to the existing driver to make it work with the MX28 FEC. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Juergen Beisert
Sascha Hauer
parent
07965c6fa1
commit
cf463d7430
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@ -21,6 +21,7 @@ config ARCH_IMX23
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config ARCH_IMX28
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bool "i.MX28"
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select CPU_ARM926T
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select ARCH_HAS_FEC_IMX
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endchoice
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@ -29,10 +29,13 @@
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <mach/generic.h>
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#include <mach/imx-regs.h>
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#include <clock.h>
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#include <mach/clock.h>
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#include <mach/iim.h>
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#ifndef CONFIG_ARCH_STM
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# include <mach/iim.h>
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#endif
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#include <xfuncs.h>
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#include "fec_imx.h"
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@ -150,6 +153,39 @@ static int fec_tx_task_disable(struct fec_priv *fec)
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return 0;
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}
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/**
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* Swap endianess to send data on an i.MX28 based platform
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* @param buf Pointer to little endian data
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* @param len Size in words (max. 1500 bytes)
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* @return Pointer to the big endian data
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*/
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static void *imx28_fix_endianess_wr(uint32_t *buf, unsigned wlen)
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{
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unsigned u;
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static uint32_t data[376]; /* = 1500 bytes + 4 bytes */
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for (u = 0; u < wlen; u++, buf++)
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data[u] = __swab32(*buf);
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return data;
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}
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/**
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* Swap endianess to read data on an i.MX28 based platform
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* @param buf Pointer to little endian data
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* @param len Size in words (max. 1500 bytes)
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*
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* TODO: Check for the risk of destroying some other data behind the buffer
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* if its size is not a multiple of 4.
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*/
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static void imx28_fix_endianess_rd(uint32_t *buf, unsigned wlen)
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{
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unsigned u;
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for (u = 0; u < wlen; u++, buf++)
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*buf = __swab32(*buf);
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}
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/**
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* Initialize receive task's buffer descriptors
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* @param[in] fec all we know about the device yet
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@ -233,7 +269,11 @@ static void fec_rbd_clean(int last, struct buffer_descriptor __iomem *pRbd)
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static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
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{
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#ifdef CONFIG_ARCH_STM
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return -1;
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#else
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return imx_iim_get_mac(mac);
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#endif
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}
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static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
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@ -270,12 +310,13 @@ static int fec_init(struct eth_device *dev)
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/*
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* Frame length=1518; 7-wire mode
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*/
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writel((1518 << 16), fec->regs + FEC_R_CNTRL);
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writel(FEC_R_CNTRL_MAX_FL(1518), fec->regs + FEC_R_CNTRL);
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} else {
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/*
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* Frame length=1518; MII mode;
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*/
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writel((1518 << 16) | (1 << 2), fec->regs + FEC_R_CNTRL);
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writel(FEC_R_CNTRL_MAX_FL(1518) | FEC_R_CNTRL_MII_MODE,
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fec->regs + FEC_R_CNTRL);
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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@ -285,16 +326,26 @@ static int fec_init(struct eth_device *dev)
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}
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if (fec->xcv_type == RMII) {
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/* disable the gasket and wait */
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writel(0, fec->regs + FEC_MIIGSK_ENR);
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while (readl(fec->regs + FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
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udelay(1);
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if (cpu_is_mx28()) {
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/* just another way to enable RMII */
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uint32_t reg = readl(fec->regs + FEC_R_CNTRL);
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writel(reg | FEC_R_CNTRL_RMII_MODE
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/* the linux driver add these bits, why not we? */
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/* | FEC_R_CNTRL_FCE | */
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/* FEC_R_CNTRL_NO_LGTH_CHECK */,
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fec->regs + FEC_R_CNTRL);
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} else {
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/* disable the gasket and wait */
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writel(0, fec->regs + FEC_MIIGSK_ENR);
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while (readl(fec->regs + FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
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udelay(1);
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/* configure the gasket for RMII, 50 MHz, no loopback, no echo */
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writel(FEC_MIIGSK_CFGR_IF_MODE_RMII, fec->regs + FEC_MIIGSK_CFGR);
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/* configure the gasket for RMII, 50 MHz, no loopback, no echo */
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writel(FEC_MIIGSK_CFGR_IF_MODE_RMII, fec->regs + FEC_MIIGSK_CFGR);
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/* re-enable the gasket */
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writel(FEC_MIIGSK_ENR_EN, fec->regs + FEC_MIIGSK_ENR);
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/* re-enable the gasket */
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writel(FEC_MIIGSK_ENR_EN, fec->regs + FEC_MIIGSK_ENR);
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}
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}
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/*
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@ -419,6 +470,9 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
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* Note: We are always using the first buffer for transmission,
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* the second will be empty and only used to stop the DMA engine
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*/
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if (cpu_is_mx28())
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eth_data = imx28_fix_endianess_wr(eth_data, (data_length + 3) >> 2);
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writew(data_length, &fec->tbd_base[fec->tbd_index].data_length);
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writel((uint32_t)(eth_data), &fec->tbd_base[fec->tbd_index].data_pointer);
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@ -483,10 +537,12 @@ static int fec_recv(struct eth_device *dev)
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printf("some error: 0x%08x\n", ievent);
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return 0;
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}
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if (ievent & FEC_IEVENT_HBERR) {
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/* Heartbeat error */
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writel(readl(fec->regs + FEC_X_CNTRL) | 0x1,
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fec->regs + FEC_X_CNTRL);
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if (!cpu_is_mx28()) {
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if (ievent & FEC_IEVENT_HBERR) {
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/* Heartbeat error */
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writel(readl(fec->regs + FEC_X_CNTRL) | 0x1,
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fec->regs + FEC_X_CNTRL);
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}
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}
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if (ievent & FEC_IEVENT_GRA) {
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/* Graceful stop complete */
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@ -506,6 +562,12 @@ static int fec_recv(struct eth_device *dev)
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if (!(bd_status & FEC_RBD_EMPTY)) {
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if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
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((readw(&rbd->data_length) - 4) > 14)) {
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if (cpu_is_mx28())
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imx28_fix_endianess_rd(
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(void *)readl(&rbd->data_pointer),
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(readw(&rbd->data_length) + 3) >> 2);
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/*
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* Get buffer address and size
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*/
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@ -63,8 +63,19 @@
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#define FEC_MIIGSK_ENR_READY (1 << 2)
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#define FEC_MIIGSK_ENR_EN (1 << 1)
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#define FEC_R_CNTRL_GRS (1 << 31)
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#define FEC_R_CNTRL_NO_LGTH_CHECK (1 << 30)
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#ifdef CONFIG_ARCH_IMX28
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# define FEC_R_CNTRL_MAX_FL(x) (((x) & 0x3fff) << 16)
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#else
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# define FEC_R_CNTRL_MAX_FL(x) (((x) & 0x7ff) << 16)
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#endif
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#define FEC_R_CNTRL_RMII_10T (1 << 9) /* i.MX28 specific */
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#define FEC_R_CNTRL_RMII_MODE (1 << 8) /* i.MX28 specific */
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#define FEC_R_CNTRL_FCE (1 << 5)
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#define FEC_R_CNTRL_MII_MODE (1 << 2)
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#define FEC_IEVENT_HBERR 0x80000000
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#define FEC_IEVENT_HBERR 0x80000000 /* Note: Not on i.MX28 */
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#define FEC_IEVENT_BABR 0x40000000
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#define FEC_IEVENT_BABT 0x20000000
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#define FEC_IEVENT_GRA 0x10000000
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@ -74,7 +85,7 @@
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#define FEC_IEVENT_COL_RETRY_LIM 0x00100000
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#define FEC_IEVENT_XFIFO_UN 0x00080000
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#define FEC_IMASK_HBERR 0x80000000
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#define FEC_IMASK_HBERR 0x80000000 /* Note: Not on i.MX28 */
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#define FEC_IMASK_BABR 0x40000000
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#define FEC_IMASK_BABT 0x20000000
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#define FEC_IMASK_GRA 0x10000000
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@ -120,6 +131,8 @@
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* @brief Receive & Transmit Buffer Descriptor definitions
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*
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* Note: The first BD must be aligned (see DB_ALIGNMENT)
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*
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* BTW: Don't trust the i.MX27 and i.MX28 data sheet
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*/
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struct buffer_descriptor {
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uint16_t data_length; /**< payload's length in bytes */
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