From 582432593625e4248b72363c34d8dc64b75f0a59 Mon Sep 17 00:00:00 2001
From: Jan Luebbe <jlu@pengutronix.de>
Date: Thu, 13 Dec 2012 17:30:49 +0100
Subject: [PATCH 01/16] drivers: net: add driver for TI CPSW

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/include/mach/cpsw.h |   29 +
 drivers/net/Kconfig                    |    4 +
 drivers/net/Makefile                   |    1 +
 drivers/net/cpsw.c                     | 1070 ++++++++++++++++++++++++
 4 files changed, 1104 insertions(+)
 create mode 100644 arch/arm/mach-omap/include/mach/cpsw.h
 create mode 100644 drivers/net/cpsw.c

diff --git a/arch/arm/mach-omap/include/mach/cpsw.h b/arch/arm/mach-omap/include/mach/cpsw.h
new file mode 100644
index 000000000..5474667a0
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/cpsw.h
@@ -0,0 +1,29 @@
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPSW_H_
+#define _CPSW_H_
+
+struct cpsw_slave_data {
+	int		phy_id;
+	int		phy_if;
+};
+
+struct cpsw_platform_data {
+	struct cpsw_slave_data	*slave_data;
+	int			num_slaves;
+};
+
+#endif /* _CPSW_H_  */
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 43d5984e0..cf6ceee06 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -31,6 +31,10 @@ config DRIVER_NET_CS8900
 	bool "cs8900 ethernet driver"
 	depends on HAS_CS8900
 
+config DRIVER_NET_CPSW
+	bool "CPSW ethernet driver"
+	select PHYLIB
+
 config DRIVER_NET_SMC911X
 	bool "smc911x ethernet driver"
 	select PHYLIB
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4e6b49b19..6e1aeaaad 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_DRIVER_NET_CS8900)		+= cs8900.o
+obj-$(CONFIG_DRIVER_NET_CPSW)		+= cpsw.o
 obj-$(CONFIG_DRIVER_NET_SMC911X)	+= smc911x.o
 obj-$(CONFIG_DRIVER_NET_SMC91111)	+= smc91111.o
 obj-$(CONFIG_DRIVER_NET_DAVINCI_EMAC)	+= davinci_emac.o
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
new file mode 100644
index 000000000..58c097afe
--- /dev/null
+++ b/drivers/net/cpsw.c
@@ -0,0 +1,1070 @@
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+#include <net.h>
+#include <linux/phy.h>
+#include <errno.h>
+#include <io.h>
+#include <xfuncs.h>
+#include <asm/mmu.h>
+#include <asm/system.h>
+
+#include <mach/cpsw.h>
+
+#define CPSW_VERSION_1		0x19010a
+#define CPSW_VERSION_2		0x19010c
+
+#define BITMASK(bits)		((1 << (bits)) - 1)
+#define PHY_REG_MASK		0x1f
+#define PHY_ID_MASK		0x1f
+#define NUM_DESCS		(PKTBUFSRX * 2)
+#define PKT_MIN			60
+#define PKT_MAX			(1500 + 14 + 4 + 4)
+
+/* DMA Registers */
+#define CPDMA_TXCONTROL		0x004
+#define CPDMA_RXCONTROL		0x014
+#define CPDMA_SOFTRESET		0x01c
+#define CPDMA_RXFREE		0x0e0
+#define STATERAM_TXHDP		0x000
+#define STATERAM_RXHDP		0x020
+#define STATERAM_TXCP		0x040
+#define STATERAM_RXCP		0x060
+
+#define CPDMA_RAM_ADDR          0x4a102000
+
+/* Descriptor mode bits */
+#define CPDMA_DESC_SOP		BIT(31)
+#define CPDMA_DESC_EOP		BIT(30)
+#define CPDMA_DESC_OWNER	BIT(29)
+#define CPDMA_DESC_EOQ		BIT(28)
+
+#define SLIVER_SIZE		0x40
+
+struct cpsw_mdio_regs {
+	u32	version;
+	u32	control;
+#define CONTROL_IDLE		(1 << 31)
+#define CONTROL_ENABLE		(1 << 30)
+
+	u32	alive;
+	u32	link;
+	u32	linkintraw;
+	u32	linkintmasked;
+	u32	__reserved_0[2];
+	u32	userintraw;
+	u32	userintmasked;
+	u32	userintmaskset;
+	u32	userintmaskclr;
+	u32	__reserved_1[20];
+
+	struct {
+		u32 access;
+		u32 physel;
+#define USERACCESS_GO		(1 << 31)
+#define USERACCESS_WRITE	(1 << 30)
+#define USERACCESS_ACK		(1 << 29)
+#define USERACCESS_READ		(0)
+#define USERACCESS_DATA		(0xffff)
+	} user[0];
+};
+
+struct cpsw_regs {
+	u32	id_ver;
+	u32	control;
+	u32	soft_reset;
+	u32	stat_port_en;
+	u32	ptype;
+};
+
+struct cpsw_slave_regs {
+	u32	max_blks;
+	u32	blk_cnt;
+	u32	flow_thresh;
+	u32	port_vlan;
+	u32	tx_pri_map;
+	u32	sa_lo;
+	u32	sa_hi;
+};
+
+struct cpsw_host_regs {
+	u32	max_blks;
+	u32	blk_cnt;
+	u32	flow_thresh;
+	u32	port_vlan;
+	u32	tx_pri_map;
+	u32	cpdma_tx_pri_map;
+	u32	cpdma_rx_chan_map;
+};
+
+struct cpsw_sliver_regs {
+	u32	id_ver;
+	u32	mac_control;
+	u32	mac_status;
+	u32	soft_reset;
+	u32	rx_maxlen;
+	u32	__reserved_0;
+	u32	rx_pause;
+	u32	tx_pause;
+	u32	__reserved_1;
+	u32	rx_pri_map;
+};
+
+#define ALE_ENTRY_BITS		68
+#define ALE_ENTRY_WORDS		DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
+
+/* ALE Registers */
+#define ALE_CONTROL		0x08
+#define ALE_UNKNOWNVLAN		0x18
+#define ALE_TABLE_CONTROL	0x20
+#define ALE_TABLE		0x34
+#define ALE_PORTCTL		0x40
+
+#define ALE_TABLE_WRITE		BIT(31)
+
+#define ALE_TYPE_FREE			0
+#define ALE_TYPE_ADDR			1
+#define ALE_TYPE_VLAN			2
+#define ALE_TYPE_VLAN_ADDR		3
+
+#define ALE_UCAST_PERSISTANT		0
+#define ALE_UCAST_UNTOUCHED		1
+#define ALE_UCAST_OUI			2
+#define ALE_UCAST_TOUCHED		3
+
+#define ALE_MCAST_FWD			0
+#define ALE_MCAST_BLOCK_LEARN_FWD	1
+#define ALE_MCAST_FWD_LEARN		2
+#define ALE_MCAST_FWD_2			3
+
+enum cpsw_ale_port_state {
+	ALE_PORT_STATE_DISABLE	= 0x00,
+	ALE_PORT_STATE_BLOCK	= 0x01,
+	ALE_PORT_STATE_LEARN	= 0x02,
+	ALE_PORT_STATE_FORWARD	= 0x03,
+};
+
+/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
+#define ALE_SECURE	1
+#define ALE_BLOCKED	2
+
+struct cpsw_slave {
+	struct cpsw_slave_regs		*regs;
+	struct cpsw_sliver_regs		*sliver;
+	int				slave_num;
+	u32				mac_control;
+	struct cpsw_slave_data		*data;
+};
+
+struct cpdma_desc {
+	/* hardware fields */
+	u32			hw_next;
+	u32			hw_buffer;
+	u32			hw_len;
+	u32			hw_mode;
+	/* software fields */
+	u32			sw_buffer;
+	u32			sw_len;
+};
+
+struct cpdma_chan {
+	struct cpdma_desc	*head, *tail;
+	void			*hdp, *cp, *rxfree;
+};
+
+struct cpsw_priv {
+	struct device_d			*dev;
+	struct eth_device		edev;
+	struct mii_bus			miibus;
+
+	u32				version;
+	struct cpsw_platform_data	data;
+	int				host_port;
+	uint8_t				mac_addr[6];
+
+	struct cpsw_regs		*regs;
+	struct cpsw_mdio_regs		*mdio_regs;
+	void				*dma_regs;
+	struct cpsw_host_regs		*host_port_regs;
+	void				*ale_regs;
+	void				*state_ram;
+
+	unsigned int			ale_entries;
+	unsigned int			num_slaves;
+	unsigned int			channels;
+	unsigned int			slave_ofs;
+	unsigned int			slave_size;
+	unsigned int			sliver_ofs;
+
+	struct cpdma_desc		*descs;
+	struct cpdma_desc		*desc_free;
+	struct cpdma_chan		rx_chan, tx_chan;
+
+	struct cpsw_slave		*slaves;
+#define for_each_slave(priv, func, arg...)			\
+	do {							\
+		int idx;					\
+		for (idx = 0; idx < (priv)->num_slaves; idx++)	\
+			(func)((priv)->slaves + idx, ##arg);	\
+	} while (0)
+};
+
+static int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
+{
+	int idx;
+
+	idx    = start / 32;
+	start -= idx * 32;
+	idx    = 2 - idx; /* flip */
+
+	return (ale_entry[idx] >> start) & BITMASK(bits);
+}
+
+static void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
+				      u32 value)
+{
+	int idx;
+
+	value &= BITMASK(bits);
+	idx    = start / 32;
+	start -= idx * 32;
+	idx    = 2 - idx; /* flip */
+	ale_entry[idx] &= ~(BITMASK(bits) << start);
+	ale_entry[idx] |=  (value << start);
+}
+
+#define DEFINE_ALE_FIELD(name, start, bits)				\
+static inline int cpsw_ale_get_##name(u32 *ale_entry)			\
+{									\
+	return cpsw_ale_get_field(ale_entry, start, bits);		\
+}									\
+static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)	\
+{									\
+	cpsw_ale_set_field(ale_entry, start, bits, value);		\
+}
+
+DEFINE_ALE_FIELD(entry_type,		60,	2)
+DEFINE_ALE_FIELD(mcast_state,		62,	2)
+DEFINE_ALE_FIELD(port_mask,		66,	3)
+DEFINE_ALE_FIELD(ucast_type,		62,	2)
+DEFINE_ALE_FIELD(port_num,		66,	2)
+DEFINE_ALE_FIELD(blocked,		65,	1)
+DEFINE_ALE_FIELD(secure,		64,	1)
+DEFINE_ALE_FIELD(mcast,			40,	1)
+
+static char ethbdaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+
+/* The MAC address field in the ALE entry cannot be macroized as above */
+static void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
+{
+	int i;
+
+	for (i = 0; i < 6; i++)
+		addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
+}
+
+static void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
+{
+	int i;
+
+	for (i = 0; i < 6; i++)
+		cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
+}
+
+static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
+{
+	int i;
+
+	writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
+
+	for (i = 0; i < ALE_ENTRY_WORDS; i++)
+		ale_entry[i] = readl(priv->ale_regs + ALE_TABLE + 4 * i);
+
+	return idx;
+}
+
+static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
+{
+	int i;
+
+	for (i = 0; i < ALE_ENTRY_WORDS; i++)
+		writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
+
+	writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
+
+	return idx;
+}
+
+static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
+{
+	u32 ale_entry[ALE_ENTRY_WORDS];
+	int type, idx;
+
+	for (idx = 0; idx < priv->ale_entries; idx++) {
+		u8 entry_addr[6];
+
+		cpsw_ale_read(priv, idx, ale_entry);
+		type = cpsw_ale_get_entry_type(ale_entry);
+
+		if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+			continue;
+
+		cpsw_ale_get_addr(ale_entry, entry_addr);
+
+		if (memcmp(entry_addr, addr, 6) == 0)
+			return idx;
+	}
+
+	return -ENOENT;
+}
+
+static int cpsw_ale_match_free(struct cpsw_priv *priv)
+{
+	u32 ale_entry[ALE_ENTRY_WORDS];
+	int type, idx;
+
+	for (idx = 0; idx < priv->ale_entries; idx++) {
+		cpsw_ale_read(priv, idx, ale_entry);
+		type = cpsw_ale_get_entry_type(ale_entry);
+
+		if (type == ALE_TYPE_FREE)
+			return idx;
+	}
+
+	return -ENOENT;
+}
+
+static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
+{
+	u32 ale_entry[ALE_ENTRY_WORDS];
+	int type, idx;
+
+	for (idx = 0; idx < priv->ale_entries; idx++) {
+		cpsw_ale_read(priv, idx, ale_entry);
+		type = cpsw_ale_get_entry_type(ale_entry);
+
+		if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+			continue;
+
+		if (cpsw_ale_get_mcast(ale_entry))
+			continue;
+
+		type = cpsw_ale_get_ucast_type(ale_entry);
+
+		if (type != ALE_UCAST_PERSISTANT &&
+		    type != ALE_UCAST_OUI)
+			return idx;
+	}
+
+	return -ENOENT;
+}
+
+static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
+			      int port, int flags)
+{
+	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+	int idx;
+
+	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+	cpsw_ale_set_addr(ale_entry, addr);
+	cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
+	cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
+	cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
+	cpsw_ale_set_port_num(ale_entry, port);
+
+	idx = cpsw_ale_match_addr(priv, addr);
+	if (idx < 0)
+		idx = cpsw_ale_match_free(priv);
+	if (idx < 0)
+		idx = cpsw_ale_find_ageable(priv);
+	if (idx < 0)
+		return -ENOMEM;
+
+	cpsw_ale_write(priv, idx, ale_entry);
+	return 0;
+}
+
+static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
+{
+	u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+	int idx, mask;
+
+	idx = cpsw_ale_match_addr(priv, addr);
+	if (idx >= 0)
+		cpsw_ale_read(priv, idx, ale_entry);
+
+	cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+	cpsw_ale_set_addr(ale_entry, addr);
+	cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
+
+	mask = cpsw_ale_get_port_mask(ale_entry);
+	port_mask |= mask;
+	cpsw_ale_set_port_mask(ale_entry, port_mask);
+
+	if (idx < 0)
+		idx = cpsw_ale_match_free(priv);
+	if (idx < 0)
+		idx = cpsw_ale_find_ageable(priv);
+	if (idx < 0)
+		return -ENOMEM;
+
+	cpsw_ale_write(priv, idx, ale_entry);
+	return 0;
+}
+
+static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
+{
+	u32 tmp, mask = BIT(bit);
+
+	tmp  = readl(priv->ale_regs + ALE_CONTROL);
+	tmp &= ~mask;
+	tmp |= val ? mask : 0;
+	writel(tmp, priv->ale_regs + ALE_CONTROL);
+}
+
+#define cpsw_ale_enable(priv, val)	cpsw_ale_control(priv, 31, val)
+#define cpsw_ale_clear(priv, val)	cpsw_ale_control(priv, 30, val)
+#define cpsw_ale_bypass(priv, val)	cpsw_ale_control(priv,  4, val)
+#define cpsw_ale_vlan_aware(priv, val)	cpsw_ale_control(priv,  2, val)
+
+static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
+				       int val)
+{
+	int offset = ALE_PORTCTL + 4 * port;
+	u32 tmp, mask = 0x3;
+
+	tmp  = readl(priv->ale_regs + offset);
+	tmp &= ~mask;
+	tmp |= val & 0x3;
+	writel(tmp, priv->ale_regs + offset);
+}
+
+/* wait until hardware is ready for another user access */
+static u32 wait_for_user_access(struct cpsw_priv *priv)
+{
+	struct cpsw_mdio_regs *mdio_regs = priv->mdio_regs;
+	u32 tmp;
+	uint64_t start = get_time_ns();
+
+	do {
+		tmp = readl(&mdio_regs->user[0].access);
+
+		if (!(tmp & USERACCESS_GO))
+			break;
+
+		if (is_timeout(start, 100 * MSECOND)) {
+			dev_err(priv->dev, "timeout waiting for user access\n");
+			break;
+		}
+	} while (1);
+
+	return tmp;
+}
+
+static int cpsw_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
+{
+	struct cpsw_priv *priv = bus->priv;
+	struct cpsw_mdio_regs *mdio_regs = priv->mdio_regs;
+
+	u32 tmp;
+
+	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+		return -EINVAL;
+
+	wait_for_user_access(priv);
+
+	tmp = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
+	       (phy_id << 16));
+	writel(tmp, &mdio_regs->user[0].access);
+
+	tmp = wait_for_user_access(priv);
+
+	return (tmp & USERACCESS_ACK) ? (tmp & USERACCESS_DATA) : -1;
+}
+
+static int cpsw_mdio_write(struct mii_bus *bus, int phy_id, int phy_reg, u16 value)
+{
+	struct cpsw_priv *priv = bus->priv;
+	struct cpsw_mdio_regs *mdio_regs = priv->mdio_regs;
+	u32 tmp;
+
+	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+		return -EINVAL;
+
+	wait_for_user_access(priv);
+	tmp = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
+		   (phy_id << 16) | (value & USERACCESS_DATA));
+	writel(tmp, &mdio_regs->user[0].access);
+	wait_for_user_access(priv);
+
+	return 0;
+}
+
+static inline void soft_reset(struct cpsw_priv *priv, void *reg)
+{
+	int ret;
+
+	writel(1, reg);
+
+	ret = wait_on_timeout(100 * MSECOND, (readl(reg) & 1) == 0);
+	if (ret)
+		dev_err(priv->dev, "reset timeout\n");
+}
+
+#define mac_hi(mac)	(((mac)[0] << 0) | ((mac)[1] << 8) |	\
+			 ((mac)[2] << 16) | ((mac)[3] << 24))
+#define mac_lo(mac)	(((mac)[4] << 0) | ((mac)[5] << 8))
+
+static void cpsw_set_slave_mac(struct cpsw_slave *slave,
+			       struct cpsw_priv *priv,
+			       unsigned char *mac)
+{
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	writel(mac_hi(mac), &slave->regs->sa_hi);
+	writel(mac_lo(mac), &slave->regs->sa_lo);
+}
+
+static int cpsw_get_hwaddr(struct eth_device *edev, unsigned char *mac)
+{
+	struct cpsw_priv *priv = edev->priv;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	return -1;
+}
+
+static int cpsw_set_hwaddr(struct eth_device *edev, unsigned char *mac)
+{
+	struct cpsw_priv *priv = edev->priv;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	memcpy(&priv->mac_addr, mac, sizeof(priv->mac_addr));
+
+	for_each_slave(priv, cpsw_set_slave_mac, priv, mac);
+
+	return 0;
+}
+
+static void cpsw_slave_update_link(struct cpsw_slave *slave,
+				   struct cpsw_priv *priv, int *link)
+{
+	struct phy_device *phydev = priv->edev.phydev;
+	u32 mac_control = 0;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	if (!phydev)
+		return;
+
+	if (slave->slave_num)
+		return;
+
+	if (phydev->link) {
+		*link = 1;
+		mac_control = BIT(5); /* MIIEN */
+		if (phydev->speed == SPEED_10)
+			mac_control |= BIT(18);	/* In Band mode	*/
+		else if (phydev->speed == SPEED_100)
+			mac_control |= BIT(15);
+		else if (phydev->speed == SPEED_1000)
+			mac_control &= ~BIT(7);	/* TODO: Do not enable
+						 * gig support now */
+		if (phydev->duplex == DUPLEX_FULL)
+			mac_control |= BIT(0);	/* FULLDUPLEXEN	*/
+	}
+
+	if (mac_control == slave->mac_control)
+		return;
+
+	if (mac_control) {
+		dev_dbg(priv->dev, "link up on port %d, speed %d, %s duplex\n",
+				slave->slave_num, phydev->speed,
+				(phydev->duplex == DUPLEX_FULL) ?  "full" : "half");
+	} else {
+		dev_dbg(priv->dev, "link down on port %d\n", slave->slave_num);
+	}
+
+	writel(mac_control, &slave->sliver->mac_control);
+	slave->mac_control = mac_control;
+}
+
+static int cpsw_update_link(struct cpsw_priv *priv)
+{
+	int link = 0;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	for_each_slave(priv, cpsw_slave_update_link, priv, &link);
+	return link;
+}
+
+static void cpsw_adjust_link(struct eth_device *edev) {
+	struct cpsw_priv *priv = edev->priv;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	cpsw_update_link(priv);
+}
+
+static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
+{
+	if (priv->host_port == 0)
+		return slave_num + 1;
+	else
+		return slave_num;
+}
+
+static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
+{
+	u32	slave_port;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	soft_reset(priv, &slave->sliver->soft_reset);
+
+	/* setup priority mapping */
+	writel(0x76543210, &slave->sliver->rx_pri_map);
+	writel(0x33221100, &slave->regs->tx_pri_map);
+
+	/* setup max packet size, and mac address */
+	writel(PKT_MAX, &slave->sliver->rx_maxlen);
+
+	slave->mac_control = 0;	/* no link yet */
+
+	/* enable forwarding */
+	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
+	cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
+
+	/* add broadcast address */
+	cpsw_ale_add_mcast(priv, ethbdaddr, 1 << slave_port);
+}
+
+static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
+{
+	struct cpdma_desc *desc = priv->desc_free;
+
+	if (desc)
+		priv->desc_free = (void *)readl(&desc->hw_next);
+
+	return desc;
+}
+
+static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
+{
+	dev_dbg(priv->dev, "%s: free desc=0x%p\n", __func__, desc);
+
+	if (desc) {
+		writel((u32)priv->desc_free, &desc->hw_next);
+		priv->desc_free = desc;
+	}
+}
+
+static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
+			void *buffer, int len)
+{
+	struct cpdma_desc *desc, *prev;
+	u32 mode;
+
+	desc = cpdma_desc_alloc(priv);
+	if (!desc)
+		return -ENOMEM;
+
+	if (len < PKT_MIN)
+		len = PKT_MIN;
+
+	mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
+
+	writel(0, &desc->hw_next);
+	writel((u32)buffer, &desc->hw_buffer);
+	writel(len, &desc->hw_len);
+	writel(mode | len, &desc->hw_mode);
+	writel((u32)buffer, &desc->sw_buffer);
+	writel((u32)len, &desc->sw_len);
+
+	if (!chan->head) {
+		/* simple case - first packet enqueued */
+		chan->head = desc;
+		chan->tail = desc;
+		writel((u32)desc, chan->hdp);
+		goto done;
+	}
+
+	/* not the first packet - enqueue at the tail */
+	prev = chan->tail;
+	writel((u32)desc, &prev->hw_next);
+	chan->tail = desc;
+
+	/* next check if EOQ has been triggered already */
+	if (readl(&prev->hw_mode) & CPDMA_DESC_EOQ)
+		writel((u32)desc, chan->hdp);
+
+done:
+	if (chan->rxfree)
+		writel(1, chan->rxfree);
+	return 0;
+}
+
+static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
+			 void **buffer, int *len)
+{
+	struct cpdma_desc *desc = chan->head;
+	u32 status;
+
+	if (!desc)
+		return -ENOENT;
+
+	status = readl(&desc->hw_mode);
+
+	if (len)
+		*len = status & 0x7ff;
+
+	if (buffer)
+		*buffer = (void *)readl(&desc->sw_buffer);
+
+	if (status & CPDMA_DESC_OWNER)
+		return -EBUSY;
+
+	chan->head = (void *)readl(&desc->hw_next);
+
+	writel((u32)desc, chan->cp);
+
+	cpdma_desc_free(priv, desc);
+
+	return 0;
+}
+
+static int cpsw_init(struct eth_device *edev)
+{
+	return 0;
+}
+
+static int cpsw_open(struct eth_device *edev)
+{
+	struct cpsw_priv *priv = edev->priv;
+	struct cpsw_slave_data	*slave_data = priv->data.slave_data;
+	int i, ret;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	ret = phy_device_connect(edev, &priv->miibus, slave_data[0].phy_id,
+				 cpsw_adjust_link, 0, slave_data[0].phy_if);
+	if (ret)
+		return ret;
+
+	/* soft reset the controller and initialize priv */
+	soft_reset(priv, &priv->regs->soft_reset);
+
+	/* initialize and reset the address lookup engine */
+	cpsw_ale_enable(priv, 1);
+	cpsw_ale_clear(priv, 1);
+	cpsw_ale_bypass(priv, 0);
+	cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
+
+	/* setup host port priority mapping */
+	writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
+	writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
+
+	/* disable priority elevation and enable statistics on all ports */
+	writel(0, &priv->regs->ptype);
+
+	/* enable statistics collection only on the host port */
+	writel(BIT(priv->host_port), &priv->regs->stat_port_en);
+
+	cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
+
+	cpsw_ale_add_ucast(priv, priv->mac_addr, priv->host_port,
+			   ALE_SECURE);
+	cpsw_ale_add_mcast(priv, ethbdaddr, 1 << priv->host_port);
+
+	for_each_slave(priv, cpsw_slave_init, priv);
+
+	cpsw_update_link(priv);
+
+	/* init descriptor pool */
+	for (i = 0; i < NUM_DESCS; i++) {
+		u32 val = (i == (NUM_DESCS - 1)) ? 0 : (u32)&priv->descs[i + 1];
+
+		writel(val, &priv->descs[i].hw_next);
+	}
+
+	priv->desc_free = &priv->descs[0];
+
+	/* initialize channels */
+	memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
+	priv->rx_chan.hdp	= priv->state_ram + STATERAM_RXHDP;
+	priv->rx_chan.cp	= priv->state_ram + STATERAM_RXCP;
+	priv->rx_chan.rxfree	= priv->dma_regs + CPDMA_RXFREE;
+
+	memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
+	priv->tx_chan.hdp	= priv->state_ram + STATERAM_TXHDP;
+	priv->tx_chan.cp	= priv->state_ram + STATERAM_TXCP;
+
+	/* clear dma state */
+	soft_reset(priv, priv->dma_regs + CPDMA_SOFTRESET);
+
+	for (i = 0; i < priv->channels; i++) {
+		writel(0, priv->state_ram + STATERAM_RXHDP + 4 * i);
+		writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
+		writel(0, priv->state_ram + STATERAM_RXCP + 4 * i);
+		writel(0, priv->state_ram + STATERAM_TXHDP + 4 * i);
+		writel(0, priv->state_ram + STATERAM_TXCP + 4 * i);
+	}
+
+	writel(1, priv->dma_regs + CPDMA_TXCONTROL);
+	writel(1, priv->dma_regs + CPDMA_RXCONTROL);
+
+	/* submit rx descs */
+	for (i = 0; i < PKTBUFSRX - 2; i++) {
+		ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
+				   PKTSIZE);
+		if (ret < 0) {
+			dev_err(priv->dev, "error %d submitting rx desc\n", ret);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static void cpsw_halt(struct eth_device *dev)
+{
+	struct cpsw_priv	*priv = dev->priv;
+
+	writel(0, priv->dma_regs + CPDMA_TXCONTROL);
+	writel(0, priv->dma_regs + CPDMA_RXCONTROL);
+
+	/* soft reset the controller */
+	soft_reset(priv, &priv->regs->soft_reset);
+
+	/* clear dma state */
+	soft_reset(priv, priv->dma_regs + CPDMA_SOFTRESET);
+}
+
+static int cpsw_send(struct eth_device *dev, void *packet, int length)
+{
+	struct cpsw_priv	*priv = dev->priv;
+	void *buffer;
+	int ret, len;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	/* first reap completed packets */
+	while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0);
+
+	dev_dbg(priv->dev, "%s: %i bytes @ 0x%p\n", __func__, length, packet);
+
+	dma_flush_range((ulong) packet, (ulong)packet + length);
+
+	ret = cpdma_submit(priv, &priv->tx_chan, packet, length);
+
+	return ret;
+}
+
+static int cpsw_recv(struct eth_device *dev)
+{
+	struct cpsw_priv	*priv = dev->priv;
+	void *buffer;
+	int len;
+
+	while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
+		dma_inv_range((ulong)buffer, (ulong)buffer + len);
+		net_receive(buffer, len);
+		cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
+	}
+
+	return 0;
+}
+
+static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
+			    struct cpsw_priv *priv)
+{
+	void			*regs = priv->regs;
+	struct cpsw_slave_data	*data = priv->data.slave_data + slave_num;
+
+	dev_dbg(priv->dev, "* %s\n", __func__);
+
+	slave->slave_num = slave_num;
+	slave->data	= data;
+	slave->regs	= regs + priv->slave_ofs + priv->slave_size * slave_num;
+	slave->sliver	= regs + priv->sliver_ofs + SLIVER_SIZE * slave_num;
+}
+
+struct cpsw_data {
+	unsigned int host_port_reg_ofs;
+	unsigned int cpdma_reg_ofs;
+	unsigned int ale_reg_ofs;
+	unsigned int state_ram_ofs;
+	unsigned int slave_ofs;
+	unsigned int slave_size;
+	unsigned int sliver_ofs;
+	unsigned int mdio_reg_ofs;
+	unsigned int cppi_ram_ofs;
+};
+
+static struct cpsw_data cpsw1_data = {
+	.host_port_reg_ofs	= 0x028,
+	.cpdma_reg_ofs		= 0x100,
+	.state_ram_ofs		= 0x200,
+	.ale_reg_ofs		= 0x600,
+	.slave_ofs		= 0x050,
+	.slave_size		= 0x040,
+	.sliver_ofs		= 0x700,
+	/* FIXME: mdio_reg_ofs and cppi_ram_ofs missing */
+};
+
+static struct cpsw_data cpsw2_data = {
+	.host_port_reg_ofs	= 0x108,
+	.cpdma_reg_ofs		= 0x800,
+	.state_ram_ofs		= 0xa00,
+	.ale_reg_ofs		= 0xd00,
+	.slave_ofs		= 0x200,
+	.slave_size		= 0x100,
+	.sliver_ofs		= 0xd80,
+	.mdio_reg_ofs		= 0x1000,
+	.cppi_ram_ofs		= 0x2000,
+};
+
+int cpsw_probe(struct device_d *dev)
+{
+	struct cpsw_platform_data *data = (struct cpsw_platform_data *)dev->platform_data;
+	struct cpsw_priv	*priv;
+	void __iomem		*regs;
+	struct eth_device	*edev;
+	uint64_t start;
+	uint32_t phy_mask;
+	struct cpsw_data *cpsw_data;
+
+	dev_dbg(dev, "* %s\n", __func__);
+
+	regs = dev_request_mem_region(dev, 0);
+
+	priv = xzalloc(sizeof(*priv));
+	priv->dev = dev;
+	priv->data = *data;
+	priv->channels = 8;
+	priv->num_slaves = data->num_slaves;
+	priv->ale_entries = 1024;
+	edev = &priv->edev;
+
+	priv->slaves = xzalloc(sizeof(struct cpsw_slave) * priv->num_slaves);
+
+	priv->host_port         = 0;
+	priv->regs		= regs;
+
+	priv->version = readl(&priv->regs->id_ver);
+
+	switch (priv->version) {
+	case CPSW_VERSION_1:
+		cpsw_data = &cpsw1_data;
+		break;
+	case CPSW_VERSION_2:
+		cpsw_data = &cpsw2_data;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	priv->descs		= regs + cpsw_data->cppi_ram_ofs;
+	priv->host_port_regs	= regs + cpsw_data->host_port_reg_ofs;
+	priv->dma_regs		= regs + cpsw_data->cpdma_reg_ofs;
+	priv->ale_regs		= regs + cpsw_data->ale_reg_ofs;
+	priv->state_ram		= regs + cpsw_data->state_ram_ofs;
+	priv->mdio_regs		= regs + cpsw_data->mdio_reg_ofs;
+
+	priv->slave_ofs		= cpsw_data->slave_ofs;
+	priv->slave_size	= cpsw_data->slave_size;
+	priv->sliver_ofs	= cpsw_data->sliver_ofs;
+
+	for_each_slave(priv, cpsw_slave_setup, idx, priv);
+
+	edev->priv	= priv;
+	edev->init	= cpsw_init;
+	edev->open	= cpsw_open;
+	edev->halt	= cpsw_halt;
+	edev->send	= cpsw_send;
+	edev->recv	= cpsw_recv;
+	edev->get_ethaddr = cpsw_get_hwaddr;
+	edev->set_ethaddr = cpsw_set_hwaddr;
+	edev->parent	= dev;
+
+	priv->miibus.read = cpsw_mdio_read;
+	priv->miibus.write = cpsw_mdio_write;
+	priv->miibus.priv = priv;
+	priv->miibus.parent = dev;
+
+	/*
+	 * set enable and clock divider
+	 *
+	 * FIXME: Use a clock to calculate the divider
+	 */
+	writel(0xff | CONTROL_ENABLE, &priv->mdio_regs->control);
+
+	/*
+	 * wait for scan logic to settle:
+	 * the scan time consists of (a) a large fixed component, and (b) a
+	 * small component that varies with the mii bus frequency.  These
+	 * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
+	 * silicon.  Since the effect of (b) was found to be largely
+	 * negligible, we keep things simple here.
+	 */
+	udelay(1000);
+
+	start = get_time_ns();
+	while (1) {
+		phy_mask = readl(&priv->mdio_regs->alive);
+		if (phy_mask) {
+			dev_info(dev, "detected phy mask 0x%x\n", phy_mask);
+			phy_mask = ~phy_mask;
+			break;
+		}
+		if (is_timeout(start, 256 * MSECOND)) {
+			dev_err(dev, "no live phy, scanning all\n");
+			phy_mask = 0;
+			break;
+		}
+	}
+
+	priv->miibus.phy_mask = phy_mask;
+
+	mdiobus_register(&priv->miibus);
+
+	eth_register(edev);
+
+	return 0;
+}
+
+static struct driver_d cpsw_driver = {
+	.name   = "cpsw",
+	.probe  = cpsw_probe,
+};
+
+static int cpsw_register(void)
+{
+	return platform_driver_register(&cpsw_driver);
+}
+
+device_initcall(cpsw_register);

From cee6e122ffc0b1fd6a90613f283626be899f812b Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Wed, 9 Jan 2013 11:39:56 +0100
Subject: [PATCH 02/16] ARM am33xx: Add cpws convenience functions

This adds a function to register the cpws device and another one
to register the MAC addresses provided by the am33xx.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/am33xx_generic.c           | 27 +++++++++++++++++++
 .../mach-omap/include/mach/am33xx-devices.h   |  7 +++++
 .../mach-omap/include/mach/am33xx-generic.h   |  6 +++++
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/mach-omap/include/mach/am33xx-generic.h

diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index e8293f7b9..d3014c20b 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -18,11 +18,14 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
 #include <io.h>
+#include <net.h>
 #include <mach/am33xx-silicon.h>
 #include <mach/am33xx-clock.h>
 #include <mach/sys_info.h>
 #include <mach/xload.h>
+#include <mach/am33xx-generic.h>
 
 void __noreturn reset_cpu(unsigned long addr)
 {
@@ -95,3 +98,27 @@ enum omap_boot_src am33xx_bootsrc(void)
 {
 	return OMAP_BOOTSRC_MMC1; /* only MMC for now */
 }
+
+int am33xx_register_ethaddr(int eth_id, int mac_id)
+{
+	void __iomem *mac_id_low = (void *)AM33XX_MAC_ID0_LO + mac_id * 8;
+	void __iomem *mac_id_high = (void *)AM33XX_MAC_ID0_HI + mac_id * 8;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	mac_lo = readl(mac_id_low);
+	mac_hi = readl(mac_id_high);
+	mac_addr[0] = mac_hi & 0xff;
+	mac_addr[1] = (mac_hi & 0xff00) >> 8;
+	mac_addr[2] = (mac_hi & 0xff0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xff000000) >> 24;
+	mac_addr[4] = mac_lo & 0xff;
+	mac_addr[5] = (mac_lo & 0xff00) >> 8;
+
+	if (is_valid_ether_addr(mac_addr)) {
+		eth_register_ethaddr(eth_id, mac_addr);
+		return 0;
+	}
+
+	return -ENODEV;
+}
diff --git a/arch/arm/mach-omap/include/mach/am33xx-devices.h b/arch/arm/mach-omap/include/mach/am33xx-devices.h
index c194303a5..fe9fba996 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-devices.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-devices.h
@@ -6,6 +6,7 @@
 #include <mach/am33xx-silicon.h>
 #include <mach/devices.h>
 #include <mach/omap_hsmmc.h>
+#include <mach/cpsw.h>
 
 /* the device numbering is the same as in the TRM memory map (SPRUH73G) */
 
@@ -30,4 +31,10 @@ static inline struct device_d *am33xx_add_mmc0(struct omap_hsmmc_platform_data *
 			AM33XX_MMCHS0_BASE, SZ_4K, IORESOURCE_MEM, pdata);
 }
 
+static inline struct device_d *am33xx_add_cpsw(struct cpsw_platform_data *cpsw_data)
+{
+	return add_generic_device("cpsw", 0, NULL,
+			AM335X_CPSW_BASE, SZ_32K, IORESOURCE_MEM, cpsw_data);
+}
+
 #endif /* __MACH_OMAP3_DEVICES_H */
diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h
new file mode 100644
index 000000000..ba69caf31
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/am33xx-generic.h
@@ -0,0 +1,6 @@
+#ifndef __MACH_AM33XX_GENERIC_H
+#define __MACH_AM33XX_GENERIC_H
+
+int am33xx_register_ethaddr(int eth_id, int mac_id);
+
+#endif /* __MACH_AM33XX_GENERIC_H */

From bfe2fad5f26e138eb5ae362aa79aaa4c0673a8fe Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Wed, 9 Jan 2013 11:41:12 +0100
Subject: [PATCH 03/16] ARM beaglebone: Add network support

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/beaglebone/board.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index f9ac7a469..fddfd0388 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -31,6 +31,7 @@
 #include <sizes.h>
 #include <io.h>
 #include <ns16550.h>
+#include <net.h>
 #include <asm/armlinux.h>
 #include <generated/mach-types.h>
 #include <mach/am33xx-silicon.h>
@@ -42,11 +43,14 @@
 #include <mach/ehci.h>
 #include <i2c/i2c.h>
 #include <linux/err.h>
+#include <linux/phy.h>
 #include <usb/ehci.h>
 #include <mach/xload.h>
 #include <mach/am33xx-devices.h>
 #include <mach/am33xx-mux.h>
 #include <mach/wdt.h>
+#include <mach/am33xx-generic.h>
+#include <mach/cpsw.h>
 
 /* UART Defines */
 #define UART_SYSCFG_OFFSET  (0x54)
@@ -313,11 +317,35 @@ static int beaglebone_mem_init(void)
 }
 mem_initcall(beaglebone_mem_init);
 
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.phy_id		= 0,
+		.phy_if		= PHY_INTERFACE_MODE_MII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.slave_data		= cpsw_slaves,
+	.num_slaves		= ARRAY_SIZE(cpsw_slaves),
+};
+
+static void beaglebone_eth_init(void)
+{
+	am33xx_register_ethaddr(0, 0);
+
+	writel(0, AM33XX_MAC_MII_SEL);
+
+	enable_mii1_pin_mux();
+
+	am33xx_add_cpsw(&cpsw_data);
+}
+
 static int beaglebone_devices_init(void)
 {
 	am33xx_add_mmc0(NULL);
 
 	enable_i2c0_pin_mux();
+	beaglebone_eth_init();
 
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_BEAGLEBONE);

From d174218c098ba04f3c57fc79c7e6eff179bc756b Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Wed, 9 Jan 2013 11:53:25 +0100
Subject: [PATCH 04/16] ARM beaglebone: update defconfig for networking

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/configs/am335x_beaglebone_defconfig | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/configs/am335x_beaglebone_defconfig b/arch/arm/configs/am335x_beaglebone_defconfig
index 2066d9c93..4e37e0163 100644
--- a/arch/arm/configs/am335x_beaglebone_defconfig
+++ b/arch/arm/configs/am335x_beaglebone_defconfig
@@ -17,6 +17,7 @@ CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/beaglebone/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
+CONFIG_CMD_MSLEEP=y
 CONFIG_CMD_SAVEENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
@@ -24,10 +25,17 @@ CONFIG_CMD_READLINE=y
 CONFIG_CMD_MENU=y
 CONFIG_CMD_MENU_MANAGEMENT=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_DIRNAME=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_READLINK=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_FILETYPE=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
 CONFIG_CMD_CRC=y
 CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
 CONFIG_CMD_BOOTM_VERBOSE=y
 CONFIG_CMD_BOOTM_INITRD=y
@@ -43,12 +51,21 @@ CONFIG_CMD_MAGICVAR=y
 CONFIG_CMD_MAGICVAR_HELP=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_SERIAL_NS16550=y
 CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+CONFIG_DRIVER_NET_CPSW=y
 # CONFIG_SPI is not set
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
 CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y

From 753394a991dc0d694ea9e77b5cfd5711fbe6def2 Mon Sep 17 00:00:00 2001
From: Vicente Bergas <vicencb@gmail.com>
Date: Thu, 17 Jan 2013 02:39:18 +0100
Subject: [PATCH 05/16] OMAP4: use OPPs recommended in datasheet

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/include/mach/omap4-clock.h | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h
index 469c71679..8f49aa376 100644
--- a/arch/arm/mach-omap/include/mach/omap4-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap4-clock.h
@@ -307,7 +307,9 @@ struct dpll_param {
 #define OMAP4_MPU_DPLL_PARAM_38M4_MPU600	{0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 #define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000	{0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 /* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
-#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920	{0x23F, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920	{0x30, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1200	{0x7d, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
+#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1500	{0x4e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
 
 #define OMAP4_IVA_DPLL_PARAM_19M2		{0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
 #define OMAP4_IVA_DPLL_PARAM_38M4		{0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}
@@ -321,11 +323,11 @@ struct dpll_param {
 #define OMAP4_USB_DPLL_PARAM_19M2		{0x32, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}
 #define OMAP4_USB_DPLL_PARAM_38M4		{0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}
 
-#define OMAP4_CORE_DPLL_PARAM_19M2_DDR200	{0x7d, 0x02, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}
+#define OMAP4_CORE_DPLL_PARAM_19M2_DDR200	{0x7d, 0x02, 0x02, 0x05, 0x08, 0x04, 0x06, 0x06}
 #define OMAP4_CORE_DPLL_PARAM_19M2_DDR333	{0x410,	0x09, 0x03, 0x0c, 0x14, 0x0a, 0x0f, 0x0c}
-#define OMAP4_CORE_DPLL_PARAM_19M2_DDR400	{0x7d, 0x02, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}
-#define OMAP4_CORE_DPLL_PARAM_38M4_DDR200	{0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}
-#define OMAP4_CORE_DPLL_PARAM_38M4_DDR400	{0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}
+#define OMAP4_CORE_DPLL_PARAM_19M2_DDR400	{0x7d, 0x02, 0x01, 0x05, 0x08, 0x04, 0x06, 0x06}
+#define OMAP4_CORE_DPLL_PARAM_38M4_DDR200	{0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x06}
+#define OMAP4_CORE_DPLL_PARAM_38M4_DDR400	{0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x06}
 
 void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param);
 void omap4_configure_iva_dpll(const struct dpll_param *dpll_param);

From b13920c0d1f23c54b5a660ea54ea5bb839ea9a88 Mon Sep 17 00:00:00 2001
From: Vicente Bergas <vicencb@gmail.com>
Date: Thu, 17 Jan 2013 02:39:19 +0100
Subject: [PATCH 06/16] OMAP4_USB: more stable communications

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 scripts/omap4_usbboot.c | 68 +++++++++++++++++++++++++----------------
 scripts/usb_linux.c     |  4 +--
 2 files changed, 44 insertions(+), 28 deletions(-)

diff --git a/scripts/omap4_usbboot.c b/scripts/omap4_usbboot.c
index a276c2923..8c5775d84 100644
--- a/scripts/omap4_usbboot.c
+++ b/scripts/omap4_usbboot.c
@@ -41,10 +41,17 @@
 #define host_print(fmt, arg...)	printf(FORMAT fmt FORMAT, \
 					HOST_FORMAT, ##arg, TARGET_FORMAT)
 
+void panic(struct termios *t_restore)
+{
+	tcsetattr(STDIN_FILENO, TCSANOW, t_restore);
+	printf(FORMAT, HOST_FORMAT);
+	exit(1);
+}
+
 struct thread_vars {
 	struct usb_handle *usb;
-	int hide;
-	struct termios to;
+	pthread_mutex_t usb_mutex;
+	struct termios t_restore;
 };
 
 void *listenerTask(void *argument)
@@ -55,13 +62,12 @@ void *listenerTask(void *argument)
 		c = getchar();
 		if (c == EOF)
 			return NULL;
-		while (vars->hide)
-			usleep(10000);
+		pthread_mutex_lock(&vars->usb_mutex);
 		if (usb_write(vars->usb, &c, 4) != 4) {
 			host_print("could not send '%c' to target\n", c);
-			tcsetattr(STDIN_FILENO, TCSANOW, &vars->to);
-			exit(1);
+			panic(&vars->t_restore);
 		}
+		pthread_mutex_unlock(&vars->usb_mutex);
 	}
 	return NULL;
 }
@@ -168,8 +174,8 @@ struct file_data {
 	void *data;
 };
 
-int process_file(
-	struct usb_handle *usb, const char *rootfs, struct file_data *fd_vector)
+int process_file(struct usb_handle *usb, const char *rootfs,
+	struct file_data *fd_vector, struct termios *t_restore)
 {
 	uint32_t i, j, pos, size;
 	struct stat s;
@@ -178,7 +184,7 @@ int process_file(
 
 	if (usb_read(usb, &i, 4) != 4) {
 		host_print("USB error\n");
-		exit(1);
+		panic(t_restore);
 	}
 	ret = 0;
 	switch (i) {
@@ -188,7 +194,7 @@ int process_file(
 		for (;; j++) {
 			if (usb_read(usb, &i, 4) != 4) {
 				host_print("USB error\n");
-				exit(1);
+				panic(t_restore);
 			}
 			if (i == USBBOOT_FS_CMD_END) {
 				fname[j] = 0;
@@ -242,13 +248,13 @@ open_ok:
 			usb_write(usb, &size, 4) != 4
 		) {
 			host_print("could not send file size to target\n");
-			exit(1);
+			panic(t_restore);
 		}
 		break;
 	case USBBOOT_FS_CMD_CLOSE:
 		if (usb_read(usb, &i, 4) != 4) {
 			host_print("USB error\n");
-			exit(1);
+			panic(t_restore);
 		}
 		if (i >= MAX_OPEN_FILES || !fd_vector[i].data) {
 			host_print("invalid close index\n");
@@ -257,7 +263,7 @@ open_ok:
 		}
 		if (usb_read(usb, &j, 4) != 4) {
 			host_print("USB error\n");
-			exit(1);
+			panic(t_restore);
 		}
 		if (j != USBBOOT_FS_CMD_END) {
 			host_print("invalid close\n");
@@ -270,7 +276,7 @@ open_ok:
 	case USBBOOT_FS_CMD_READ:
 		if (usb_read(usb, &i, 4) != 4) {
 			host_print("USB error\n");
-			exit(1);
+			panic(t_restore);
 		}
 		if (i >= MAX_OPEN_FILES || !fd_vector[i].data) {
 			host_print("invalid read index\n");
@@ -279,7 +285,7 @@ open_ok:
 		}
 		if (usb_read(usb, &pos, 4) != 4) {
 			host_print("USB error\n");
-			exit(1);
+			panic(t_restore);
 		}
 		if (pos >= fd_vector[i].size) {
 			host_print("invalid read pos\n");
@@ -288,7 +294,7 @@ open_ok:
 		}
 		if (usb_read(usb, &size, 4) != 4) {
 			host_print("USB error\n");
-			exit(1);
+			panic(t_restore);
 		}
 		if (pos+size > fd_vector[i].size) {
 			host_print("invalid read size\n");
@@ -297,7 +303,7 @@ open_ok:
 		}
 		if (usb_read(usb, &j, 4) != 4) {
 			host_print("USB error\n");
-			exit(1);
+			panic(t_restore);
 		}
 		if (j != USBBOOT_FS_CMD_END) {
 			host_print("invalid read\n");
@@ -306,7 +312,7 @@ open_ok:
 		}
 		if (usb_write(usb, fd_vector[i].data+pos, size) != size) {
 			host_print("could not send file to target\n");
-			exit(1);
+			panic(t_restore);
 		}
 		break;
 	case USBBOOT_FS_CMD_END:
@@ -329,38 +335,48 @@ int usb_boot(
 	struct termios tn;
 	struct file_data fd_vector[MAX_OPEN_FILES];
 
-	read_asic_id(usb);
+	if (read_asic_id(usb))
+		return -1;
 
 	printf("sending xload to target...\n");
+	usleep(1000);
 	usb_write(usb, &msg_boot, sizeof(msg_boot));
+	usleep(1000);
 	usb_write(usb, &msg_size, sizeof(msg_size));
+	usleep(1000);
 	usb_write(usb, data, sz);
+	usleep(100000);
 	munmap(data, msg_size);
 	for (i = 0; i < MAX_OPEN_FILES; i++)
 		fd_vector[i].data = NULL;
 
 	vars.usb = usb;
-	vars.hide = 0;
-	tcgetattr(STDIN_FILENO, &vars.to);
-	tn = vars.to;
+	pthread_mutex_init(&vars.usb_mutex, NULL);
+	tcgetattr(STDIN_FILENO, &vars.t_restore);
+	tn = vars.t_restore;
 	tn.c_lflag &= ~(ICANON | ECHO);
 	printf(FORMAT, TARGET_FORMAT);
 	tcsetattr(STDIN_FILENO, TCSANOW, &tn);
 	if (pthread_create(&thread, NULL, listenerTask, &vars))
 		host_print("listenerTask failed\n");
 	for (;;) {
+		usleep(100);
 		if (usb_read(usb, &i, 4) != 4)
 			break;
 		if (i == USBBOOT_FS_MAGIC) {
-			vars.hide = 1;
-			process_file(usb, rootfs, fd_vector);
-			vars.hide = 0;
+			usleep(100);
+			pthread_mutex_lock(&vars.usb_mutex);
+			process_file(usb, rootfs, fd_vector, &vars.t_restore);
+			pthread_mutex_unlock(&vars.usb_mutex);
 			continue;
 		}
 		printf("%c", i);
 		fflush(stdout);
 	}
-	tcsetattr(STDIN_FILENO, TCSANOW, &vars.to);
+	usb_close(usb);
+	pthread_mutex_destroy(&vars.usb_mutex);
+	tcsetattr(STDIN_FILENO, TCSANOW, &vars.t_restore);
+	printf(FORMAT, HOST_FORMAT);
 	return 0;
 }
 
diff --git a/scripts/usb_linux.c b/scripts/usb_linux.c
index 43529aaf1..9a6e0b84d 100644
--- a/scripts/usb_linux.c
+++ b/scripts/usb_linux.c
@@ -47,7 +47,7 @@
 
 #include "usb.h"
 
-#define MAX_RETRIES 5
+#define MAX_RETRIES 2
 
 #ifdef TRACE_USB
 #define DBG1(x...) fprintf(stderr, x)
@@ -350,7 +350,7 @@ int usb_read(struct usb_handle *h, void *_data, int len)
 				n, errno, strerror(errno));
 				if (++retry > MAX_RETRIES)
 					return -1;
-				sleep(1);
+				usleep(10000);
 			}
 		} while (n < 0);
 

From 63d11f044a5fdfaf72ce983f7c6f297b32885a97 Mon Sep 17 00:00:00 2001
From: Vicente Bergas <vicencb@gmail.com>
Date: Thu, 17 Jan 2013 02:39:20 +0100
Subject: [PATCH 07/16] ARCHOS: use manufacturer values for pad_conf and
 reorder initialization

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/archosg9/board.c    |   1 +
 arch/arm/boards/archosg9/lowlevel.c |  16 +-
 arch/arm/boards/archosg9/mux.c      | 654 ++++++++++------------------
 3 files changed, 242 insertions(+), 429 deletions(-)

diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c
index 1911c62de..200fe9295 100644
--- a/arch/arm/boards/archosg9/board.c
+++ b/arch/arm/boards/archosg9/board.c
@@ -58,6 +58,7 @@ static int archosg9_devices_init(void){
 	 * So here there is the hardcoded value
 	 */
 	armlinux_set_architecture(5032);
+	armlinux_set_revision(5);
 
 	return 0;
 }
diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c
index d0506bb60..aea6342bb 100644
--- a/arch/arm/boards/archosg9/lowlevel.c
+++ b/arch/arm/boards/archosg9/lowlevel.c
@@ -39,12 +39,19 @@ static const struct ddr_regs ddr_regs_400_mhz_2cs = {
 static noinline void archosg9_init_lowlevel(void)
 {
 	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
-	struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU600;
+	struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1200;
 	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
 	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
 	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
 	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;
 
+	set_muxconf_regs();
+
+	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
+	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
+
+	/* Enable all clocks */
+	omap4_enable_all_clocks();
 	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
 
 	/* Configure all DPLL's at 100% OPP */
@@ -54,15 +61,8 @@ static noinline void archosg9_init_lowlevel(void)
 	omap4_configure_abe_dpll(&abe);
 	omap4_configure_usb_dpll(&usb);
 
-	/* Enable all clocks */
-	omap4_enable_all_clocks();
-
-	set_muxconf_regs();
-
 	omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
 
-	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
-	omap4_scale_vcores(TPS62361_VSEL0_GPIO);
 	board_init_lowlevel_return();
 }
 
diff --git a/arch/arm/boards/archosg9/mux.c b/arch/arm/boards/archosg9/mux.c
index 7ca5057d7..4fab75915 100644
--- a/arch/arm/boards/archosg9/mux.c
+++ b/arch/arm/boards/archosg9/mux.c
@@ -19,429 +19,242 @@
 #include "mux.h"
 
 static const struct pad_conf_entry core_padconf_array[] = {
-	/* sdmmc2_dat0         */ /* internal FLASH */
-	{ GPMC_AD0            ,                               IEN | PTU | M1 },
-	/* sdmmc2_dat1         */ /* internal FLASH */
-	{ GPMC_AD1            ,                               IEN | PTU | M1 },
-	/* sdmmc2_dat2         */ /* internal FLASH */
-	{ GPMC_AD2            ,                               IEN | PTU | M1 },
-	/* sdmmc2_dat3         */ /* internal FLASH */
-	{ GPMC_AD3            ,                               IEN | PTU | M1 },
-	/* sdmmc2_dat4         */ /* internal FLASH */
-	{ GPMC_AD4            ,                               IEN | PTU | M1 },
-	/* sdmmc2_dat5         */ /* internal FLASH */
-	{ GPMC_AD5            ,                               IEN | PTU | M1 },
-	/* sdmmc2_dat6         */ /* internal FLASH */
-	{ GPMC_AD6            ,                               IEN | PTU | M1 },
-	/* sdmmc2_dat7         */ /* internal FLASH */
-	{ GPMC_AD7            ,                               IEN | PTU | M1 },
-	/* gpio_32             */
-	{ GPMC_AD8            ,                               IEN | PTD | M3 },
-	/* gpmc_ad9            */
-	{ GPMC_AD9            ,                               IEN | PTU | M0 },
-	/* gpio_34             */ /* 1v8_pwron */
-	{ GPMC_AD10           ,                               IEN | PTU | M3 },
-	/* gpio_35             */ /* vcc_pwron */
-	{ GPMC_AD11           ,                               IEN | PTU | M3 },
-	/* gpio_36             */ /* 5v_pwron */
-	{ GPMC_AD12           ,                               IEN       | M3 },
-	/* gpio_37             */ /* hdmi_pwr */
-	{ GPMC_AD13           ,                               IEN       | M3 },
-	/* gpio_38             */ /* lcd_pwon */
-	{ GPMC_AD14           ,                               IEN       | M3 },
-	/* gpio_39             */ /* lvds_en */
-	{ GPMC_AD15           ,                               IEN       | M3 },
-	/* gpio_40             */ /* 3g_enable */
-	{ GPMC_A16            ,                               IEN       | M3 },
-	/* gpio_41             */ /* gps_enable */
-	{ GPMC_A17            ,                               IEN       | M3 },
-	/* gpio_42             */ /* ehci_enable */
-	{ GPMC_A18            ,                               IEN       | M3 },
-	/* gpio_43             */ /* volume up */
-	{ GPMC_A19            ,                               IEN       | M3 },
-	/* gpio_44             */ /* volume down */
-	{ GPMC_A20            ,                               IEN       | M3 },
-	/* gpio_45             */ /* accel_int1 */
-	{ GPMC_A21            ,                               IEN | PTU | M3 },
-	/* kpd_col6            */
-	{ GPMC_A22            ,                               IEN | PTD | M1 },
-	/* kpd_col7            */
-	{ GPMC_A23            ,                               IEN | PTD | M1 },
-	/* gpio_48             */ /* vbus_detect */
-	{ GPMC_A24            ,                               IEN       | M3 },
-	/* gpio_49             */ /* id */
-	{ GPMC_A25            ,                               IEN | PTU | M3 },
-	/* gpmc_ncs0           */
-	{ GPMC_NCS0           ,                               IEN | PTU | M0 },
-	/* gpio_51             */ /* compass_data_ready */
-	{ GPMC_NCS1           ,                               IEN       | M3 },
-	/* safe_mode           */
-	{ GPMC_NCS2           ,                               IEN | PTU | M7 },
-	/* gpio_53             */ /* lcd_rst */
-	{ GPMC_NCS3           ,                               IEN       | M3 },
-	/* gpmc_nwp            */
-	{ GPMC_NWP            ,                               IEN | PTD | M0 },
-	/* gpmc_clk            */
-	{ GPMC_CLK            ,                               IEN | PTD | M0 },
-	/* gpmc_nadv_ale       */
-	{ GPMC_NADV_ALE       ,                               IEN | PTD | M0 },
-	/* sdmmc2_clk          */ /* internal FLASH */
-	{ GPMC_NOE            ,                               IEN | PTU | M1 },
-	/* sdmmc2_cmd          */ /* internal FLASH */
-	{ GPMC_NWE            ,                               IEN | PTU | M1 },
-	/* gpmc_nbe0_cle       */
-	{ GPMC_NBE0_CLE       ,                               IEN | PTD | M0 },
-	/* safe_mode           */
-	{ GPMC_NBE1           ,                               IEN | PTD | M7 },
-	/* gpmc_wait0          */
-	{ GPMC_WAIT0          ,                               IEN | PTU | M0 },
-	/* gpio_62             */ /* camera_reset */
-	{ GPMC_WAIT1          ,                               IEN       | M3 },
-	/* safe_mode           */
-	{ GPMC_WAIT2          ,                               IEN | PTD | M7 },
-	/* gpio_101            */ /* lcd_stdby */
-	{ GPMC_NCS4           ,                                           M3 },
-	/* gpio_102            */ /* wifi_irq */
-	{ GPMC_NCS5           ,                               IEN       | M3 },
-	/* gpio_103            */ /* wifi_power */
-	{ GPMC_NCS6           ,                                           M3 },
-	/* gpio_104            */ /* bt_power */
-	{ GPMC_NCS7           ,                               IEN       | M3 },
-	/* gpio_63             */ /* hdmi_hpd ?? */
-	{ GPIO63              ,                               IEN | PTD | M3 },
-	/*                     */
-	{ GPIO64              ,                               IEN       | M0 },
-	/*                     */
-	{ GPIO65              ,                               IEN       | M0 },
-	/*                     */
-	{ GPIO66              ,                               IEN       | M0 },
-	/* csi21_dx0           */
-	{ CSI21_DX0           ,                               IEN       | M0 },
-	/* csi21_dy0           */
-	{ CSI21_DY0           ,                               IEN       | M0 },
-	/* csi21_dx1           */
-	{ CSI21_DX1           ,                               IEN       | M0 },
-	/* csi21_dy1           */
-	{ CSI21_DY1           ,                               IEN       | M0 },
-	/* safe_mode           */
-	{ CSI21_DX2           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI21_DY2           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI21_DX3           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI21_DY3           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI21_DX4           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI21_DY4           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI22_DX0           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI22_DY0           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI22_DX1           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI22_DY1           ,                               IEN | PTD | M7 },
-	/* cam_shutter         */
-	{ CAM_SHUTTER         ,                                     PTD | M0 },
-	/* cam_strobe          */
-	{ CAM_STROBE          ,                                     PTD | M0 },
-	/* gpio_83             */
-	{ CAM_GLOBALRESET     ,                                     PTD | M3 },
-	/* usbb1_ulpiphy_clk   */
-	{ USBB1_ULPITLL_CLK   ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_stp   */
-	{ USBB1_ULPITLL_STP   ,                                           M4 },
-	/* usbb1_ulpiphy_dir   */
-	{ USBB1_ULPITLL_DIR   ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_nxt   */
-	{ USBB1_ULPITLL_NXT   ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_dat0  */
-	{ USBB1_ULPITLL_DAT0  , WAKEUP_EN                   | IEN | PTD | M4 },
-	/* usbb1_ulpiphy_dat1  */
-	{ USBB1_ULPITLL_DAT1  ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_dat2  */
-	{ USBB1_ULPITLL_DAT2  ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_dat3  */
-	{ USBB1_ULPITLL_DAT3  ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_dat4  */
-	{ USBB1_ULPITLL_DAT4  ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_dat5  */
-	{ USBB1_ULPITLL_DAT5  ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_dat6  */
-	{ USBB1_ULPITLL_DAT6  ,                               IEN | PTD | M4 },
-	/* usbb1_ulpiphy_dat7  */
-	{ USBB1_ULPITLL_DAT7  ,                               IEN | PTD | M4 },
-	/* usbb1_hsic_data     */
-	{ USBB1_HSIC_DATA     ,                                           M0 },
-	/* usbb1_hsic_strobe   */
-	{ USBB1_HSIC_STROBE   ,                                           M0 },
-	/* usbc1_icusb_dp      */
-	{ USBC1_ICUSB_DP      ,                                           M0 },
-	/* usbc1_icusb_dm      */
-	{ USBC1_ICUSB_DM      ,                                           M0 },
-	/* sdmmc1_clk          */ /* SD card */
-	{ SDMMC1_CLK          ,                                     PTU | M0 },
-	/* sdmmc1_cmd          */ /* SD card */
-	{ SDMMC1_CMD          ,                               IEN | PTU | M0 },
-	/* sdmmc1_dat0         */ /* SD card */
-	{ SDMMC1_DAT0         ,                               IEN | PTU | M0 },
-	/* sdmmc1_dat1         */ /* SD card */
-	{ SDMMC1_DAT1         ,                               IEN | PTU | M0 },
-	/* sdmmc1_dat2         */ /* SD card */
-	{ SDMMC1_DAT2         ,                               IEN | PTU | M0 },
-	/* sdmmc1_dat3         */ /* SD card */
-	{ SDMMC1_DAT3         ,                               IEN | PTU | M0 },
-	/* sdmmc1_dat4         */ /* SD card */
-	{ SDMMC1_DAT4         ,                               IEN | PTU | M0 },
-	/* sdmmc1_dat5         */ /* SD card */
-	{ SDMMC1_DAT5         ,                               IEN | PTU | M0 },
-	/* sdmmc1_dat6         */ /* SD card */
-	{ SDMMC1_DAT6         ,                               IEN | PTU | M0 },
-	/* sdmmc1_dat7         */ /* SD card */
-	{ SDMMC1_DAT7         ,                               IEN | PTU | M0 },
-	/* gpio_110            */ /* tsp_pwr_gpio */
-	{ ABE_MCBSP2_CLKX     ,                                           M3 },
-	/* gpio_111            */ /* vbus_musb_pwron */
-	{ ABE_MCBSP2_DR       ,                               IEN       | M3 },
-	/* gpio_112            */ /* tsp_irq_gpio */
-	{ ABE_MCBSP2_DX       , WAKEUP_EN                   | IEN | PTU | M3 },
-	/* gpio_113            */ /* vbus_flag */
-	{ ABE_MCBSP2_FSX      ,                               IEN | PTU | M3 },
-	/* safe_mode           */
-	{ ABE_MCBSP1_CLKX     ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ ABE_MCBSP1_DR       ,                               IEN | PTD | M7 },
-	/* abe_mcbsp1_dx       */
-	{ ABE_MCBSP1_DX       ,                                           M0 },
-	/* abe_mcbsp1_fsx      */
-	{ ABE_MCBSP1_FSX      ,                               IEN       | M0 },
-	/* abe_pdm_ul_data     */
-	{ ABE_PDM_UL_DATA     ,                               IEN       | M0 },
-	/* abe_pdm_dl_data     */
-	{ ABE_PDM_DL_DATA     ,                                           M0 },
-	/* abe_pdm_frame       */
-	{ ABE_PDM_FRAME       ,                               IEN       | M0 },
-	/* abe_pdm_lb_clk      */
-	{ ABE_PDM_LB_CLK      ,                               IEN       | M0 },
-	/* abe_clks            */
-	{ ABE_CLKS            ,                               IEN       | M0 },
-	/* safe_mode           */
-	{ ABE_DMIC_CLK1       ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ ABE_DMIC_DIN1       ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ ABE_DMIC_DIN2       ,                               IEN | PTD | M7 },
-	/* safe_mode           */ /* bkl_en on gpio_122 ?? */
-	{ ABE_DMIC_DIN3       ,                               IEN | PTD | M7 },
-	/* uart2_cts           */
-	{ UART2_CTS           , WAKEUP_EN | OFF_PU | OFF_IN             | M0 },
-	/* safe_mode           */
-	{ UART2_RTS           ,             OFF_PU | OFF_IN             | M7 },
-	/* uart2_rx            */
-	{ UART2_RX            ,                               IEN | PTU | M0 },
-	/* uart2_tx            */
-	{ UART2_TX            ,                                           M0 },
-	/* gpio_127            */ /* audio_power_on */
-	{ HDQ_SIO             ,                                           M3 },
-	/* i2c1_scl            */
-	{ I2C1_SCL            ,                               IEN       | M0 },
-	/* i2c1_sda            */
-	{ I2C1_SDA            ,                               IEN       | M0 },
-	/* i2c2_scl            */
-	{ I2C2_SCL            ,                               IEN       | M0 },
-	/* i2c2_sda            */
-	{ I2C2_SDA            ,                               IEN       | M0 },
-	/* i2c3_scl            */
-	{ I2C3_SCL            ,                               IEN       | M0 },
-	/* i2c3_sda            */
-	{ I2C3_SDA            ,                               IEN       | M0 },
-	/* i2c4_scl            */
-	{ I2C4_SCL            ,                               IEN       | M0 },
-	/* i2c4_sda            */
-	{ I2C4_SDA            ,                               IEN       | M0 },
-	/* mcspi1_clk          */
-	{ MCSPI1_CLK          ,                               IEN       | M0 },
-	/* mcspi1_somi         */
-	{ MCSPI1_SOMI         ,                               IEN       | M0 },
-	/* mcspi1_simo         */
-	{ MCSPI1_SIMO         ,                               IEN       | M0 },
-	/* mcspi1_cs0          */
-	{ MCSPI1_CS0          ,                               IEN | PTD | M0 },
-	/* uart1_rx            */
-	{ MCSPI1_CS1          , WAKEUP_EN                   | IEN       | M1 },
-	/* gpio_139            */
-	{ MCSPI1_CS2          ,                                           M3 },
-	/* safe_mode           */
-	{ MCSPI1_CS3          ,                               IEN | PTU | M7 },
-	/* uart1_tx            */
-	{ UART3_CTS_RCTX      ,                                           M1 },
-	/* uart3_rts_sd        */
-	{ UART3_RTS_SD        ,                                           M0 },
-	/* safe_mode           */
-	{ UART3_RX_IRRX       ,                               IEN | PTU | M7 },
-	/* safe_mode           */
-	{ UART3_TX_IRTX       ,                               IEN | PTD | M7 },
-	/* sdmmc5_clk          */
-	{ SDMMC5_CLK          ,                                     PTU | M0 },
-	/* sdmmc5_cmd          */
-	{ SDMMC5_CMD          ,                               IEN | PTU | M0 },
-	/* sdmmc5_dat0         */
-	{ SDMMC5_DAT0         ,                               IEN | PTU | M0 },
-	/* sdmmc5_dat1         */
-	{ SDMMC5_DAT1         ,                               IEN | PTU | M0 },
-	/* sdmmc5_dat2         */
-	{ SDMMC5_DAT2         ,                               IEN | PTU | M0 },
-	/* sdmmc5_dat3         */
-	{ SDMMC5_DAT3         ,                               IEN | PTU | M0 },
-	/* sdmmc4_clk          */
-	{ MCSPI4_CLK          ,                               IEN | PTU | M1 },
-	/* sdmmc4_cmd          */
-	{ MCSPI4_SIMO         ,                               IEN | PTU | M1 },
-	/* sdmmc4_dat0         */
-	{ MCSPI4_SOMI         ,                               IEN | PTU | M1 },
-	/* sdmmc4_dat3         */
-	{ MCSPI4_CS0          ,                               IEN | PTU | M1 },
-	/* sdmmc4_dat2         */
-	{ UART4_RX            ,                               IEN | PTU | M1 },
-	/* sdmmc4_dat1         */
-	{ UART4_TX            ,                               IEN | PTU | M1 },
-	/* gpio_157            */
-	{ USBB2_ULPITLL_CLK   ,                                           M3 },
-	/* dispc2_data23       */
-	{ USBB2_ULPITLL_STP   ,                                           M5 },
-	/* dispc2_data22       */
-	{ USBB2_ULPITLL_DIR   ,                                           M5 },
-	/* dispc2_data21       */
-	{ USBB2_ULPITLL_NXT   ,                                           M5 },
-	/* dispc2_data20       */
-	{ USBB2_ULPITLL_DAT0  ,                                           M5 },
-	/* dispc2_data19       */
-	{ USBB2_ULPITLL_DAT1  ,                                           M5 },
-	/* dispc2_data18       */
-	{ USBB2_ULPITLL_DAT2  ,                                           M5 },
-	/* dispc2_data15       */
-	{ USBB2_ULPITLL_DAT3  ,                                           M5 },
-	/* dispc2_data14       */
-	{ USBB2_ULPITLL_DAT4  ,                                           M5 },
-	/* dispc2_data13       */
-	{ USBB2_ULPITLL_DAT5  ,                                           M5 },
-	/* dispc2_data12       */
-	{ USBB2_ULPITLL_DAT6  ,                                           M5 },
-	/* dispc2_data11       */
-	{ USBB2_ULPITLL_DAT7  ,                                           M5 },
-	/* gpio_169            */
-	{ USBB2_HSIC_DATA     ,                                           M3 },
-	/* gpio_170            */
-	{ USBB2_HSIC_STROBE   ,                                           M3 },
-	/* kpd_col0            */
-	{ KPD_COL3            ,                               IEN | PTD | M1 },
-	/* kpd_col1            */
-	{ KPD_COL4            ,                               IEN | PTD | M1 },
-	/* kpd_col2            */
-	{ KPD_COL5            ,                               IEN | PTD | M1 },
-	/* gpio_174            */ /* accel_int2 */
-	{ KPD_COL0            ,                               IEN | PTU | M3 },
-	/* gpio_0              */ /* tsp_shtdwn_gpio */
-	{ KPD_COL1            ,                               IEN | PTD | M3 },
-	/* gpio_1              */
-	{ KPD_COL2            ,                               IEN | PTD | M3 },
-	/* kpd_row0            */
-	{ KPD_ROW3            ,                               IEN | PTD | M1 },
-	/* kpd_row1            */
-	{ KPD_ROW4            ,                               IEN | PTD | M1 },
-	/* kpd_row2            */
-	{ KPD_ROW5            ,                               IEN | PTD | M1 },
-	/* kpd_row3            */
-	{ KPD_ROW0            ,                               IEN | PTD | M1 },
-	/* kpd_row4            */
-	{ KPD_ROW1            ,                               IEN | PTD | M1 },
-	/* kpd_row5            */
-	{ KPD_ROW2            ,                               IEN | PTD | M1 },
-	/* usba0_otg_ce        */
-	{ USBA0_OTG_CE        ,                                     PTU | M0 },
-	/* usba0_otg_dp        */
-	{ USBA0_OTG_DP        ,                                           M0 },
-	/* usba0_otg_dm        */
-	{ USBA0_OTG_DM        ,                                           M0 },
-	/* safe_mode           */
-	{ FREF_CLK1_OUT       ,                               IEN | PTD | M7 },
-	/* fref_clk2_out       */
-	{ FREF_CLK2_OUT       ,                                           M0 },
-	/* sys_nirq1           */
-	{ SYS_NIRQ1           , WAKEUP_EN                   | IEN | PTU | M0 },
-	/* sys_nirq2           */ /* audio_irq */
-	{ SYS_NIRQ2           ,                               IEN | PTU | M0 },
-	/* sys_boot0           */
-	{ SYS_BOOT0           ,                               IEN | PTD | M0 },
-	/* sys_boot1           */
-	{ SYS_BOOT1           ,                               IEN | PTD | M0 },
-	/* sys_boot2           */
-	{ SYS_BOOT2           ,                               IEN | PTD | M0 },
-	/* sys_boot3           */
-	{ SYS_BOOT3           ,                               IEN | PTD | M0 },
-	/* sys_boot4           */
-	{ SYS_BOOT4           ,                               IEN | PTD | M0 },
-	/* sys_boot5           */
-	{ SYS_BOOT5           ,                               IEN | PTD | M0 },
-	/* dpm_emu0            */
-	{ DPM_EMU0            ,                               IEN | PTU | M0 },
-	/* gpio_12             */ /* lcd_avdd_en */
-	{ DPM_EMU1            ,                               IEN       | M3 },
-	/* safe_mode           */
-	{ DPM_EMU2            ,                               IEN | PTD | M7 },
-	/* dispc2_data10       */
-	{ DPM_EMU3            ,                                           M5 },
-	/* dispc2_data9        */
-	{ DPM_EMU4            ,                                           M5 },
-	/* dispc2_data16       */
-	{ DPM_EMU5            ,                                           M5 },
-	/* dispc2_data17       */
-	{ DPM_EMU6            ,                                           M5 },
-	/* dispc2_hsync        */
-	{ DPM_EMU7            ,                                           M5 },
-	/* dispc2_pclk         */
-	{ DPM_EMU8            ,                                           M5 },
-	/* dispc2_vsync        */
-	{ DPM_EMU9            ,                                           M5 },
-	/* dispc2_de           */
-	{ DPM_EMU10           ,                                           M5 },
-	/* dispc2_data8        */
-	{ DPM_EMU11           ,                                           M5 },
-	/* dispc2_data7        */
-	{ DPM_EMU12           ,                                           M5 },
-	/* dispc2_data6        */
-	{ DPM_EMU13           ,                                           M5 },
-	/* dispc2_data5        */
-	{ DPM_EMU14           ,                                           M5 },
-	/* dispc2_data4        */
-	{ DPM_EMU15           ,                                           M5 },
-	/* dispc2_data3        */
-	{ DPM_EMU16           ,                                           M5 },
-	/* dispc2_data2        */
-	{ DPM_EMU17           ,                                           M5 },
-	/* dispc2_data1        */
-	{ DPM_EMU18           ,                                           M5 },
-	/* dispc2_data0        */
-	{ DPM_EMU19           ,                                           M5 },
-	/* safe_mode           */
-	{ CSI22_DX2           ,                               IEN | PTD | M7 },
-	/* safe_mode           */
-	{ CSI22_DY2           ,                               IEN | PTD | M7 },
+	{ GPMC_AD0            , IEN | PTU | M1 },
+	{ GPMC_AD1            , IEN | PTU | M1 },
+	{ GPMC_AD2            , IEN | PTU | M1 },
+	{ GPMC_AD3            , IEN | PTU | M1 },
+	{ GPMC_AD4            , IEN | PTU | M1 },
+	{ GPMC_AD5            , IEN | PTU | M1 },
+	{ GPMC_AD6            , IEN | PTU | M1 },
+	{ GPMC_AD7            , IEN | PTU | M1 },
+	{ GPMC_AD8            , IEN | PTD | M3 },
+	{ GPMC_AD9            , IEN | PTU | M0 },
+	{ GPMC_AD10           , IEN | PTU | M0 },
+	{ GPMC_AD11           , IEN | PTU | M0 },
+	{ GPMC_AD12           , IEN | PTD | M0 },
+	{ GPMC_AD13           ,       PTD | M3 },
+	{ GPMC_AD14           ,       PTD | M3 },
+	{ GPMC_AD15           ,       PTD | M3 },
+	{ GPMC_A16            , IEN | PTD | M7 },
+	{ GPMC_A17            , IEN | PTD | M7 },
+	{ GPMC_A18            , IEN | PTD | M1 },
+	{ GPMC_A19            , IEN | PTU | M3 },
+	{ GPMC_A20            , IEN | PTU | M3 },
+	{ GPMC_A21            , IEN | PTD | M7 },
+	{ GPMC_A22            , IEN | PTD | M1 },
+	{ GPMC_A23            , IEN | PTD | M1 },
+	{ GPMC_A24            , IEN | PTD | M3 },
+	{ GPMC_A25            , IEN | PTU | M3 },
+	{ GPMC_NCS0           , IEN | PTU | M0 },
+	{ GPMC_NCS1           , IEN | PTU | M7 },
+	{ GPMC_NCS2           , IEN | PTU | M7 },
+	{ GPMC_NCS3           , IEN | PTU | M7 },
+	{ GPMC_NWP            , IEN | PTD | M0 },
+	{ GPMC_CLK            , IEN | PTD | M0 },
+	{ GPMC_NADV_ALE       , IEN | PTD | M0 },
+	{ GPMC_NOE            , IEN | PTU | M1 },
+	{ GPMC_NWE            , IEN | PTU | M1 },
+	{ GPMC_NBE0_CLE       , IEN | PTD | M0 },
+	{ GPMC_NBE1           , IEN | PTD | M7 },
+	{ GPMC_WAIT0          , IEN | PTU | M0 },
+	{ GPMC_WAIT1          , IEN | PTU | M7 },
+	{ GPMC_WAIT2          , IEN | PTD | M7 },
+	{ GPMC_NCS4           , IEN | PTD | M7 },
+	{ GPMC_NCS5           , IEN | PTD | M7 },
+	{ GPMC_NCS6           , IEN | PTD | M7 },
+	{ GPMC_NCS7           , IEN | PTD | M7 },
+	{ GPIO63              ,             M0 },
+	{ GPIO64              ,             M0 },
+	{ GPIO65              ,             M0 },
+	{ GPIO66              , IEN       | M0 },
+	{ CSI21_DX0           , IEN | PTD | M7 },
+	{ CSI21_DY0           , IEN | PTD | M7 },
+	{ CSI21_DX1           , IEN | PTD | M7 },
+	{ CSI21_DY1           , IEN | PTD | M7 },
+	{ CSI21_DX2           , IEN | PTD | M7 },
+	{ CSI21_DY2           , IEN | PTD | M7 },
+	{ CSI21_DX3           , IEN | PTD | M7 },
+	{ CSI21_DY3           , IEN | PTD | M7 },
+	{ CSI21_DX4           , IEN | PTD | M7 },
+	{ CSI21_DY4           , IEN | PTD | M7 },
+	{ CSI22_DX0           , IEN | PTD | M7 },
+	{ CSI22_DY0           , IEN | PTD | M7 },
+	{ CSI22_DX1           , IEN | PTD | M7 },
+	{ CSI22_DY1           , IEN | PTD | M7 },
+	{ CAM_SHUTTER         ,       PTD | M0 },
+	{ CAM_STROBE          ,       PTD | M0 },
+	{ CAM_GLOBALRESET     ,       PTD | M3 },
+	{ USBB1_ULPITLL_CLK   , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_STP   ,       PTU | M0 },
+	{ USBB1_ULPITLL_DIR   , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_NXT   , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_DAT0  , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_DAT1  , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_DAT2  , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_DAT3  , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_DAT4  , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_DAT5  , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_DAT6  , IEN | PTD | M0 },
+	{ USBB1_ULPITLL_DAT7  , IEN | PTD | M0 },
+	{ USBB1_HSIC_DATA     ,             M0 },
+	{ USBB1_HSIC_STROBE   ,             M0 },
+	{ USBC1_ICUSB_DP      ,             M0 },
+	{ USBC1_ICUSB_DM      ,             M0 },
+	{ SDMMC1_CLK          ,       PTU | M0 },
+	{ SDMMC1_CMD          , IEN | PTU | M0 },
+	{ SDMMC1_DAT0         , IEN | PTU | M0 },
+	{ SDMMC1_DAT1         , IEN | PTU | M0 },
+	{ SDMMC1_DAT2         , IEN | PTU | M0 },
+	{ SDMMC1_DAT3         , IEN | PTU | M0 },
+	{ SDMMC1_DAT4         , IEN | PTU | M0 },
+	{ SDMMC1_DAT5         , IEN | PTU | M0 },
+	{ SDMMC1_DAT6         , IEN | PTU | M0 },
+	{ SDMMC1_DAT7         , IEN | PTU | M0 },
+	{ ABE_MCBSP2_CLKX     , IEN       | M0 },
+	{ ABE_MCBSP2_DR       , IEN       | M0 },
+	{ ABE_MCBSP2_DX       ,             M0 },
+	{ ABE_MCBSP2_FSX      , IEN       | M0 },
+	{ ABE_MCBSP1_CLKX     , IEN | PTD | M7 },
+	{ ABE_MCBSP1_DR       , IEN | PTD | M7 },
+	{ ABE_MCBSP1_DX       ,             M0 },
+	{ ABE_MCBSP1_FSX      , IEN       | M0 },
+	{ ABE_PDM_UL_DATA     , IEN | PTD | M7 },
+	{ ABE_PDM_DL_DATA     , IEN | PTD | M7 },
+	{ ABE_PDM_FRAME       , IEN | PTD | M7 },
+	{ ABE_PDM_LB_CLK      , IEN | PTD | M7 },
+	{ ABE_CLKS            , IEN | PTD | M7 },
+	{ ABE_DMIC_CLK1       , IEN | PTD | M7 },
+	{ ABE_DMIC_DIN1       , IEN | PTD | M7 },
+	{ ABE_DMIC_DIN2       , IEN | PTD | M7 },
+	{ ABE_DMIC_DIN3       , IEN | PTD | M7 },
+	{ UART2_CTS           , IEN | PTU | M0 },
+	{ UART2_RTS           ,             M0 },
+	{ UART2_RX            , IEN       | M0 },
+	{ UART2_TX            ,             M0 },
+	{ HDQ_SIO             , IEN       | M7 },
+	{ I2C1_SCL            , IEN       | M0 },
+	{ I2C1_SDA            , IEN       | M0 },
+	{ I2C2_SCL            , IEN       | M0 },
+	{ I2C2_SDA            , IEN       | M0 },
+	{ I2C3_SCL            , IEN       | M0 },
+	{ I2C3_SDA            , IEN       | M0 },
+	{ I2C4_SCL            , IEN       | M0 },
+	{ I2C4_SDA            , IEN       | M0 },
+	{ MCSPI1_CLK          , IEN       | M0 },
+	{ MCSPI1_SOMI         , IEN       | M0 },
+	{ MCSPI1_SIMO         , IEN       | M0 },
+	{ MCSPI1_CS0          , IEN | PTD | M0 },
+	{ MCSPI1_CS1          , IEN | PTU | M1 },
+	{ MCSPI1_CS2          ,             M3 },
+	{ MCSPI1_CS3          , IEN | PTU | M7 },
+	{ UART3_CTS_RCTX      ,             M1 },
+	{ UART3_RTS_SD        ,             M0 },
+	{ UART3_RX_IRRX       , IEN | PTU | M0 },
+	{ UART3_TX_IRTX       ,             M0 },
+	{ SDMMC5_CLK          ,       PTU | M0 },
+	{ SDMMC5_CMD          , IEN | PTU | M0 },
+	{ SDMMC5_DAT0         , IEN | PTU | M0 },
+	{ SDMMC5_DAT1         , IEN | PTU | M0 },
+	{ SDMMC5_DAT2         , IEN | PTU | M0 },
+	{ SDMMC5_DAT3         , IEN | PTU | M0 },
+	{ MCSPI4_CLK          , IEN       | M0 },
+	{ MCSPI4_SIMO         , IEN       | M0 },
+	{ MCSPI4_SOMI         , IEN       | M0 },
+	{ MCSPI4_CS0          , IEN | PTD | M0 },
+	{ UART4_RX            , IEN       | M0 },
+	{ UART4_TX            ,             M0 },
+	{ USBB2_ULPITLL_CLK   ,             M3 },
+	{ USBB2_ULPITLL_STP   ,             M5 },
+	{ USBB2_ULPITLL_DIR   ,             M5 },
+	{ USBB2_ULPITLL_NXT   ,             M5 },
+	{ USBB2_ULPITLL_DAT0  ,             M5 },
+	{ USBB2_ULPITLL_DAT1  ,             M5 },
+	{ USBB2_ULPITLL_DAT2  ,             M5 },
+	{ USBB2_ULPITLL_DAT3  ,             M5 },
+	{ USBB2_ULPITLL_DAT4  ,             M5 },
+	{ USBB2_ULPITLL_DAT5  ,             M5 },
+	{ USBB2_ULPITLL_DAT6  ,             M5 },
+	{ USBB2_ULPITLL_DAT7  ,             M5 },
+	{ USBB2_HSIC_DATA     ,             M3 },
+	{ USBB2_HSIC_STROBE   ,             M3 },
+	{ KPD_COL3            , IEN | PTD | M1 },
+	{ KPD_COL4            , IEN | PTD | M1 },
+	{ KPD_COL5            , IEN | PTD | M1 },
+	{ KPD_COL0            , IEN | PTD | M1 },
+	{ KPD_COL1            , IEN | PTD | M3 },
+	{ KPD_COL2            , IEN | PTD | M3 },
+	{ KPD_ROW3            , IEN | PTD | M1 },
+	{ KPD_ROW4            , IEN | PTD | M1 },
+	{ KPD_ROW5            , IEN | PTD | M1 },
+	{ KPD_ROW0            , IEN | PTD | M1 },
+	{ KPD_ROW1            , IEN | PTD | M1 },
+	{ KPD_ROW2            , IEN | PTD | M1 },
+	{ USBA0_OTG_CE        ,       PTU | M0 },
+	{ USBA0_OTG_DP        ,             M0 },
+	{ USBA0_OTG_DM        ,             M0 },
+	{ FREF_CLK1_OUT       , IEN | PTD | M7 },
+	{ FREF_CLK2_OUT       , IEN | PTD | M7 },
+	{ SYS_NIRQ1           , IEN | PTU | M0 },
+	{ SYS_NIRQ2           , IEN | PTU | M0 },
+	{ SYS_BOOT0           , IEN | PTD | M0 },
+	{ SYS_BOOT1           , IEN | PTD | M0 },
+	{ SYS_BOOT2           , IEN | PTD | M0 },
+	{ SYS_BOOT3           , IEN | PTD | M0 },
+	{ SYS_BOOT4           , IEN | PTD | M0 },
+	{ SYS_BOOT5           , IEN | PTD | M0 },
+	{ DPM_EMU0            , IEN | PTU | M0 },
+	{ DPM_EMU1            , IEN | PTU | M0 },
+	{ DPM_EMU2            , IEN | PTD | M7 },
+	{ DPM_EMU3            ,             M5 },
+	{ DPM_EMU4            ,             M5 },
+	{ DPM_EMU5            ,             M5 },
+	{ DPM_EMU6            ,             M5 },
+	{ DPM_EMU7            ,             M5 },
+	{ DPM_EMU8            ,             M5 },
+	{ DPM_EMU9            ,             M5 },
+	{ DPM_EMU10           ,             M5 },
+	{ DPM_EMU11           ,             M5 },
+	{ DPM_EMU12           ,             M5 },
+	{ DPM_EMU13           ,             M5 },
+	{ DPM_EMU14           ,             M5 },
+	{ DPM_EMU15           ,             M5 },
+	{ DPM_EMU16           ,             M5 },
+	{ DPM_EMU17           ,             M5 },
+	{ DPM_EMU18           ,             M5 },
+	{ DPM_EMU19           ,             M5 },
+	{ CSI22_DX2           , IEN | PTD | M7 },
+	{ CSI22_DY2           , IEN | PTD | M7 },
 };
 
 static const struct pad_conf_entry wkup_padconf_array[] = {
-	/* sr_scl              */
-	{ SR_SCL               , IEN            },
-	/* sr_sda              */
-	{ SR_SDA               , IEN            },
-	/* fref_clk0_out       */
-	{ FREF_CLK0_OUT        ,             M0 },
-	/* gpio_wk30           */
-	{ FREF_CLK3_REQ        ,             M3 },
-	/* gpio_wk7            */ /* tps62361_vsel0 */
-	{ FREF_CLK4_REQ        , IEN | PTU | M3 },
+	{ GPIO_WK0            , IEN | PTD | M7 },
+	{ GPIO_WK1            , IEN | PTD | M7 },
+	{ GPIO_WK2            , IEN | PTD | M7 },
+	{ GPIO_WK3            , IEN | PTU | M7 },
+	{ GPIO_WK4            , IEN | PTD | M7 },
+	{ SR_SCL              , IEN       | M0 },
+	{ SR_SDA              , IEN       | M0 },
+	{ FREF_XTAL_IN        ,             M0 },
+	{ FREF_SLICER_IN      ,             M0 },
+	{ FREF_CLK_IOREQ      , IEN | PTD | M0 },
+	{ FREF_CLK0_OUT       , IEN | PTD | M7 },
+	{ FREF_CLK3_REQ       , IEN | PTD | M7 },
+	{ FREF_CLK3_OUT       , IEN | PTD | M7 },
+	{ FREF_CLK4_REQ       , IEN | PTU | M3 },
+	{ FREF_CLK4_OUT       , IEN | PTD | M0 },
+	{ SYS_32K             , IEN       | M0 },
+	{ SYS_NRESPWRON       ,             M0 },
+	{ SYS_NRESWARM        ,             M0 },
+	{ SYS_PWR_REQ         , IEN | PTU | M0 },
+	{ SYS_PWRON_RESET_OUT , IEN | PTD | M0 },
+	{ SYS_BOOT6           , IEN       | M0 },
+	{ SYS_BOOT7           , IEN       | M0 },
+	{ JTAG_NTRST          , IEN | PTD | M0 },
+	{ JTAG_TCK            , IEN | PTD | M0 },
+	{ JTAG_RTCK           ,       PTD | M0 },
+	{ JTAG_TMS_TMSC       , IEN       | M0 },
+	{ JTAG_TDI            , IEN | PTU | M0 },
+	{ JTAG_TDO            , IEN | PTU | M0 },
 };
 
 void set_muxconf_regs(void){
@@ -452,7 +265,6 @@ void set_muxconf_regs(void){
 
 	/* gpio_wk7 is used for controlling TPS on 4460 */
 	if (omap4_revision() >= OMAP4460_ES1_0) {
-		writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + FREF_CLK4_REQ);
 		/* Enable GPIO-1 clocks before TPS initialization */
 		omap4_enable_gpio1_wup_clocks();
 	}

From 53f1d60627c8dfae835c2a7e3a9b7af132da3e64 Mon Sep 17 00:00:00 2001
From: Vicente Bergas <vicencb@gmail.com>
Date: Sat, 19 Jan 2013 18:23:27 +0100
Subject: [PATCH 08/16] feature_list: a way to pass hardware info to the kernel

Hi Sascha,
I've made the changes you suggested in this resent patch.

Everything related to custom ATAGs has been moved to the board
directory.

The generic code does not make any references to feature lists or
bootloader versions.

About the setup_feature_list prototype:
 it has been renamed to atag_appender
 it's not a function, it's a pointer to a function. Can it have a
prototype other than it's own declaration?

All non-related changes has been dropped. They were checkpatch.pl
warnings unrelated to this patch.

Regards,
  Vicente.

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/Kconfig                           |   7 +
 arch/arm/boards/archosg9/Makefile          |   1 +
 arch/arm/boards/archosg9/archos_features.c | 225 +++++++++++++
 arch/arm/boards/archosg9/archos_features.h |  22 ++
 arch/arm/boards/archosg9/board.c           |   2 +
 arch/arm/boards/archosg9/feature_list.h    | 352 +++++++++++++++++++++
 arch/arm/configs/archosg9_defconfig        |   1 +
 arch/arm/include/asm/armlinux.h            |   9 +
 arch/arm/lib/armlinux.c                    |  12 +
 9 files changed, 631 insertions(+)
 create mode 100644 arch/arm/boards/archosg9/archos_features.c
 create mode 100644 arch/arm/boards/archosg9/archos_features.h
 create mode 100644 arch/arm/boards/archosg9/feature_list.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f567531d1..6f7a71f2c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -152,6 +152,13 @@ config THUMB2_BAREBOX
 	  your board lowlevel init code may break in thumb-2 mode. You have been
 	  warned.
 
+config ARM_BOARD_APPEND_ATAG
+	bool "Let board specific code to add ATAGs to be passed to the kernel"
+	depends on ARM_LINUX
+	help
+	  This option is purely to start some vendor provided kernels.
+	  ** DO NOT USE FOR YOUR OWN DESIGNS! **
+
 endmenu
 
 menu "Arm specific settings"
diff --git a/arch/arm/boards/archosg9/Makefile b/arch/arm/boards/archosg9/Makefile
index 256eaf616..450c03f2a 100644
--- a/arch/arm/boards/archosg9/Makefile
+++ b/arch/arm/boards/archosg9/Makefile
@@ -1,3 +1,4 @@
 obj-y += board.o
+obj-$(CONFIG_ARM_BOARD_APPEND_ATAG) += archos_features.o
 obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel.o mux.o
 pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel.o mux.o
diff --git a/arch/arm/boards/archosg9/archos_features.c b/arch/arm/boards/archosg9/archos_features.c
new file mode 100644
index 000000000..5d934038f
--- /dev/null
+++ b/arch/arm/boards/archosg9/archos_features.c
@@ -0,0 +1,225 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot.h>
+#include <asm/setup.h>
+#include "archos_features.h"
+#include "feature_list.h"
+
+static inline void *atag_data(struct tag *t)
+{
+	return ((void *)t) + sizeof(struct tag_header);
+}
+
+static struct feature_tag *features;
+
+static void setup_feature_core(void)
+{
+	features->hdr.tag = FTAG_CORE;
+	features->hdr.size = feature_tag_size(feature_tag_core);
+
+	features->u.core.magic = FEATURE_LIST_MAGIC;
+	features->u.core.list_revision = FEATURE_LIST_REV;
+	features->u.core.flags = 0;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_product_name(void)
+{
+	features->hdr.tag = FTAG_PRODUCT_NAME;
+	features->hdr.size = feature_tag_size(feature_tag_product_name);
+
+	memset(features->u.product_name.name, 0,
+		sizeof(features->u.product_name.name));
+	sprintf(features->u.product_name.name, "A80S");
+	features->u.product_name.id = 0x13A8;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_product_serial_number(void)
+{
+	features->hdr.tag = FTAG_PRODUCT_SERIAL_NUMBER;
+	features->hdr.size = feature_tag_size(feature_tag_product_serial);
+
+	features->u.product_serial.serial[0] = 0;
+	features->u.product_serial.serial[1] = 0;
+	features->u.product_serial.serial[2] = 0;
+	features->u.product_serial.serial[3] = 0;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_product_mac_address(void)
+{
+	features->hdr.tag = FTAG_PRODUCT_MAC_ADDRESS;
+	features->hdr.size = feature_tag_size(feature_tag_product_mac_address);
+
+	features->u.mac_address.addr[0] = 0;
+	features->u.mac_address.addr[1] = 0;
+	features->u.mac_address.addr[2] = 0;
+	features->u.mac_address.addr[3] = 0;
+	features->u.mac_address.addr[4] = 0;
+	features->u.mac_address.addr[5] = 0;
+	features->u.mac_address.reserved1 = 0;
+	features->u.mac_address.reserved2 = 0;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_board_pcb_revision(void)
+{
+	features->hdr.tag = FTAG_BOARD_PCB_REVISION;
+	features->hdr.size = feature_tag_size(feature_tag_board_revision);
+
+	features->u.board_revision.revision = 5;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_sdram(void)
+{
+	features->hdr.tag = FTAG_SDRAM;
+	features->hdr.size = feature_tag_size(feature_tag_sdram);
+
+	memset(features->u.sdram.vendor, 0, sizeof(features->u.sdram.vendor));
+	memset(features->u.sdram.product, 0,
+		sizeof(features->u.sdram.product));
+	sprintf(features->u.sdram.vendor , "elpida");
+	sprintf(features->u.sdram.product, "EDB8064B1PB"/*"EDB4064B2PB"*/);
+	features->u.sdram.type     = 0;
+	features->u.sdram.revision = 0;
+	features->u.sdram.flags    = 0;
+	features->u.sdram.clock    = 400;
+	features->u.sdram.param_0  = 0;
+	features->u.sdram.param_1  = 0;
+	features->u.sdram.param_2  = 0;
+	features->u.sdram.param_3  = 0;
+	features->u.sdram.param_4  = 0;
+	features->u.sdram.param_5  = 0;
+	features->u.sdram.param_6  = 0;
+	features->u.sdram.param_7  = 0;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_pmic(void)
+{
+	features->hdr.tag = FTAG_PMIC;
+	features->hdr.size = feature_tag_size(feature_tag_pmic);
+
+	features->u.pmic.flags = FTAG_PMIC_TPS62361;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_serial_port(void)
+{
+	features->hdr.tag = FTAG_SERIAL_PORT;
+	features->hdr.size = feature_tag_size(feature_tag_serial_port);
+
+	features->u.serial_port.uart_id = 1;
+	features->u.serial_port.speed = 115200;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_has_gpio_volume_keys(void)
+{
+	features->hdr.tag = FTAG_HAS_GPIO_VOLUME_KEYS;
+	features->hdr.size = feature_tag_size(feature_tag_gpio_volume_keys);
+
+	features->u.gpio_volume_keys.gpio_vol_up   = 0x2B;
+	features->u.gpio_volume_keys.gpio_vol_down = 0x2C;
+	features->u.gpio_volume_keys.flags = 0;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_screen(void)
+{
+	features->hdr.tag = FTAG_SCREEN;
+	features->hdr.size = feature_tag_size(feature_tag_screen);
+
+	memset(features->u.screen.vendor, 0,
+		sizeof(features->u.screen.vendor));
+	sprintf(features->u.screen.vendor, "CMI");
+	features->u.screen.type = 0;
+	features->u.screen.revision = 0;
+	features->u.screen.vcom = 0;
+	features->u.screen.backlight = 0xC8;
+	features->u.screen.reserved[0] = 0;
+	features->u.screen.reserved[1] = 0;
+	features->u.screen.reserved[2] = 0;
+	features->u.screen.reserved[3] = 0;
+	features->u.screen.reserved[4] = 0;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_turbo(void)
+{
+	features->hdr.tag = FTAG_TURBO;
+	features->hdr.size = feature_tag_size(feature_tag_turbo);
+
+	features->u.turbo.flag = 1;
+
+	features = feature_tag_next(features);
+}
+static void setup_feature_none(void)
+{
+	features->hdr.tag = FTAG_NONE;
+	features->hdr.size = sizeof(struct feature_tag_header) >> 2;
+
+	features = feature_tag_next(features);
+}
+static struct tag *setup_feature_list(struct tag * params)
+{
+	struct tag_feature_list *fl;
+
+	fl = atag_data(params);
+	features = (struct feature_tag *)fl->data;
+
+	setup_feature_core();
+	setup_feature_product_name();
+	setup_feature_product_serial_number();
+	setup_feature_product_mac_address();
+	setup_feature_board_pcb_revision();
+	setup_feature_sdram();
+	setup_feature_pmic();
+	setup_feature_serial_port();
+	setup_feature_has_gpio_volume_keys();
+	setup_feature_screen();
+	setup_feature_turbo();
+	setup_feature_none();
+
+	fl->size = ((u32)features) - ((u32)(fl->data));
+
+	params->hdr.tag = ATAG_FEATURE_LIST;
+	params->hdr.size = (sizeof(struct tag_feature_list) + fl->size) >> 2;
+
+	return tag_next(params);
+}
+
+static struct tag *setup_boot_version(struct tag *params)
+{
+	struct tag_boot_version *bv;
+
+	bv = atag_data(params);
+
+	params->hdr.tag = ATAG_BOOT_VERSION;
+	params->hdr.size = tag_size(tag_boot_version);
+
+	bv->major = 5;
+	bv->minor = 5;
+	bv->extra = 3;
+
+	return tag_next(params);
+}
+
+struct tag *archos_append_atags(struct tag *params)
+{
+	params = setup_feature_list(params);
+	params = setup_boot_version(params);
+	return params;
+}
diff --git a/arch/arm/boards/archosg9/archos_features.h b/arch/arm/boards/archosg9/archos_features.h
new file mode 100644
index 000000000..5769c6c66
--- /dev/null
+++ b/arch/arm/boards/archosg9/archos_features.h
@@ -0,0 +1,22 @@
+#ifndef __ARCHOS_FEATURES_H
+#define __ARCHOS_FEATURES_H
+
+/* bootloader version */
+#define ATAG_BOOT_VERSION	0x5441000A
+
+struct tag_boot_version {
+	u32		major;
+	u32		minor;
+	u32		extra;
+};
+
+#define ATAG_FEATURE_LIST	0x5441000B
+
+struct tag_feature_list {
+	u32	size;
+	u8	data[0];
+};
+
+struct tag *archos_append_atags(struct tag * params);
+
+#endif /* __ARCHOS_FEATURES_H */
diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c
index 200fe9295..8366ccafe 100644
--- a/arch/arm/boards/archosg9/board.c
+++ b/arch/arm/boards/archosg9/board.c
@@ -20,6 +20,7 @@
 #include <sizes.h>
 #include <i2c/i2c.h>
 #include <gpio.h>
+#include "archos_features.h"
 
 static int archosg9_console_init(void){
 	if (IS_ENABLED(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT))
@@ -59,6 +60,7 @@ static int archosg9_devices_init(void){
 	 */
 	armlinux_set_architecture(5032);
 	armlinux_set_revision(5);
+	armlinux_set_atag_appender(archos_append_atags);
 
 	return 0;
 }
diff --git a/arch/arm/boards/archosg9/feature_list.h b/arch/arm/boards/archosg9/feature_list.h
new file mode 100644
index 000000000..0b726cd1a
--- /dev/null
+++ b/arch/arm/boards/archosg9/feature_list.h
@@ -0,0 +1,352 @@
+#ifndef _FEATURE_LIST_H
+#define _FEATURE_LIST_H
+
+/*
+ This file comes from:
+ http://gitorious.org/archos/archos-gpl-gen9-kernel-ics/blobs/raw/master/
+ arch/arm/include/asm/feature_list.h
+*/
+
+#define FEATURE_LIST_MAGIC		0xFEA01234
+
+#define FEATURE_LIST_REV		0x00000001
+
+struct feature_tag_header {
+	u32 size;
+	u32 tag;
+};
+
+struct feature_tag_generic {
+	u32 vendor;
+	u32 product;
+	u32 type;
+	u32 revision;
+	u32 flags;
+};
+
+#define FTAG_NONE			0x00000000
+
+#define FTAG_CORE			0x00000001
+struct feature_tag_core {
+	u32 magic;
+	u32 list_revision;
+	u32 flags;
+};
+
+/* product specific */
+#define FTAG_PRODUCT_NAME		0x00000002
+struct feature_tag_product_name {
+	char name[64];
+	u32 id;
+};
+#define FTAG_PRODUCT_SERIAL_NUMBER	0x00000003
+struct feature_tag_product_serial {
+	u32 serial[4];
+};
+
+#define FTAG_PRODUCT_MAC_ADDRESS	0x00000004
+struct feature_tag_product_mac_address {
+	u8 addr[6];
+	u8 reserved1;
+	u8 reserved2;
+};
+
+#define FTAG_PRODUCT_OEM		0x00000005
+struct feature_tag_product_oem {
+	char name[16];
+	u32 id;
+};
+
+#define FTAG_PRODUCT_ZONE		0x00000006
+struct feature_tag_product_zone {
+	char name[16];
+	u32 id;
+};
+
+/* board pcb specific */
+#define FTAG_BOARD_PCB_REVISION		0x00000010
+struct feature_tag_board_revision {
+	u32 revision;
+};
+
+/* clock and ram setup */
+#define FTAG_CLOCK			0x00000011
+struct feature_tag_clock {
+	u32 clock;
+};
+
+#define FTAG_SDRAM			0x00000012
+struct feature_tag_sdram {
+	char vendor[16];
+	char product[32];
+	u32 type;
+	u32 revision;
+	u32 flags;
+	u32 clock;
+	/* custom params */
+	u32 param_0;
+	u32 param_1;
+	u32 param_2;
+	u32 param_3;
+	u32 param_4;
+	u32 param_5;
+	u32 param_6;
+	u32 param_7;
+};
+
+/* PMIC */
+#define FTAG_PMIC			0x00000013
+#define FTAG_PMIC_TPS62361		0x00000001
+struct feature_tag_pmic {
+	u32 flags;
+};
+
+/* serial port */
+#define FTAG_SERIAL_PORT		0x00000020
+struct feature_tag_serial_port {
+	u32 uart_id;
+	u32 speed;
+};
+
+/* turbo bit */
+#define FTAG_TURBO			0x00000014
+struct feature_tag_turbo {
+	u32 flag;
+};
+
+/*** features ****/
+#define FTAG_HAS_GPIO_VOLUME_KEYS	0x00010001
+struct feature_tag_gpio_volume_keys {
+	u32 gpio_vol_up;
+	u32 gpio_vol_down;
+	u32 flags;
+};
+
+#define FTAG_HAS_ELECTRICAL_SHORTCUT	0x00010002
+#define FTAG_HAS_DCIN			0x00010003
+struct feature_tag_dcin {
+	u32 autodetect;
+};
+
+/* external screen support */
+#define FTAG_HAS_EXT_SCREEN		0x00010004
+
+#define EXT_SCREEN_TYPE_TVOUT	0x00000001
+#define EXT_SCREEN_TYPE_HDMI	0x00000002
+#define EXT_SCREEN_TYPE_VGA	0x00000004
+struct feature_tag_ext_screen {
+	u32 type;
+	u32 revision;
+};
+
+/* wireless lan */
+#define FTAG_HAS_WIFI			0x00010005
+
+#define WIFI_TYPE_TIWLAN	0x00000001
+struct feature_tag_wifi {
+	u32 vendor;
+	u32 product;
+	u32 type;
+	u32 revision;
+	u32 flags;
+};
+
+/* bluetooth */
+#define FTAG_HAS_BLUETOOTH		0x00010006
+
+#define BLUETOOTH_TYPE_TIWLAN	0x00000001
+struct feature_tag_bluetooth {
+	u32 vendor;
+	u32 product;
+	u32 type;
+	u32 revision;
+	u32 flags;
+};
+
+/* accelerometer */
+#define FTAG_HAS_ACCELEROMETER		0x00010007
+struct feature_tag_accelerometer {
+	u32 vendor;
+	u32 product;
+	u32 type;
+	u32 revision;
+	u32 flags;
+};
+
+/* gyroscope */
+#define FTAG_HAS_GYROSCOPE		0x00010008
+
+/* compass */
+#define FTAG_HAS_COMPASS		0x00010009
+
+/* gps */
+#define FTAG_HAS_GPS			0x0001000a
+#define GPS_FLAG_DISABLED		0x00000001
+struct feature_tag_gps {
+	u32 vendor;
+	u32 product;
+	u32 revision;
+	u32 flags;
+};
+
+/* camera */
+#define FTAG_HAS_CAMERA			0x0001000b
+
+/* harddisk controller */
+#define FTAG_HAS_HARDDISK_CONTROLLER	0x0001000c
+#define HDCONTROLLER_TYPE_SATA	0x00000001
+struct feature_tag_harddisk_controller {
+	u32 vendor;
+	u32 product;
+	u32 type;
+	u32 revision;
+	u32 flags;
+};
+
+/* harddisk */
+#define FTAG_HAS_HARDDISK		0x0001000d
+
+#define HARDDISK_TYPE_SATA	0x00000001
+#define HARDDISK_TYPE_PATA	0x00000002
+struct feature_tag_harddisk {
+	u32 vendor;
+	u32 product;
+	u32 type;
+	u32 revision;
+	u32 flags;
+};
+
+/* touchscreen */
+#define FTAG_HAS_TOUCHSCREEN		0x0001000e
+
+#define TOUCHSCREEN_TYPE_CAPACITIVE 0x00000001
+#define TOUCHSCREEN_TYPE_RESISTIVE  0x00000002
+
+#define TOUCHSCREEN_FLAG_MULTITOUCH 0x00000001
+struct feature_tag_touchscreen {
+	u32 vendor;
+	u32 product;
+	u32 type;
+	u32 revision;
+	u32 flags;
+};
+
+/* microphone */
+#define FTAG_HAS_MICROPHONE		0x0001000f
+
+/* external SDMMC slot */
+#define FTAG_HAS_EXT_MMCSD_SLOT		0x00010010
+#define MMCSD_FLAG_CARDDETECT    0x00000001
+#define MMCSD_FLAG_CARDPREDETECT 0x00000002
+
+struct feature_tag_mmcsd {
+	u32 width;
+	u32 voltagemask;
+	u32 revision;
+	u32 flags;
+};
+
+/* ambient light sensor */
+#define FTAG_HAS_AMBIENT_LIGHT_SENSOR	0x00010011
+
+/* proximity sensor */
+#define FTAG_HAS_PROXIMITY_SENSOR	0x00010012
+
+/* gps */
+#define FTAG_HAS_GSM			0x00010013
+
+/* dect */
+#define FTAG_HAS_DECT			0x00010014
+
+/* hsdpa data modem */
+#define FTAG_HAS_HSDPA			0x00010015
+
+/* near field communication */
+#define FTAG_HAS_NFC			0x00010016
+
+#define FTAG_GPIO_KEYS			0x00010017
+struct feature_tag_gpio_keys {
+#define GPIO_KEYS_LONG_PRESS		0x00010000
+	u32 vol_up;
+	u32 vol_down;
+	u32 ok;
+	u32 reserved[5];
+};
+
+#define FTAG_SCREEN			0x00010018
+struct feature_tag_screen {
+	char vendor[16];
+	u32 type;
+	u32 revision;
+	u32 vcom;
+	u32 backlight;
+	u32 reserved[5];
+};
+
+#define FTAG_WIFI_PA			0x00010019
+struct feature_tag_wifi_pa {
+	char vendor[16];
+	u32 type;
+};
+
+/* loudspeaker */
+#define FTAG_HAS_SPEAKER		0x0001001a
+
+#define SPEAKER_FLAG_STEREO	 0x00000001
+#define SPEAKER_FLAG_OWN_VOLCTRL 0x00000002
+struct feature_tag_speaker {
+	u32 flags;
+};
+
+#define FTAG_BATTERY			0x0001001b
+struct feature_tag_battery {
+	u32 type;
+};
+#define BATTERY_TYPE_HIGHRS	 0x00000000
+#define BATTERY_TYPE_LOWRS	 0x00000001
+
+
+#define feature_tag_next(t) \
+	((struct feature_tag *)((u32 *)(t) + (t)->hdr.size))
+#define feature_tag_size(type) \
+	((sizeof(struct feature_tag_header) + sizeof(struct type)) >> 2)
+#define for_each_feature_tag(t, base) \
+	for (t = base; t->hdr.size; t = feature_tag_next(t))
+
+
+struct feature_tag {
+	struct feature_tag_header hdr;
+	union {
+		struct feature_tag_core			core;
+		struct feature_tag_generic		generic;
+		struct feature_tag_product_name		product_name;
+		struct feature_tag_product_serial	product_serial;
+		struct feature_tag_product_oem		product_oem;
+		struct feature_tag_product_zone		product_zone;
+		struct feature_tag_product_mac_address	mac_address;
+		struct feature_tag_board_revision	board_revision;
+		struct feature_tag_clock		clock;
+		struct feature_tag_sdram		sdram;
+		struct feature_tag_pmic			pmic;
+		struct feature_tag_turbo		turbo;
+		struct feature_tag_serial_port		serial_port;
+		struct feature_tag_gpio_volume_keys	gpio_volume_keys;
+		struct feature_tag_dcin			dcin;
+		struct feature_tag_ext_screen		ext_screen;
+		struct feature_tag_wifi			wifi;
+		struct feature_tag_bluetooth		bluetooth;
+		struct feature_tag_accelerometer	accelerometer;
+		struct feature_tag_harddisk_controller	harddisk_controller;
+		struct feature_tag_harddisk		harddisk;
+		struct feature_tag_touchscreen		touchscreen;
+		struct feature_tag_gps			gps;
+		struct feature_tag_speaker		speaker;
+		struct feature_tag_mmcsd		mmcsd;
+		struct feature_tag_gpio_keys		gpio_keys;
+		struct feature_tag_screen		screen;
+		struct feature_tag_wifi_pa		wifi_pa;
+		struct feature_tag_battery		battery;
+	} u;
+};
+
+#endif /* _FEATURE_LIST_H */
diff --git a/arch/arm/configs/archosg9_defconfig b/arch/arm/configs/archosg9_defconfig
index 2a20dd77b..1f3d105aa 100644
--- a/arch/arm/configs/archosg9_defconfig
+++ b/arch/arm/configs/archosg9_defconfig
@@ -11,6 +11,7 @@ CONFIG_TEXT_BASE=0xa0000000
 CONFIG_MALLOC_BASE=0x90000000
 CONFIG_MALLOC_SIZE=0x10000000
 CONFIG_KALLSYMS=y
+CONFIG_ARM_BOARD_APPEND_ATAG=y
 CONFIG_PROMPT="barebox> "
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
diff --git a/arch/arm/include/asm/armlinux.h b/arch/arm/include/asm/armlinux.h
index 8ec8c4df7..07479fb15 100644
--- a/arch/arm/include/asm/armlinux.h
+++ b/arch/arm/include/asm/armlinux.h
@@ -2,6 +2,7 @@
 #define __ARCH_ARMLINUX_H
 
 #include <asm/memory.h>
+#include <asm/setup.h>
 
 #if defined CONFIG_ARM_LINUX
 void armlinux_set_bootparams(void *params);
@@ -26,6 +27,14 @@ static inline void armlinux_set_serial(u64 serial)
 }
 #endif
 
+#if defined CONFIG_ARM_BOARD_APPEND_ATAG
+void armlinux_set_atag_appender(struct tag *(*)(struct tag *));
+#else
+static inline void armlinux_set_atag_appender(struct tag *(*func)(struct tag *))
+{
+}
+#endif
+
 struct image_data;
 
 void start_linux(void *adr, int swap, unsigned long initrd_address,
diff --git a/arch/arm/lib/armlinux.c b/arch/arm/lib/armlinux.c
index 9c134ed4b..40a63ea7e 100644
--- a/arch/arm/lib/armlinux.c
+++ b/arch/arm/lib/armlinux.c
@@ -106,6 +106,14 @@ u64 armlinux_get_serial(void)
 #endif
 }
 
+#ifdef CONFIG_ARM_BOARD_APPEND_ATAG
+static struct tag *(*atag_appender)(struct tag *);
+void armlinux_set_atag_appender(struct tag *(*func)(struct tag *))
+{
+	atag_appender = func;
+}
+#endif
+
 static void setup_start_tag(void)
 {
 	params = (struct tag *)armlinux_bootparams;
@@ -233,6 +241,10 @@ static void setup_tags(unsigned long initrd_address,
 
 	setup_revision_tag();
 	setup_serial_tag();
+#ifdef CONFIG_ARM_BOARD_APPEND_ATAG
+	if (atag_appender != NULL)
+		params = atag_appender(params);
+#endif
 	setup_end_tag();
 
 	printf("commandline: %s\n"

From 4b789b49e05fdfa3b9731c6f621a552f20b1f411 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue, 29 Jan 2013 08:36:14 +0100
Subject: [PATCH 09/16] ARM omap3 beagle: move lowlevel code to lowlevel.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/beagle/Makefile   |   2 +
 arch/arm/boards/beagle/board.c    | 169 ------------------------------
 arch/arm/boards/beagle/lowlevel.c | 167 +++++++++++++++++++++++++++++
 3 files changed, 169 insertions(+), 169 deletions(-)
 create mode 100644 arch/arm/boards/beagle/lowlevel.c

diff --git a/arch/arm/boards/beagle/Makefile b/arch/arm/boards/beagle/Makefile
index dcfc2937d..88c223aa6 100644
--- a/arch/arm/boards/beagle/Makefile
+++ b/arch/arm/boards/beagle/Makefile
@@ -1 +1,3 @@
 obj-y += board.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c
index 88096bb9c..bed465199 100644
--- a/arch/arm/boards/beagle/board.c
+++ b/arch/arm/boards/beagle/board.c
@@ -55,12 +55,6 @@
 #include <ns16550.h>
 #include <asm/armlinux.h>
 #include <generated/mach-types.h>
-#include <mach/omap3-silicon.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
-#include <mach/omap3-mux.h>
 #include <mach/gpmc.h>
 #include <mach/gpmc_nand.h>
 #include <mach/ehci.h>
@@ -70,169 +64,6 @@
 #include <usb/ehci.h>
 #include <mach/xload.h>
 
-/******************** Board Boot Time *******************/
-
-/**
- * @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
- *
- * @return void
- */
-static void sdrc_init(void)
-{
-	/* SDRAM software reset */
-	/* No idle ack and RESET enable */
-	writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
-	sdelay(100);
-	/* No idle ack and RESET disable */
-	writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
-
-	/* SDRC Sharing register */
-	/* 32-bit SDRAM on data lane [31:0] - CS0 */
-	/* pin tri-stated = 1 */
-	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
-
-	/* ----- SDRC Registers Configuration --------- */
-	/* SDRC_MCFG0 register */
-	writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
-
-	/* SDRC_RFR_CTRL0 register */
-	writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
-
-	/* SDRC_ACTIM_CTRLA0 register */
-	writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
-
-	/* SDRC_ACTIM_CTRLB0 register */
-	writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
-
-	/* Disble Power Down of CKE due to 1 CKE on combo part */
-	writel(0x00000081, OMAP3_SDRC_REG(POWER));
-
-	/* SDRC_MANUAL command register */
-	/* NOP command */
-	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
-	/* Precharge command */
-	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-
-	/* SDRC MR0 register Burst length=4 */
-	writel(0x00000032, OMAP3_SDRC_REG(MR_0));
-
-	/* SDRC DLLA control register */
-	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
-
-	return;
-}
-
-/**
- * @brief Do the pin muxing required for Board operation.
- * We enable ONLY the pins we require to set. OMAP provides pins which do not
- * have alternate modes. Such pins done need to be set.
- *
- * See @ref MUX_VAL for description of the muxing mode.
- *
- * @return void
- */
-static void mux_config(void)
-{
-	/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
-
-	/* GPMC */
-	MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
-
-	/* D0-D7 default mux mode is mode0 */
-	MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
-	/* GPMC_NADV_ALE default mux mode is mode0 */
-	/* GPMC_NOE default mux mode is mode0 */
-	/* GPMC_NWE default mux mode is mode0 */
-	/* GPMC_NBE0_CLE default mux mode is mode0 */
-	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
-	/* GPMC_WAIT0 default mux mode is mode0 */
-	MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
-
-	/* SERIAL INTERFACE */
-	MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
-	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
-	MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
-	/* I2C1_SCL default mux mode is mode0 */
-	/* I2C1_SDA default mux mode is mode0 */
-	/* USB EHCI (port 2) */
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3));
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/;
-}
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int beagle_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	if (!in_sdram)
-		omap3_core_init();
-
-	mux_config();
-	/* Dont reconfigure SDRAM while running in SDRAM! */
-	if (!in_sdram)
-		sdrc_init();
-
-	return 0;
-}
-pure_initcall(beagle_board_init);
-
-/******************** Board Run Time *******************/
-
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
 
 /**
diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c
new file mode 100644
index 000000000..677f055aa
--- /dev/null
+++ b/arch/arm/boards/beagle/lowlevel.c
@@ -0,0 +1,167 @@
+#include <io.h>
+#include <init.h>
+#include <mach/control.h>
+#include <mach/omap3-silicon.h>
+#include <mach/omap3-mux.h>
+#include <mach/sdrc.h>
+#include <mach/syslib.h>
+#include <mach/sys_info.h>
+
+/**
+ * @brief Do the pin muxing required for Board operation.
+ * We enable ONLY the pins we require to set. OMAP provides pins which do not
+ * have alternate modes. Such pins done need to be set.
+ *
+ * See @ref MUX_VAL for description of the muxing mode.
+ *
+ * @return void
+ */
+static void mux_config(void)
+{
+	/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
+
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
+
+	/* D0-D7 default mux mode is mode0 */
+	MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
+	/* GPMC_NADV_ALE default mux mode is mode0 */
+	/* GPMC_NOE default mux mode is mode0 */
+	/* GPMC_NWE default mux mode is mode0 */
+	/* GPMC_NBE0_CLE default mux mode is mode0 */
+	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+	/* GPMC_WAIT0 default mux mode is mode0 */
+	MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
+
+	/* SERIAL INTERFACE */
+	MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
+	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
+	MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
+	/* I2C1_SCL default mux mode is mode0 */
+	/* I2C1_SDA default mux mode is mode0 */
+	/* USB EHCI (port 2) */
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M3));
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/;
+}
+
+/**
+ * @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
+ *
+ * @return void
+ */
+static void sdrc_init(void)
+{
+	/* SDRAM software reset */
+	/* No idle ack and RESET enable */
+	writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
+	sdelay(100);
+	/* No idle ack and RESET disable */
+	writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
+
+	/* SDRC Sharing register */
+	/* 32-bit SDRAM on data lane [31:0] - CS0 */
+	/* pin tri-stated = 1 */
+	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
+
+	/* ----- SDRC Registers Configuration --------- */
+	/* SDRC_MCFG0 register */
+	writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
+
+	/* SDRC_RFR_CTRL0 register */
+	writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
+
+	/* SDRC_ACTIM_CTRLA0 register */
+	writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
+
+	/* SDRC_ACTIM_CTRLB0 register */
+	writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
+
+	/* Disble Power Down of CKE due to 1 CKE on combo part */
+	writel(0x00000081, OMAP3_SDRC_REG(POWER));
+
+	/* SDRC_MANUAL command register */
+	/* NOP command */
+	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
+	/* Precharge command */
+	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+
+	/* SDRC MR0 register Burst length=4 */
+	writel(0x00000032, OMAP3_SDRC_REG(MR_0));
+
+	/* SDRC DLLA control register */
+	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
+
+	return;
+}
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int beagle_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	if (!in_sdram)
+		omap3_core_init();
+
+	mux_config();
+	/* Dont reconfigure SDRAM while running in SDRAM! */
+	if (!in_sdram)
+		sdrc_init();
+
+	return 0;
+}
+pure_initcall(beagle_board_init);

From 52e321255c983c78d36c6690d5ec2fb7dcab93a8 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue, 29 Jan 2013 08:42:50 +0100
Subject: [PATCH 10/16] ARM omap3 phycard-a-l1: move lowlevel code to
 lowlevel.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/phycard-a-l1/Makefile   |   2 +
 arch/arm/boards/phycard-a-l1/lowlevel.c | 251 ++++++++++++++++++++++++
 arch/arm/boards/phycard-a-l1/pca-a-l1.c | 247 -----------------------
 3 files changed, 253 insertions(+), 247 deletions(-)
 create mode 100644 arch/arm/boards/phycard-a-l1/lowlevel.c

diff --git a/arch/arm/boards/phycard-a-l1/Makefile b/arch/arm/boards/phycard-a-l1/Makefile
index 7041e1106..5565c3d06 100644
--- a/arch/arm/boards/phycard-a-l1/Makefile
+++ b/arch/arm/boards/phycard-a-l1/Makefile
@@ -15,3 +15,5 @@
 #
 
 obj-y += pca-a-l1.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c
new file mode 100644
index 000000000..d82c43df5
--- /dev/null
+++ b/arch/arm/boards/phycard-a-l1/lowlevel.c
@@ -0,0 +1,251 @@
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <sizes.h>
+#include <mach/omap3-mux.h>
+#include <mach/sdrc.h>
+#include <mach/control.h>
+#include <mach/syslib.h>
+#include <mach/omap3-silicon.h>
+#include <mach/sys_info.h>
+
+/* Slower full frequency range default timings for x32 operation */
+#define SDP_SDRC_SHARING	0x00000100
+/* Diabling power down mode using CKE pin */
+#define SDP_SDRC_POWER_POP	0x00000081
+/* rkw - need to find of 90/72 degree recommendation for speed like before. */
+#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
+	(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+
+/* used to create an array of memory configuartions. */
+struct sdrc_config {
+	u32	cs_cfg;
+	u32	mcfg;
+	u32	mr;
+	u32	actim_ctrla;
+	u32	actim_ctrlb;
+	u32	rfr_ctrl;
+} const sdrc_config[] = {
+/* max cs_size for autodetection, common timing */
+/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */
+{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
+/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */
+{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
+/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */
+{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
+/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */
+{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
+};
+
+/*
+ * Boot-time initialization(s)
+ */
+
+/*********************************************************************
+ * init_sdram_ddr() - Init DDR controller.
+ *********************************************************************/
+void init_sdram_ddr(void)
+{
+	/* reset sdrc controller */
+	writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG));
+	wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000);
+	writel(0, OMAP3_SDRC_REG(SYSCONFIG));
+
+	/* setup sdrc to ball mux */
+	writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING));
+	writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER));
+
+	/* set up dll */
+	writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL));
+	sdelay(0x2000);	/* give time to lock */
+
+}
+/*********************************************************************
+ * config_sdram_ddr() - Init DDR on dev board.
+ *********************************************************************/
+void config_sdram_ddr(u8 cs, u8 cfg)
+{
+
+	writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs));
+	writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
+	writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
+	writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
+
+	writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
+
+	sdelay(5000);
+
+	writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
+	writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
+	writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
+
+	/* set mr0 */
+	writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs));
+
+	sdelay(2000);
+}
+
+/**
+ * @brief Initialize the SDRC module
+ * Initialisation for 1x256MByte but normally
+ * done by x-loader.
+ * @return void
+ */
+static void pcaal1_sdrc_init(void)
+{
+	u32 test0, test1;
+	char cfg;
+
+	init_sdram_ddr();
+
+	config_sdram_ddr(0, 0); /* 256MByte at CS0 */
+	config_sdram_ddr(1, 0); /* 256MByte at CS1 */
+
+	test0 = get_ram_size((long *) 0x80000000, SZ_256M);
+	test1 = get_ram_size((long *) 0xA0000000, SZ_256M);
+
+	/* mask out lower nible, its not tested with
+	in common/memsize.c */
+	test1 &= 0xfffffff0;
+
+	if ((test1 > 0) && (test1 != test0))
+		hang();
+
+	cfg = -1; /* illegal configuration found */
+
+	if (test1 == 0) {
+		init_sdram_ddr();
+		writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1));
+
+		/* 1 x 256MByte */
+		if (test0 == SZ_256M)
+			cfg = 2;
+
+		if (cfg != -1) {
+			config_sdram_ddr(0, cfg);
+			writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
+		}
+		return;
+	}
+
+	/* reinit both cs with correct size */
+	/* 2 x 128MByte */
+	if (test0 == SZ_128M)
+		cfg = 1;
+	/* 2 x 256MByte */
+	if (test0 == SZ_256M)
+		cfg = 3;
+
+	if (cfg != -1) {
+		init_sdram_ddr();
+		writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
+		config_sdram_ddr(0, cfg);
+		config_sdram_ddr(1, cfg);
+	}
+}
+
+/**
+ * @brief Do the necessary pin muxing required for phyCARD-A-L1.
+ * Some pins in OMAP3 do not have alternate modes.
+ * We don't program these pins.
+ *
+ * See @ref MUX_VAL for description of the muxing mode.
+ *
+ * @return void
+ */
+static void pcaal1_mux_config(void)
+{
+	/*
+	 * Serial Interface
+	 */
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
+
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));
+
+	/* ETH_PME (GPIO_55) */
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M4));
+	/* #CS5 (Ethernet) */
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0));
+	/* ETH_FIFO_SEL (GPIO_57) */
+	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTD | EN  | M4));
+	/* ETH_AMDIX_EN (GPIO_58) */
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M4));
+	/* ETH_nRST (GPIO_64) */
+	MUX_VAL(CP(GPMC_WAIT2),		(IDIS | PTU | EN  | M4));
+
+	/* HSMMC1 */
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
+
+	/* USBOTG_nRST (GPIO_63) */
+	MUX_VAL(CP(GPMC_WAIT1),		(IDIS | PTU | EN  | M4));
+
+	/* USBH_nRST (GPIO_65) */
+	MUX_VAL(CP(GPMC_WAIT3),		(IDIS | PTU | EN  | M4));
+}
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int pcaal1_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	if (!in_sdram)
+		omap3_core_init();
+
+	pcaal1_mux_config();
+	/* Dont reconfigure SDRAM while running in SDRAM! */
+	if (!in_sdram)
+		pcaal1_sdrc_init();
+
+	return 0;
+}
+pure_initcall(pcaal1_board_init);
+
diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
index db90e0ead..234d689f9 100644
--- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c
+++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
@@ -51,264 +51,17 @@
 #include <asm/io.h>
 #include <generated/mach-types.h>
 #include <linux/err.h>
-#include <mach/control.h>
 #include <mach/gpmc.h>
 #include <mach/gpmc_nand.h>
 #include <mach/omap_hsmmc.h>
 #include <mach/xload.h>
-#include <mach/omap3-mux.h>
 #include <mach/sdrc.h>
 #include <mach/omap3-silicon.h>
 #include <mach/sys_info.h>
-#include <mach/syslib.h>
 #include <mach/omap3-devices.h>
 
 #define SMC911X_BASE 0x2c000000
 
-/* Slower full frequency range default timings for x32 operation */
-#define SDP_SDRC_SHARING	0x00000100
-/* Diabling power down mode using CKE pin */
-#define SDP_SDRC_POWER_POP	0x00000081
-/* rkw - need to find of 90/72 degree recommendation for speed like before. */
-#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
-	(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
-
-/* used to create an array of memory configuartions. */
-struct sdrc_config {
-	u32	cs_cfg;
-	u32	mcfg;
-	u32	mr;
-	u32	actim_ctrla;
-	u32	actim_ctrlb;
-	u32	rfr_ctrl;
-} const sdrc_config[] = {
-/* max cs_size for autodetection, common timing */
-/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */
-{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
-/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */
-{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
-/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */
-{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
-/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */
-{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
-};
-
-/*
- * Boot-time initialization(s)
- */
-
-/*********************************************************************
- * init_sdram_ddr() - Init DDR controller.
- *********************************************************************/
-void init_sdram_ddr(void)
-{
-	/* reset sdrc controller */
-	writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG));
-	wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000);
-	writel(0, OMAP3_SDRC_REG(SYSCONFIG));
-
-	/* setup sdrc to ball mux */
-	writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING));
-	writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER));
-
-	/* set up dll */
-	writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL));
-	sdelay(0x2000);	/* give time to lock */
-
-}
-/*********************************************************************
- * config_sdram_ddr() - Init DDR on dev board.
- *********************************************************************/
-void config_sdram_ddr(u8 cs, u8 cfg)
-{
-
-	writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs));
-	writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
-	writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
-	writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
-
-	writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
-
-	sdelay(5000);
-
-	writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
-	writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
-	writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
-
-	/* set mr0 */
-	writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs));
-
-	sdelay(2000);
-}
-
-/**
- * @brief Initialize the SDRC module
- * Initialisation for 1x256MByte but normally
- * done by x-loader.
- * @return void
- */
-static void pcaal1_sdrc_init(void)
-{
-	u32 test0, test1;
-	char cfg;
-
-	init_sdram_ddr();
-
-	config_sdram_ddr(0, 0); /* 256MByte at CS0 */
-	config_sdram_ddr(1, 0); /* 256MByte at CS1 */
-
-	test0 = get_ram_size((long *) 0x80000000, SZ_256M);
-	test1 = get_ram_size((long *) 0xA0000000, SZ_256M);
-
-	/* mask out lower nible, its not tested with
-	in common/memsize.c */
-	test1 &= 0xfffffff0;
-
-	if ((test1 > 0) && (test1 != test0))
-		hang();
-
-	cfg = -1; /* illegal configuration found */
-
-	if (test1 == 0) {
-		init_sdram_ddr();
-		writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1));
-
-		/* 1 x 256MByte */
-		if (test0 == SZ_256M)
-			cfg = 2;
-
-		if (cfg != -1) {
-			config_sdram_ddr(0, cfg);
-			writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
-		}
-		return;
-	}
-
-	/* reinit both cs with correct size */
-	/* 2 x 128MByte */
-	if (test0 == SZ_128M)
-		cfg = 1;
-	/* 2 x 256MByte */
-	if (test0 == SZ_256M)
-		cfg = 3;
-
-	if (cfg != -1) {
-		init_sdram_ddr();
-		writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
-		config_sdram_ddr(0, cfg);
-		config_sdram_ddr(1, cfg);
-	}
-}
-
-/**
- * @brief Do the necessary pin muxing required for phyCARD-A-L1.
- * Some pins in OMAP3 do not have alternate modes.
- * We don't program these pins.
- *
- * See @ref MUX_VAL for description of the muxing mode.
- *
- * @return void
- */
-static void pcaal1_mux_config(void)
-{
-	/*
-	 * Serial Interface
-	 */
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0));
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | EN  | M0));
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
-
-	/* GPMC */
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));
-
-	/* ETH_PME (GPIO_55) */
-	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M4));
-	/* #CS5 (Ethernet) */
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0));
-	/* ETH_FIFO_SEL (GPIO_57) */
-	MUX_VAL(CP(GPMC_NCS6),		(IDIS | PTD | EN  | M4));
-	/* ETH_AMDIX_EN (GPIO_58) */
-	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M4));
-	/* ETH_nRST (GPIO_64) */
-	MUX_VAL(CP(GPMC_WAIT2),		(IDIS | PTU | EN  | M4));
-
-	/* HSMMC1 */
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
-
-	/* USBOTG_nRST (GPIO_63) */
-	MUX_VAL(CP(GPMC_WAIT1),		(IDIS | PTU | EN  | M4));
-
-	/* USBH_nRST (GPIO_65) */
-	MUX_VAL(CP(GPMC_WAIT3),		(IDIS | PTU | EN  | M4));
-}
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int pcaal1_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	if (!in_sdram)
-		omap3_core_init();
-
-	pcaal1_mux_config();
-	/* Dont reconfigure SDRAM while running in SDRAM! */
-	if (!in_sdram)
-		pcaal1_sdrc_init();
-
-	return 0;
-}
-pure_initcall(pcaal1_board_init);
-
-/*
- * Run-time initialization(s)
- */
-
 /**
  * @brief Initialize the serial port to be used as console.
  *

From 8acd8a37f6bc2d3c0d0f81ef63968c44001b1cf6 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue, 29 Jan 2013 08:46:23 +0100
Subject: [PATCH 11/16] ARM omap3 omap343xdsp: move lowlevel code to lowlevel.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/omap343xdsp/Makefile   |   2 +
 arch/arm/boards/omap343xdsp/board.c    | 547 -------------------------
 arch/arm/boards/omap343xdsp/lowlevel.c | 546 ++++++++++++++++++++++++
 3 files changed, 548 insertions(+), 547 deletions(-)
 create mode 100644 arch/arm/boards/omap343xdsp/lowlevel.c

diff --git a/arch/arm/boards/omap343xdsp/Makefile b/arch/arm/boards/omap343xdsp/Makefile
index dcfc2937d..88c223aa6 100644
--- a/arch/arm/boards/omap343xdsp/Makefile
+++ b/arch/arm/boards/omap343xdsp/Makefile
@@ -1 +1,3 @@
 obj-y += board.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c
index 6dbbc4c47..215fe02ef 100644
--- a/arch/arm/boards/omap343xdsp/board.c
+++ b/arch/arm/boards/omap343xdsp/board.c
@@ -50,556 +50,9 @@
 #include <asm/armlinux.h>
 #include <mach/omap3-silicon.h>
 #include <mach/omap3-devices.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
-#include <mach/omap3-mux.h>
 #include <mach/gpmc.h>
 #include <errno.h>
 
-/******************** Board Boot Time *******************/
-static void sdrc_init(void);
-static void mux_config(void);
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int sdp343x_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	if (!in_sdram)
-		omap3_core_init();
-
-	mux_config();
-	if (!in_sdram)
-		sdrc_init();
-
-	return 0;
-}
-pure_initcall(sdp343x_board_init);
-
-/**
- * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
- *
- * @return void
- */
-static void sdrc_init(void)
-{
-	/* Issue SDRC Soft reset  */
-	writel(0x12, OMAP3_SDRC_REG(SYSCONFIG));
-    /* Wait until Reset complete */
-    while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0);
-    /* SDRC to normal mode */
-	writel(0x10, OMAP3_SDRC_REG(SYSCONFIG));
-	/* SDRC Sharing register */
-	/* 32-bit SDRAM on data lane [31:0] - CS0 */
-	/* pin tri-stated = 1 */
-	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
-
-	/* ----- SDRC_REG(CS0 Configuration --------- */
-	/* SDRC_REG(MCFG0 register */
-	writel(0x02584019, OMAP3_SDRC_REG(MCFG_0));
-
-	/* SDRC_REG(RFR_CTRL0 register */
-	writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0));
-
-	/* SDRC_REG(ACTIM_CTRLA0 register */
-	writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
-
-	/* SDRC_REG(ACTIM_CTRLB0 register */
-	writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
-
-	/* Disble Power Down of CKE cuz of 1 CKE on combo part */
-	writel(0x00000081, OMAP3_SDRC_REG(POWER));
-
-	/* SDRC_REG(Manual command register */
-	/* NOP command */
-	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
-	/* Precharge command */
-	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-
-	/* SDRC MR0 register */
-	/* CAS latency = 3 */
-	/* Write Burst = Read Burst */
-	/* Serial Mode */
-	writel(0x00000032, OMAP3_SDRC_REG(MR_0));	/* Burst length =4 */
-
-    /* SDRC DLLA control register */
-	/* Enable DLL A */
-	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
-
-    /* wait until DLL is locked  */
-    while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
-	return;
-}
-
-/**
- * @brief Do the pin muxing required for Board operation.
- *
- * See @ref MUX_VAL for description of the muxing mode. Since some versions
- * of Linux depend on all pin muxing being done at barebox level, we may need to
- * enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing.
- *
- * @return void
- */
-static void mux_config(void)
-{
-	/* Essential MUX Settings */
-	MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));	/* SDRC_D0 */
-	MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));	/* SDRC_D1 */
-	MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));	/* SDRC_D2 */
-	MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));	/* SDRC_D3 */
-	MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));	/* SDRC_D4 */
-	MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));	/* SDRC_D5 */
-	MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));	/* SDRC_D6 */
-	MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));	/* SDRC_D7 */
-	MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));	/* SDRC_D8 */
-	MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));	/* SDRC_D9 */
-	MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));	/* SDRC_D10 */
-	MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));	/* SDRC_D11 */
-	MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));	/* SDRC_D12 */
-	MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));	/* SDRC_D13 */
-	MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));	/* SDRC_D14 */
-	MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));	/* SDRC_D15 */
-	MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));	/* SDRC_D16 */
-	MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));	/* SDRC_D17 */
-	MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));	/* SDRC_D18 */
-	MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));	/* SDRC_D19 */
-	MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));	/* SDRC_D20 */
-	MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));	/* SDRC_D21 */
-	MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));	/* SDRC_D22 */
-	MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));	/* SDRC_D23 */
-	MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));	/* SDRC_D24 */
-	MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));	/* SDRC_D25 */
-	MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));	/* SDRC_D26 */
-	MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));	/* SDRC_D27 */
-	MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));	/* SDRC_D28 */
-	MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));	/* SDRC_D29 */
-	MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));	/* SDRC_D30 */
-	MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));	/* SDRC_D31 */
-	MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));	/* SDRC_CLK */
-	MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));	/* SDRC_DQS0 */
-	MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));	/* SDRC_DQS1 */
-	MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));	/* SDRC_DQS2 */
-	MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));	/* SDRC_DQS3 */
-	/* GPMC */
-	MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));	/* GPMC_A1 */
-	MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));	/* GPMC_A2 */
-	MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));	/* GPMC_A3 */
-	MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));	/* GPMC_A4 */
-	MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));	/* GPMC_A5 */
-	MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));	/* GPMC_A6 */
-	MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));	/* GPMC_A7 */
-	MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));	/* GPMC_A8 */
-	MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));	/* GPMC_A9 */
-	MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));	/* GPMC_A10 */
-	MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0));	/* GPMC_D0 */
-	MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0));	/* GPMC_D1 */
-	MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0));	/* GPMC_D2 */
-	MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0));	/* GPMC_D3 */
-	MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0));	/* GPMC_D4 */
-	MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0));	/* GPMC_D5 */
-	MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0));	/* GPMC_D6 */
-	MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0));	/* GPMC_D7 */
-	MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));	/* GPMC_D8 */
-	MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));	/* GPMC_D9 */
-	MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));	/* GPMC_D10 */
-	MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));	/* GPMC_D11 */
-	MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));	/* GPMC_D12 */
-	MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));	/* GPMC_D13 */
-	MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));	/* GPMC_D14 */
-	MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));	/* GPMC_D15 */
-	MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));	/* GPMC_NCS0 */
-	MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));	/* GPMC_NCS1 */
-	MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));	/* GPMC_NCS2 */
-	MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0));	/* GPMC_NCS3 */
-	/* GPIO_55 - FLASH_DIS */
-	MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4));
-	/* GPIO_56 - TORCH_EN */
-	MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4));
-	/* GPIO_57 - AGPS SLP */
-	MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4));
-	/* GPMC_58 - WLAN_IRQ */
-	MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4));
-	MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));	/* GPMC_CLK */
-	/* GPMC_NADV_ALE */
-	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));	/* GPMC_NOE */
-	MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));	/* GPMC_NWE */
-	/* GPMC_NBE0_CLE */
-	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4));	/* GPIO_61 -BT_SHUTDN */
-	MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));	/* GPMC_NWP */
-	MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));	/* GPMC_WAIT0 */
-	MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));	/* GPMC_WAIT1 */
-	MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4));	/* GPIO_64 */
-	MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));	/* GPIO_65 */
-
-	/* SERIAL INTERFACE */
-	/* UART3_CTS_RCTX */
-	MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
-	/* UART3_RTS_SD */
-	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
-	/* UART3_RX_IRRX */
-	MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
-	/* UART3_TX_IRTX */
-	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
-	/* HSUSB0_CLK */
-	MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
-	/* HSUSB0_STP */
-	MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
-	/* HSUSB0_DIR */
-	MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
-	/* HSUSB0_NXT */
-	MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA0 */
-	MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA1 */
-	MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA2 */
-	MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA3 */
-	MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA4 */
-	MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA5 */
-	MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA6 */
-	MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
-	/* HSUSB0_DATA7 */
-	MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));	/* I2C1_SCL */
-	MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));	/* I2C1_SDA */
-#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX
-	/* DSS */
-	MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));	/* DSS_PCLK */
-	MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));	/* DSS_HSYNC */
-	MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));	/* DSS_VSYNC */
-	MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));	/* DSS_ACBIAS */
-	MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));	/* DSS_DATA0 */
-	MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));	/* DSS_DATA1 */
-	MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));	/* DSS_DATA2 */
-	MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));	/* DSS_DATA3 */
-	MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));	/* DSS_DATA4 */
-	MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));	/* DSS_DATA5 */
-	MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));	/* DSS_DATA6 */
-	MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));	/* DSS_DATA7 */
-	MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));	/* DSS_DATA8 */
-	MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));	/* DSS_DATA9 */
-	MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));	/* DSS_DATA10 */
-	MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));	/* DSS_DATA11 */
-	MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));	/* DSS_DATA12 */
-	MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));	/* DSS_DATA13 */
-	MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));	/* DSS_DATA14 */
-	MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));	/* DSS_DATA15 */
-	MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));	/* DSS_DATA16 */
-	MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));	/* DSS_DATA17 */
-	MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));	/* DSS_DATA18 */
-	MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));	/* DSS_DATA19 */
-	MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));	/* DSS_DATA20 */
-	MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));	/* DSS_DATA21 */
-	MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));	/* DSS_DATA22 */
-	MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));	/* DSS_DATA23 */
-	/* CAMERA */
-	MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0));	/* CAM_HS */
-	MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0));	/* CAM_VS */
-	MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0));	/* CAM_XCLKA */
-	MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0));	/* CAM_PCLK */
-	/* GPIO_98 - CAM_RESET */
-	MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4));
-	MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0));	/* CAM_D0 */
-	MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0));	/* CAM_D1 */
-	MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0));	/* CAM_D2 */
-	MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0));	/* CAM_D3 */
-	MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0));	/* CAM_D4 */
-	MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0));	/* CAM_D5 */
-	MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0));	/* CAM_D6 */
-	MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0));	/* CAM_D7 */
-	MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0));	/* CAM_D8 */
-	MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0));	/* CAM_D9 */
-	MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0));	/* CAM_D10 */
-	MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0));	/* CAM_D11 */
-	MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0));	/* CAM_XCLKB */
-	MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4));	/* GPIO_167 */
-	MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0));	/* CAM_STROBE */
-	MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0));	/* CSI2_DX0 */
-	MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0));	/* CSI2_DY0 */
-	MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0));	/* CSI2_DX1 */
-	MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0));	/* CSI2_DY1 */
-	/* AUDIO INTERFACE */
-	MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0));	/* MCBSP2_FSX */
-	/* MCBSP2_CLKX */
-	MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0));	/* MCBSP2_DR */
-	MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0));	/* MCBSP2_DX */
-	/* EXPANSION CARD  */
-	MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));	/* MMC1_CLK */
-	MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));	/* MMC1_CMD */
-	MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));	/* MMC1_DAT0 */
-	MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));	/* MMC1_DAT1 */
-	MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));	/* MMC1_DAT2 */
-	MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));	/* MMC1_DAT3 */
-	MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0));	/* MMC1_DAT4 */
-	MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0));	/* MMC1_DAT5 */
-	MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0));	/* MMC1_DAT6 */
-	MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0));	/* MMC1_DAT7 */
-	/* WIRELESS LAN */
-	MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0));	/* MMC2_CLK */
-	MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0));	/* MMC2_CMD */
-	MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0));	/* MMC2_DAT0 */
-	MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0));	/* MMC2_DAT1 */
-	MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0));	/* MMC2_DAT2 */
-	MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0));	/* MMC2_DAT3 */
-	/* MMC2_DIR_DAT0 */
-	MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1));
-	/* MMC2_DIR_DAT1 */
-	MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1));
-	/* MMC2_DIR_CMD */
-	MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1));
-	/* MMC2_CLKIN */
-	MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1));
-	/* BLUETOOTH */
-	/* MCBSP3_DX */
-	MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0));
-	/* MCBSP3_DR */
-	MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0));
-	/* MCBSP3_CLKX */
-	MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0));
-	/* MCBSP3_FSX */
-	MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0));	/* UART2_CTS */
-	MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0));	/* UART2_RTS */
-	MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0));	/* UART2_TX */
-	MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0));	/* UART2_RX */
-	/* MODEM INTERFACE */
-	MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));	/* UART1_TX */
-	MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));	/* UART1_RTS */
-	MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));	/* UART1_CTS */
-	MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));	/* UART1_RX */
-	/* SSI1_DAT_RX */
-	MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1));
-	MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1));	/* SSI1_FLAG_RX */
-	MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1));	/* SSI1_RDY_RX  */
-	MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1));	/* SSI1_WAKE */
-	/* MCBSP1_CLKR  */
-	MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0));
-	/* GPIO_157 - BT_WKUP */
-	MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4));
-	/* MCBSP1_DX */
-	MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0));	/* MCBSP1_DR */
-	/* MCBSP_CLKS  */
-	MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0));
-	/* MCBSP1_FSX */
-	MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0));
-	/* MCBSP1_CLKX  */
-	MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0));
-	/* SERIAL INTERFACE */
-	MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));	/* I2C2_SCL */
-	MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));	/* I2C2_SDA */
-	MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));	/* I2C3_SCL */
-	MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));	/* I2C3_SDA */
-	MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0));	/* I2C4_SCL */
-	MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0));	/* I2C4_SDA */
-	MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));	/* HDQ_SIO */
-	/* MCSPI1_CLK */
-	MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0));
-	/* MCSPI1_SIMO */
-	MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0));
-	/* MCSPI1_SOMI */
-	MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0));
-	/* MCSPI1_CS0 */
-	MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0));
-	/* MCSPI1_CS1 */
-	MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0));
-	/* GPIO_176-NOR_DPD */
-	MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4));
-	/* MCSPI1_CS3 */
-	MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0));
-	/* MCSPI2_CLK */
-	MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0));
-	/* MCSPI2_SIMO */
-	MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0));
-	/* MCSPI2_SOMI */
-	MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0));
-	/* MCSPI2_CS0 */
-	MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0));
-	/* MCSPI2_CS1 */
-	MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0));
-
-	/* CONTROL AND DEBUG */
-	MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0));	/* SYS_32K */
-	MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0));	/* SYS_CLKREQ */
-	MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));	/* SYS_NIRQ */
-	MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4));	/* GPIO_2 - PEN_IRQ */
-	MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4));	/* GPIO_3 */
-	MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4));	/* GPIO_4 - MMC1_WP */
-	MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4));	/* GPIO_5 - LCD_ENVDD */
-	MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4));	/* GPIO_6 - LAN_INTR0 */
-	MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4));	/* GPIO_7 - MMC2_WP */
-	/* GPIO_8-LCD_ENBKL */
-	MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4));
-	/* SYS_OFF_MODE */
-	MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
-	/* SYS_CLKOUT1  */
-	MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
-	MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4));	/* GPIO_186 */
-	MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));	/* JTAG_NTRST */
-	MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0));	/* JTAG_TCK */
-	MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0));	/* JTAG_TMS */
-	MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0));	/* JTAG_TDI */
-	MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0));	/* JTAG_EMU0 */
-	MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0));	/* JTAG_EMU1 */
-	/* HSUSB1_TLL_STP */
-	MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
-	/* HSUSB1_TLL_CLK */
-	MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
-	/* HSUSB1_TLL_DATA0 */
-	MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1));
-	/* MCSPI3_CS0 */
-	MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1));
-	/* HSUSB1_TLL_DATA2 */
-	MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1));
-	/* HSUSB1_TLL_DATA7 */
-	MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1));
-	/* HSUSB1_TLL_DATA4 */
-	MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_DATA5 */
-	MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_DATA6 */
-	MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_DATA3 */
-	MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_DIR */
-	MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB1_TLL_NXT */
-	MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_CLK */
-	MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_STP */
-	MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_DIR */
-	MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_NXT */
-	MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_DATA0 */
-	MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
-	/* HSUSB2_TLL_DATA1 */
-	MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
-
-	/* DIE TO DIE */
-	MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0));	/* D2D_MCAD0 */
-	MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0));	/* D2D_MCAD1 */
-	MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0));	/* D2D_MCAD2 */
-	MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0));	/* D2D_MCAD3 */
-	MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0));	/* D2D_MCAD4 */
-	MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0));	/* D2D_MCAD5 */
-	MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0));	/* D2D_MCAD6 */
-	MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0));	/* D2D_MCAD7 */
-	MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0));	/* D2D_MCAD8 */
-	MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0));	/* D2D_MCAD9 */
-	MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0));	/* D2D_MCAD10 */
-	MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0));	/* D2D_MCAD11 */
-	MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0));	/* D2D_MCAD12 */
-	MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0));	/* D2D_MCAD13 */
-	MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0));	/* D2D_MCAD14 */
-	MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0));	/* D2D_MCAD15 */
-	MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0));	/* D2D_MCAD16 */
-	MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0));	/* D2D_MCAD17 */
-	MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0));	/* D2D_MCAD18 */
-	MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0));	/* D2D_MCAD19 */
-	MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0));	/* D2D_MCAD20 */
-	MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0));	/* D2D_MCAD21 */
-	MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0));	/* D2D_MCAD22 */
-	MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0));	/* D2D_MCAD23 */
-	MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0));	/* D2D_MCAD24 */
-	MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0));	/* D2D_MCAD25 */
-	MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0));	/* D2D_MCAD26 */
-	MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0));	/* D2D_MCAD27 */
-	MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0));	/* D2D_MCAD28 */
-	MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0));	/* D2D_MCAD29 */
-	MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0));	/* D2D_MCAD30 */
-	MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0));	/* D2D_MCAD31 */
-	MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0));	/* D2D_MCAD32 */
-	MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0));	/* D2D_MCAD33 */
-	MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0));	/* D2D_MCAD34 */
-	MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0));	/* D2D_MCAD35 */
-	MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0));	/* D2D_MCAD36 */
-	/* D2D_CLK26MI  */
-	MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
-	/* D2D_NRESPWRON */
-	MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
-	/* D2D_NRESWARM */
-	MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
-	/* D2D_ARM9NIRQ */
-	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
-	/* D2D_UMA2P6FIQ */
-	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
-	/* D2D_SPINT */
-	MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
-	/* D2D_FRINT */
-	MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
-	/* D2D_DMAREQ0  */
-	MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
-	/* D2D_DMAREQ1  */
-	MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
-	/* D2D_DMAREQ2  */
-	MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
-	/* D2D_DMAREQ3  */
-	MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTRST  */
-	MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTDI */
-	MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTDO */
-	MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTMS */
-	MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
-	/* D2D_N3GTCK */
-	MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
-	/* D2D_N3GRTCK  */
-	MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
-	/* D2D_MSTDBY */
-	MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
-	/* D2D_SWAKEUP */
-	MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
-	/* D2D_IDLEREQ */
-	MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
-	/* D2D_IDLEACK */
-	MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
-	/* D2D_MWRITE */
-	MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
-	/* D2D_SWRITE */
-	MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
-	/* D2D_MREAD */
-	MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
-	/* D2D_SREAD */
-	MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
-	/* D2D_MBUSFLAG */
-	MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
-	/* D2D_SBUSFLAG */
-	MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
-	/* SDRC_CKE0 */
-	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
-	/* SDRC_CKE1 NOT USED */
-	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
-#endif				/* CONFIG_MACH_OMAP_ADVANCED_MUX */
-}
-
-/******************** Board Run Time *******************/
-
 /*-----------------------CONSOLE  Devices -----------------------------------*/
 
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c
new file mode 100644
index 000000000..0d2ccd4d6
--- /dev/null
+++ b/arch/arm/boards/omap343xdsp/lowlevel.c
@@ -0,0 +1,546 @@
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <sizes.h>
+#include <mach/omap3-mux.h>
+#include <mach/sdrc.h>
+#include <mach/control.h>
+#include <mach/syslib.h>
+#include <mach/omap3-silicon.h>
+#include <mach/sys_info.h>
+
+/**
+ * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
+ *
+ * @return void
+ */
+static void sdrc_init(void)
+{
+	/* Issue SDRC Soft reset  */
+	writel(0x12, OMAP3_SDRC_REG(SYSCONFIG));
+
+	/* Wait until Reset complete */
+	while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0);
+	/* SDRC to normal mode */
+	writel(0x10, OMAP3_SDRC_REG(SYSCONFIG));
+	/* SDRC Sharing register */
+	/* 32-bit SDRAM on data lane [31:0] - CS0 */
+	/* pin tri-stated = 1 */
+	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
+
+	/* ----- SDRC_REG(CS0 Configuration --------- */
+	/* SDRC_REG(MCFG0 register */
+	writel(0x02584019, OMAP3_SDRC_REG(MCFG_0));
+
+	/* SDRC_REG(RFR_CTRL0 register */
+	writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0));
+
+	/* SDRC_REG(ACTIM_CTRLA0 register */
+	writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
+
+	/* SDRC_REG(ACTIM_CTRLB0 register */
+	writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
+
+	/* Disble Power Down of CKE cuz of 1 CKE on combo part */
+	writel(0x00000081, OMAP3_SDRC_REG(POWER));
+
+	/* SDRC_REG(Manual command register */
+	/* NOP command */
+	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
+	/* Precharge command */
+	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+
+	/* SDRC MR0 register */
+	/* CAS latency = 3 */
+	/* Write Burst = Read Burst */
+	/* Serial Mode */
+	writel(0x00000032, OMAP3_SDRC_REG(MR_0));	/* Burst length =4 */
+
+	/* SDRC DLLA control register */
+	/* Enable DLL A */
+	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
+
+	/* wait until DLL is locked  */
+	while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
+}
+
+/**
+ * @brief Do the pin muxing required for Board operation.
+ *
+ * See @ref MUX_VAL for description of the muxing mode. Since some versions
+ * of Linux depend on all pin muxing being done at barebox level, we may need to
+ * enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing.
+ *
+ * @return void
+ */
+static void mux_config(void)
+{
+	/* Essential MUX Settings */
+	MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));	/* SDRC_D0 */
+	MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));	/* SDRC_D1 */
+	MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));	/* SDRC_D2 */
+	MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));	/* SDRC_D3 */
+	MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));	/* SDRC_D4 */
+	MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));	/* SDRC_D5 */
+	MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));	/* SDRC_D6 */
+	MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));	/* SDRC_D7 */
+	MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));	/* SDRC_D8 */
+	MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));	/* SDRC_D9 */
+	MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));	/* SDRC_D10 */
+	MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));	/* SDRC_D11 */
+	MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));	/* SDRC_D12 */
+	MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));	/* SDRC_D13 */
+	MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));	/* SDRC_D14 */
+	MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));	/* SDRC_D15 */
+	MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));	/* SDRC_D16 */
+	MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));	/* SDRC_D17 */
+	MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));	/* SDRC_D18 */
+	MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));	/* SDRC_D19 */
+	MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));	/* SDRC_D20 */
+	MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));	/* SDRC_D21 */
+	MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));	/* SDRC_D22 */
+	MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));	/* SDRC_D23 */
+	MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));	/* SDRC_D24 */
+	MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));	/* SDRC_D25 */
+	MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));	/* SDRC_D26 */
+	MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));	/* SDRC_D27 */
+	MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));	/* SDRC_D28 */
+	MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));	/* SDRC_D29 */
+	MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));	/* SDRC_D30 */
+	MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));	/* SDRC_D31 */
+	MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));	/* SDRC_CLK */
+	MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));	/* SDRC_DQS0 */
+	MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));	/* SDRC_DQS1 */
+	MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));	/* SDRC_DQS2 */
+	MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));	/* SDRC_DQS3 */
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));	/* GPMC_A1 */
+	MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));	/* GPMC_A2 */
+	MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));	/* GPMC_A3 */
+	MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));	/* GPMC_A4 */
+	MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));	/* GPMC_A5 */
+	MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));	/* GPMC_A6 */
+	MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));	/* GPMC_A7 */
+	MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));	/* GPMC_A8 */
+	MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));	/* GPMC_A9 */
+	MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));	/* GPMC_A10 */
+	MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0));	/* GPMC_D0 */
+	MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0));	/* GPMC_D1 */
+	MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0));	/* GPMC_D2 */
+	MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0));	/* GPMC_D3 */
+	MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0));	/* GPMC_D4 */
+	MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0));	/* GPMC_D5 */
+	MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0));	/* GPMC_D6 */
+	MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0));	/* GPMC_D7 */
+	MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));	/* GPMC_D8 */
+	MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));	/* GPMC_D9 */
+	MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));	/* GPMC_D10 */
+	MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));	/* GPMC_D11 */
+	MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));	/* GPMC_D12 */
+	MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));	/* GPMC_D13 */
+	MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));	/* GPMC_D14 */
+	MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));	/* GPMC_D15 */
+	MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));	/* GPMC_NCS0 */
+	MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));	/* GPMC_NCS1 */
+	MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));	/* GPMC_NCS2 */
+	MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0));	/* GPMC_NCS3 */
+	/* GPIO_55 - FLASH_DIS */
+	MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4));
+	/* GPIO_56 - TORCH_EN */
+	MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4));
+	/* GPIO_57 - AGPS SLP */
+	MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4));
+	/* GPMC_58 - WLAN_IRQ */
+	MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4));
+	MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));	/* GPMC_CLK */
+	/* GPMC_NADV_ALE */
+	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));	/* GPMC_NOE */
+	MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));	/* GPMC_NWE */
+	/* GPMC_NBE0_CLE */
+	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4));	/* GPIO_61 -BT_SHUTDN */
+	MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));	/* GPMC_NWP */
+	MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));	/* GPMC_WAIT0 */
+	MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));	/* GPMC_WAIT1 */
+	MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4));	/* GPIO_64 */
+	MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));	/* GPIO_65 */
+
+	/* SERIAL INTERFACE */
+	/* UART3_CTS_RCTX */
+	MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
+	/* UART3_RTS_SD */
+	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
+	/* UART3_RX_IRRX */
+	MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
+	/* UART3_TX_IRTX */
+	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
+	/* HSUSB0_CLK */
+	MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
+	/* HSUSB0_STP */
+	MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
+	/* HSUSB0_DIR */
+	MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
+	/* HSUSB0_NXT */
+	MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA0 */
+	MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA1 */
+	MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA2 */
+	MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA3 */
+	MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA4 */
+	MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA5 */
+	MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA6 */
+	MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
+	/* HSUSB0_DATA7 */
+	MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));	/* I2C1_SCL */
+	MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));	/* I2C1_SDA */
+#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX
+	/* DSS */
+	MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));	/* DSS_PCLK */
+	MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));	/* DSS_HSYNC */
+	MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));	/* DSS_VSYNC */
+	MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));	/* DSS_ACBIAS */
+	MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));	/* DSS_DATA0 */
+	MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));	/* DSS_DATA1 */
+	MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));	/* DSS_DATA2 */
+	MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));	/* DSS_DATA3 */
+	MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));	/* DSS_DATA4 */
+	MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));	/* DSS_DATA5 */
+	MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));	/* DSS_DATA6 */
+	MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));	/* DSS_DATA7 */
+	MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));	/* DSS_DATA8 */
+	MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));	/* DSS_DATA9 */
+	MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));	/* DSS_DATA10 */
+	MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));	/* DSS_DATA11 */
+	MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));	/* DSS_DATA12 */
+	MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));	/* DSS_DATA13 */
+	MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));	/* DSS_DATA14 */
+	MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));	/* DSS_DATA15 */
+	MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));	/* DSS_DATA16 */
+	MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));	/* DSS_DATA17 */
+	MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));	/* DSS_DATA18 */
+	MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));	/* DSS_DATA19 */
+	MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));	/* DSS_DATA20 */
+	MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));	/* DSS_DATA21 */
+	MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));	/* DSS_DATA22 */
+	MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));	/* DSS_DATA23 */
+	/* CAMERA */
+	MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0));	/* CAM_HS */
+	MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0));	/* CAM_VS */
+	MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0));	/* CAM_XCLKA */
+	MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0));	/* CAM_PCLK */
+	/* GPIO_98 - CAM_RESET */
+	MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4));
+	MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0));	/* CAM_D0 */
+	MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0));	/* CAM_D1 */
+	MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0));	/* CAM_D2 */
+	MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0));	/* CAM_D3 */
+	MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0));	/* CAM_D4 */
+	MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0));	/* CAM_D5 */
+	MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0));	/* CAM_D6 */
+	MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0));	/* CAM_D7 */
+	MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0));	/* CAM_D8 */
+	MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0));	/* CAM_D9 */
+	MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0));	/* CAM_D10 */
+	MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0));	/* CAM_D11 */
+	MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0));	/* CAM_XCLKB */
+	MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4));	/* GPIO_167 */
+	MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0));	/* CAM_STROBE */
+	MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0));	/* CSI2_DX0 */
+	MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0));	/* CSI2_DY0 */
+	MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0));	/* CSI2_DX1 */
+	MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0));	/* CSI2_DY1 */
+	/* AUDIO INTERFACE */
+	MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0));	/* MCBSP2_FSX */
+	/* MCBSP2_CLKX */
+	MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0));	/* MCBSP2_DR */
+	MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0));	/* MCBSP2_DX */
+	/* EXPANSION CARD  */
+	MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));	/* MMC1_CLK */
+	MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));	/* MMC1_CMD */
+	MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));	/* MMC1_DAT0 */
+	MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));	/* MMC1_DAT1 */
+	MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));	/* MMC1_DAT2 */
+	MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));	/* MMC1_DAT3 */
+	MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0));	/* MMC1_DAT4 */
+	MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0));	/* MMC1_DAT5 */
+	MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0));	/* MMC1_DAT6 */
+	MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0));	/* MMC1_DAT7 */
+	/* WIRELESS LAN */
+	MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0));	/* MMC2_CLK */
+	MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0));	/* MMC2_CMD */
+	MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0));	/* MMC2_DAT0 */
+	MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0));	/* MMC2_DAT1 */
+	MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0));	/* MMC2_DAT2 */
+	MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0));	/* MMC2_DAT3 */
+	/* MMC2_DIR_DAT0 */
+	MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1));
+	/* MMC2_DIR_DAT1 */
+	MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1));
+	/* MMC2_DIR_CMD */
+	MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1));
+	/* MMC2_CLKIN */
+	MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1));
+	/* BLUETOOTH */
+	/* MCBSP3_DX */
+	MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0));
+	/* MCBSP3_DR */
+	MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0));
+	/* MCBSP3_CLKX */
+	MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0));
+	/* MCBSP3_FSX */
+	MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0));	/* UART2_CTS */
+	MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0));	/* UART2_RTS */
+	MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0));	/* UART2_TX */
+	MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0));	/* UART2_RX */
+	/* MODEM INTERFACE */
+	MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));	/* UART1_TX */
+	MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));	/* UART1_RTS */
+	MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));	/* UART1_CTS */
+	MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));	/* UART1_RX */
+	/* SSI1_DAT_RX */
+	MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1));
+	MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1));	/* SSI1_FLAG_RX */
+	MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1));	/* SSI1_RDY_RX  */
+	MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1));	/* SSI1_WAKE */
+	/* MCBSP1_CLKR  */
+	MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0));
+	/* GPIO_157 - BT_WKUP */
+	MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4));
+	/* MCBSP1_DX */
+	MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0));	/* MCBSP1_DR */
+	/* MCBSP_CLKS  */
+	MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0));
+	/* MCBSP1_FSX */
+	MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0));
+	/* MCBSP1_CLKX  */
+	MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0));
+	/* SERIAL INTERFACE */
+	MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));	/* I2C2_SCL */
+	MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));	/* I2C2_SDA */
+	MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));	/* I2C3_SCL */
+	MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));	/* I2C3_SDA */
+	MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0));	/* I2C4_SCL */
+	MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0));	/* I2C4_SDA */
+	MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));	/* HDQ_SIO */
+	/* MCSPI1_CLK */
+	MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0));
+	/* MCSPI1_SIMO */
+	MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0));
+	/* MCSPI1_SOMI */
+	MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0));
+	/* MCSPI1_CS0 */
+	MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0));
+	/* MCSPI1_CS1 */
+	MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0));
+	/* GPIO_176-NOR_DPD */
+	MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4));
+	/* MCSPI1_CS3 */
+	MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0));
+	/* MCSPI2_CLK */
+	MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0));
+	/* MCSPI2_SIMO */
+	MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0));
+	/* MCSPI2_SOMI */
+	MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0));
+	/* MCSPI2_CS0 */
+	MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0));
+	/* MCSPI2_CS1 */
+	MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0));
+
+	/* CONTROL AND DEBUG */
+	MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0));	/* SYS_32K */
+	MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0));	/* SYS_CLKREQ */
+	MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));	/* SYS_NIRQ */
+	MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4));	/* GPIO_2 - PEN_IRQ */
+	MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4));	/* GPIO_3 */
+	MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4));	/* GPIO_4 - MMC1_WP */
+	MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4));	/* GPIO_5 - LCD_ENVDD */
+	MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4));	/* GPIO_6 - LAN_INTR0 */
+	MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4));	/* GPIO_7 - MMC2_WP */
+	/* GPIO_8-LCD_ENBKL */
+	MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4));
+	/* SYS_OFF_MODE */
+	MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
+	/* SYS_CLKOUT1  */
+	MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
+	MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4));	/* GPIO_186 */
+	MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));	/* JTAG_NTRST */
+	MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0));	/* JTAG_TCK */
+	MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0));	/* JTAG_TMS */
+	MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0));	/* JTAG_TDI */
+	MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0));	/* JTAG_EMU0 */
+	MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0));	/* JTAG_EMU1 */
+	/* HSUSB1_TLL_STP */
+	MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
+	/* HSUSB1_TLL_CLK */
+	MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
+	/* HSUSB1_TLL_DATA0 */
+	MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1));
+	/* MCSPI3_CS0 */
+	MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1));
+	/* HSUSB1_TLL_DATA2 */
+	MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1));
+	/* HSUSB1_TLL_DATA7 */
+	MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1));
+	/* HSUSB1_TLL_DATA4 */
+	MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_DATA5 */
+	MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_DATA6 */
+	MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_DATA3 */
+	MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_DIR */
+	MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB1_TLL_NXT */
+	MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_CLK */
+	MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_STP */
+	MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_DIR */
+	MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_NXT */
+	MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_DATA0 */
+	MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
+	/* HSUSB2_TLL_DATA1 */
+	MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
+
+	/* DIE TO DIE */
+	MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0));	/* D2D_MCAD0 */
+	MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0));	/* D2D_MCAD1 */
+	MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0));	/* D2D_MCAD2 */
+	MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0));	/* D2D_MCAD3 */
+	MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0));	/* D2D_MCAD4 */
+	MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0));	/* D2D_MCAD5 */
+	MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0));	/* D2D_MCAD6 */
+	MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0));	/* D2D_MCAD7 */
+	MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0));	/* D2D_MCAD8 */
+	MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0));	/* D2D_MCAD9 */
+	MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0));	/* D2D_MCAD10 */
+	MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0));	/* D2D_MCAD11 */
+	MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0));	/* D2D_MCAD12 */
+	MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0));	/* D2D_MCAD13 */
+	MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0));	/* D2D_MCAD14 */
+	MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0));	/* D2D_MCAD15 */
+	MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0));	/* D2D_MCAD16 */
+	MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0));	/* D2D_MCAD17 */
+	MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0));	/* D2D_MCAD18 */
+	MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0));	/* D2D_MCAD19 */
+	MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0));	/* D2D_MCAD20 */
+	MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0));	/* D2D_MCAD21 */
+	MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0));	/* D2D_MCAD22 */
+	MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0));	/* D2D_MCAD23 */
+	MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0));	/* D2D_MCAD24 */
+	MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0));	/* D2D_MCAD25 */
+	MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0));	/* D2D_MCAD26 */
+	MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0));	/* D2D_MCAD27 */
+	MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0));	/* D2D_MCAD28 */
+	MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0));	/* D2D_MCAD29 */
+	MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0));	/* D2D_MCAD30 */
+	MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0));	/* D2D_MCAD31 */
+	MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0));	/* D2D_MCAD32 */
+	MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0));	/* D2D_MCAD33 */
+	MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0));	/* D2D_MCAD34 */
+	MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0));	/* D2D_MCAD35 */
+	MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0));	/* D2D_MCAD36 */
+	/* D2D_CLK26MI  */
+	MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
+	/* D2D_NRESPWRON */
+	MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
+	/* D2D_NRESWARM */
+	MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
+	/* D2D_ARM9NIRQ */
+	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
+	/* D2D_UMA2P6FIQ */
+	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
+	/* D2D_SPINT */
+	MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
+	/* D2D_FRINT */
+	MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
+	/* D2D_DMAREQ0  */
+	MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
+	/* D2D_DMAREQ1  */
+	MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
+	/* D2D_DMAREQ2  */
+	MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
+	/* D2D_DMAREQ3  */
+	MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTRST  */
+	MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTDI */
+	MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTDO */
+	MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTMS */
+	MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
+	/* D2D_N3GTCK */
+	MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
+	/* D2D_N3GRTCK  */
+	MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
+	/* D2D_MSTDBY */
+	MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
+	/* D2D_SWAKEUP */
+	MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
+	/* D2D_IDLEREQ */
+	MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
+	/* D2D_IDLEACK */
+	MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
+	/* D2D_MWRITE */
+	MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
+	/* D2D_SWRITE */
+	MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
+	/* D2D_MREAD */
+	MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
+	/* D2D_SREAD */
+	MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
+	/* D2D_MBUSFLAG */
+	MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
+	/* D2D_SBUSFLAG */
+	MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
+	/* SDRC_CKE0 */
+	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+	/* SDRC_CKE1 NOT USED */
+	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
+#endif				/* CONFIG_MACH_OMAP_ADVANCED_MUX */
+}
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int sdp343x_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	if (!in_sdram)
+		omap3_core_init();
+
+	mux_config();
+	if (!in_sdram)
+		sdrc_init();
+
+	return 0;
+}
+pure_initcall(sdp343x_board_init);

From 2f9a2bf63508113d0a1b89f11859bc45c797be4d Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue, 29 Jan 2013 08:48:28 +0100
Subject: [PATCH 12/16] ARM omap3 omap3evm: move lowlevel code to lowlevel.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/omap3evm/Makefile   |   2 +
 arch/arm/boards/omap3evm/board.c    | 158 ---------------------------
 arch/arm/boards/omap3evm/lowlevel.c | 160 ++++++++++++++++++++++++++++
 3 files changed, 162 insertions(+), 158 deletions(-)
 create mode 100644 arch/arm/boards/omap3evm/lowlevel.c

diff --git a/arch/arm/boards/omap3evm/Makefile b/arch/arm/boards/omap3evm/Makefile
index dcfc2937d..88c223aa6 100644
--- a/arch/arm/boards/omap3evm/Makefile
+++ b/arch/arm/boards/omap3evm/Makefile
@@ -1 +1,3 @@
 obj-y += board.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c
index f636fe35d..758554129 100644
--- a/arch/arm/boards/omap3evm/board.c
+++ b/arch/arm/boards/omap3evm/board.c
@@ -47,170 +47,12 @@
 #include <ns16550.h>
 #include <asm/armlinux.h>
 #include <mach/omap3-silicon.h>
-#include <mach/sdrc.h>
-#include <mach/sys_info.h>
-#include <mach/syslib.h>
-#include <mach/control.h>
 #include <mach/omap3-mux.h>
 #include <mach/gpmc.h>
 #include <errno.h>
 #include <generated/mach-types.h>
 #include <mach/omap3-devices.h>
 
-
-/*
- * Boot-time initialization(s)
- */
-
-/**
- * @brief Initialize the SDRC module
- *
- * @return void
- */
-static void sdrc_init(void)
-{
-	/* SDRAM software reset */
-	/* No idle ack and RESET enable */
-	writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
-	sdelay(100);
-	/* No idle ack and RESET disable */
-	writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
-
-	/* SDRC Sharing register */
-	/* 32-bit SDRAM on data lane [31:0] - CS0 */
-	/* pin tri-stated = 1 */
-	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
-
-	/* ----- SDRC Registers Configuration --------- */
-	/* SDRC_MCFG0 register */
-	writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
-
-	/* SDRC_RFR_CTRL0 register */
-	writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
-
-	/* SDRC_ACTIM_CTRLA0 register */
-	writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
-
-	/* SDRC_ACTIM_CTRLB0 register */
-	writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
-
-	/* Disble Power Down of CKE due to 1 CKE on combo part */
-	writel(0x00000081, OMAP3_SDRC_REG(POWER));
-
-	/* SDRC_MANUAL command register */
-	/* NOP command */
-	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
-	/* Precharge command */
-	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-	/* Auto-refresh command */
-	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
-
-	/* SDRC MR0 register Burst length=4 */
-	writel(0x00000032, OMAP3_SDRC_REG(MR_0));
-
-	/* SDRC DLLA control register */
-	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
-
-	return;
-}
-
-/**
- * @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3
- * do not have alternate modes. We don't program these pins.
- *
- * See @ref MUX_VAL for description of the muxing mode.
- *
- * @return void
- */
-static void mux_config(void)
-{
-	/*
-	 * SDRC
-	 * - SDRC_D0-SDRC_D31: Default MUX mode is mode0.
-	 */
-
-	/*
-	 * GPMC
-	 * - GPMC_D0-GPMC_D7: Default MUX mode is mode0.
-	 * - GPMC_NADV_ALE: Default MUX mode is mode0.
-	 * - GPMC_NOE: Default MUX mode is mode0.
-	 * - GPMC_NWE: Default MUX mode is mode0.
-	 * - GPMC_WAIT0: Default MUX mode is mode0.
-	 */
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0));
-
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0));
-
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
-
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0));
-
-	/*
-	 * Serial Interface
-	 */
-#if defined(CONFIG_OMAP3EVM_UART1)
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0));
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0));
-#elif defined(CONFIG_OMAP3EVM_UART3)
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0));
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
-#endif
-}
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int omap3_evm_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	omap3_core_init();
-
-	mux_config();
-
-	/* Dont reconfigure SDRAM while running in SDRAM! */
-	if (!in_sdram)
-		sdrc_init();
-
-	return 0;
-}
-pure_initcall(omap3_evm_board_init);
-
-/*
- * Run-time initialization(s)
- */
-
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
 
 /**
diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c
new file mode 100644
index 000000000..9050c09f7
--- /dev/null
+++ b/arch/arm/boards/omap3evm/lowlevel.c
@@ -0,0 +1,160 @@
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <sizes.h>
+#include <mach/omap3-mux.h>
+#include <mach/sdrc.h>
+#include <mach/control.h>
+#include <mach/syslib.h>
+#include <mach/omap3-silicon.h>
+#include <mach/sys_info.h>
+
+
+/*
+ * Boot-time initialization(s)
+ */
+
+/**
+ * @brief Initialize the SDRC module
+ *
+ * @return void
+ */
+static void sdrc_init(void)
+{
+	/* SDRAM software reset */
+	/* No idle ack and RESET enable */
+	writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
+	sdelay(100);
+	/* No idle ack and RESET disable */
+	writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
+
+	/* SDRC Sharing register */
+	/* 32-bit SDRAM on data lane [31:0] - CS0 */
+	/* pin tri-stated = 1 */
+	writel(0x00000100, OMAP3_SDRC_REG(SHARING));
+
+	/* ----- SDRC Registers Configuration --------- */
+	/* SDRC_MCFG0 register */
+	writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
+
+	/* SDRC_RFR_CTRL0 register */
+	writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
+
+	/* SDRC_ACTIM_CTRLA0 register */
+	writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
+
+	/* SDRC_ACTIM_CTRLB0 register */
+	writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
+
+	/* Disble Power Down of CKE due to 1 CKE on combo part */
+	writel(0x00000081, OMAP3_SDRC_REG(POWER));
+
+	/* SDRC_MANUAL command register */
+	/* NOP command */
+	writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
+	/* Precharge command */
+	writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+	/* Auto-refresh command */
+	writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
+
+	/* SDRC MR0 register Burst length=4 */
+	writel(0x00000032, OMAP3_SDRC_REG(MR_0));
+
+	/* SDRC DLLA control register */
+	writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
+
+	return;
+}
+
+/**
+ * @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3
+ * do not have alternate modes. We don't program these pins.
+ *
+ * See @ref MUX_VAL for description of the muxing mode.
+ *
+ * @return void
+ */
+static void mux_config(void)
+{
+	/*
+	 * SDRC
+	 * - SDRC_D0-SDRC_D31: Default MUX mode is mode0.
+	 */
+
+	/*
+	 * GPMC
+	 * - GPMC_D0-GPMC_D7: Default MUX mode is mode0.
+	 * - GPMC_NADV_ALE: Default MUX mode is mode0.
+	 * - GPMC_NOE: Default MUX mode is mode0.
+	 * - GPMC_NWE: Default MUX mode is mode0.
+	 * - GPMC_WAIT0: Default MUX mode is mode0.
+	 */
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0));
+
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0));
+
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
+
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0));
+
+	/*
+	 * Serial Interface
+	 */
+#if defined(CONFIG_OMAP3EVM_UART1)
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0));
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0));
+#elif defined(CONFIG_OMAP3EVM_UART3)
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
+#endif
+}
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int omap3_evm_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	omap3_core_init();
+
+	mux_config();
+
+	/* Dont reconfigure SDRAM while running in SDRAM! */
+	if (!in_sdram)
+		sdrc_init();
+
+	return 0;
+}
+pure_initcall(omap3_evm_board_init);

From 75536f898b3c71cc0ce81e7b060cdf6f3513f454 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue, 29 Jan 2013 08:52:40 +0100
Subject: [PATCH 13/16] ARM am33xx beaglebone: move lowlevel code to lowlevel.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/beaglebone/Makefile   |   2 +
 arch/arm/boards/beaglebone/board.c    | 240 -------------------------
 arch/arm/boards/beaglebone/lowlevel.c | 248 ++++++++++++++++++++++++++
 3 files changed, 250 insertions(+), 240 deletions(-)
 create mode 100644 arch/arm/boards/beaglebone/lowlevel.c

diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile
index dcfc2937d..88c223aa6 100644
--- a/arch/arm/boards/beaglebone/Makefile
+++ b/arch/arm/boards/beaglebone/Makefile
@@ -1 +1,3 @@
 obj-y += board.o
+obj-y += lowlevel.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index f9ac7a469..6eb2c0abd 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -48,246 +48,6 @@
 #include <mach/am33xx-mux.h>
 #include <mach/wdt.h>
 
-/* UART Defines */
-#define UART_SYSCFG_OFFSET  (0x54)
-#define UART_SYSSTS_OFFSET  (0x58)
-
-#define UART_RESET      (0x1 << 1)
-#define UART_CLK_RUNNING_MASK   0x1
-#define UART_SMART_IDLE_EN  (0x1 << 0x3)
-
-/* AM335X EMIF Register values */
-#define EMIF_SDMGT		0x80000000
-#define EMIF_SDRAM		0x00004650
-#define EMIF_PHYCFG		0x2
-#define DDR_PHY_RESET		(0x1 << 10)
-#define DDR_FUNCTIONAL_MODE_EN	0x1
-#define DDR_PHY_READY		(0x1 << 2)
-#define	VTP_CTRL_READY		(0x1 << 5)
-#define VTP_CTRL_ENABLE		(0x1 << 6)
-#define VTP_CTRL_LOCK_EN	(0x1 << 4)
-#define VTP_CTRL_START_EN	(0x1)
-#define DDR2_RATIO		0x80	/* for mDDR */
-#define CMD_FORCE		0x00	/* common #def */
-#define CMD_DELAY		0x00
-
-#define EMIF_READ_LATENCY	0x05
-#define EMIF_TIM1		0x0666B3D6
-#define EMIF_TIM2		0x143731DA
-#define	EMIF_TIM3		0x00000347
-#define EMIF_SDCFG		0x43805332
-#define EMIF_SDREF		0x0000081a
-#define DDR2_DLL_LOCK_DIFF	0x0
-#define DDR2_RD_DQS		0x12
-#define DDR2_PHY_FIFO_WE	0x80
-
-#define	DDR2_INVERT_CLKOUT	0x00
-#define	DDR2_WR_DQS		0x00
-#define	DDR2_PHY_WRLVL		0x00
-#define	DDR2_PHY_GATELVL	0x00
-#define	DDR2_PHY_WR_DATA	0x40
-#define	PHY_RANK0_DELAY		0x01
-#define PHY_DLL_LOCK_DIFF	0x0
-#define DDR_IOCTRL_VALUE	0x18B
-
-static void beaglebone_data_macro_config(int dataMacroNum)
-{
-	u32 BaseAddrOffset = 0x00;;
-
-	if (dataMacroNum == 1)
-		BaseAddrOffset = 0xA4;
-
-	__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-		|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
-		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_RD_DQS>>2,
-		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-		|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
-		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_WR_DQS>>2,
-		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-		|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
-		(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_PHY_WRLVL>>2,
-		(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-		|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
-		(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_PHY_GATELVL>>2,
-		(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-		|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
-		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_PHY_FIFO_WE>>2,
-		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-		|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
-		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
-	__raw_writel(DDR2_PHY_WR_DATA>>2,
-		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(PHY_DLL_LOCK_DIFF,
-		(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
-}
-
-static void beaglebone_cmd_macro_config(void)
-{
-	__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
-	__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
-	__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
-	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
-	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
-
-	__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
-	__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
-	__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
-	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
-	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
-
-	__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
-	__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
-	__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
-	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
-	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
-}
-
-static void beaglebone_config_vtp(void)
-{
-	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
-		AM33XX_VTP0_CTRL_REG);
-	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
-		AM33XX_VTP0_CTRL_REG);
-	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
-		AM33XX_VTP0_CTRL_REG);
-
-	/* Poll for READY */
-	while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
-}
-
-static void beaglebone_config_emif_ddr2(void)
-{
-	u32 i;
-
-	/*Program EMIF0 CFG Registers*/
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
-
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-
-	/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
-	__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
-	for (i = 0; i < 5000; i++) {
-
-	}
-
-	/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
-	__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-}
-
-static void beaglebone_config_ddr(void)
-{
-	enable_ddr_clocks();
-
-	beaglebone_config_vtp();
-
-	beaglebone_cmd_macro_config();
-	beaglebone_data_macro_config(0);
-	beaglebone_data_macro_config(1);
-
-	__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
-	__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
-
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
-	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
-
-	__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
-	__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
-
-	beaglebone_config_emif_ddr2();
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void beaglebone_sram_init(void)
-{
-	u32 regVal, uart_base;
-
-	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	beaglebone_config_ddr();
-
-	/* UART softreset */
-	uart_base = AM33XX_UART0_BASE;
-
-	regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
-	regVal |= UART_RESET;
-	__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
-	while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
-
-	/* Disable smart idle */
-	regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
-	regVal |= UART_SMART_IDLE_EN;
-	__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
-}
-
-
-/**
- * @brief The basic entry point for board initialization.
- *
- * This is called as part of machine init (after arch init).
- * This is again called with stack in SRAM, so not too many
- * constructs possible here.
- *
- * @return void
- */
-static int beaglebone_board_init(void)
-{
-	int in_sdram = running_in_sdram();
-
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
-	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
-
-	/* Dont reconfigure SDRAM while running in SDRAM! */
-	if (!in_sdram)
-		beaglebone_sram_init();
-
-	/* Enable pin mux */
-	enable_uart0_pin_mux();
-
-	return 0;
-}
-pure_initcall(beaglebone_board_init);
-
-/******************** Board Run Time *******************/
-
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
 
 /**
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
new file mode 100644
index 000000000..d446e8d48
--- /dev/null
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -0,0 +1,248 @@
+#include <init.h>
+#include <sizes.h>
+#include <io.h>
+#include <mach/am33xx-silicon.h>
+#include <mach/am33xx-clock.h>
+#include <mach/sdrc.h>
+#include <mach/sys_info.h>
+#include <mach/syslib.h>
+#include <mach/am33xx-mux.h>
+#include <mach/wdt.h>
+
+/* UART Defines */
+#define UART_SYSCFG_OFFSET  (0x54)
+#define UART_SYSSTS_OFFSET  (0x58)
+
+#define UART_RESET      (0x1 << 1)
+#define UART_CLK_RUNNING_MASK   0x1
+#define UART_SMART_IDLE_EN  (0x1 << 0x3)
+
+/* AM335X EMIF Register values */
+#define EMIF_SDMGT		0x80000000
+#define EMIF_SDRAM		0x00004650
+#define EMIF_PHYCFG		0x2
+#define DDR_PHY_RESET		(0x1 << 10)
+#define DDR_FUNCTIONAL_MODE_EN	0x1
+#define DDR_PHY_READY		(0x1 << 2)
+#define	VTP_CTRL_READY		(0x1 << 5)
+#define VTP_CTRL_ENABLE		(0x1 << 6)
+#define VTP_CTRL_LOCK_EN	(0x1 << 4)
+#define VTP_CTRL_START_EN	(0x1)
+#define DDR2_RATIO		0x80	/* for mDDR */
+#define CMD_FORCE		0x00	/* common #def */
+#define CMD_DELAY		0x00
+
+#define EMIF_READ_LATENCY	0x05
+#define EMIF_TIM1		0x0666B3D6
+#define EMIF_TIM2		0x143731DA
+#define	EMIF_TIM3		0x00000347
+#define EMIF_SDCFG		0x43805332
+#define EMIF_SDREF		0x0000081a
+#define DDR2_DLL_LOCK_DIFF	0x0
+#define DDR2_RD_DQS		0x12
+#define DDR2_PHY_FIFO_WE	0x80
+
+#define	DDR2_INVERT_CLKOUT	0x00
+#define	DDR2_WR_DQS		0x00
+#define	DDR2_PHY_WRLVL		0x00
+#define	DDR2_PHY_GATELVL	0x00
+#define	DDR2_PHY_WR_DATA	0x40
+#define	PHY_RANK0_DELAY		0x01
+#define PHY_DLL_LOCK_DIFF	0x0
+#define DDR_IOCTRL_VALUE	0x18B
+
+static void beaglebone_data_macro_config(int dataMacroNum)
+{
+	u32 BaseAddrOffset = 0x00;;
+
+	if (dataMacroNum == 1)
+		BaseAddrOffset = 0xA4;
+
+	__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+		|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_RD_DQS>>2,
+		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+		|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_WR_DQS>>2,
+		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+		|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+		(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_PHY_WRLVL>>2,
+		(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+		|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+		(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_PHY_GATELVL>>2,
+		(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+		|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_PHY_FIFO_WE>>2,
+		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
+	__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+		|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
+	__raw_writel(DDR2_PHY_WR_DATA>>2,
+		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
+	__raw_writel(PHY_DLL_LOCK_DIFF,
+		(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
+}
+
+static void beaglebone_cmd_macro_config(void)
+{
+	__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
+	__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
+	__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
+	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
+	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
+
+	__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
+	__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
+	__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
+	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
+	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
+
+	__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
+	__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
+	__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
+	__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
+	__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
+}
+
+static void beaglebone_config_vtp(void)
+{
+	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
+		AM33XX_VTP0_CTRL_REG);
+	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
+		AM33XX_VTP0_CTRL_REG);
+	__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
+		AM33XX_VTP0_CTRL_REG);
+
+	/* Poll for READY */
+	while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
+}
+
+static void beaglebone_config_emif_ddr2(void)
+{
+	u32 i;
+
+	/*Program EMIF0 CFG Registers*/
+	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
+	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
+	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
+	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
+	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
+	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
+	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
+	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
+	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
+
+	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+
+	/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+	__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+	for (i = 0; i < 5000; i++) {
+
+	}
+
+	/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
+	__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
+	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
+	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+
+	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+}
+
+static void beaglebone_config_ddr(void)
+{
+	enable_ddr_clocks();
+
+	beaglebone_config_vtp();
+
+	beaglebone_cmd_macro_config();
+	beaglebone_data_macro_config(0);
+	beaglebone_data_macro_config(1);
+
+	__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
+	__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
+
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
+	__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
+
+	__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
+	__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
+
+	beaglebone_config_emif_ddr2();
+}
+
+/*
+ * early system init of muxing and clocks.
+ */
+void beaglebone_sram_init(void)
+{
+	u32 regVal, uart_base;
+
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	beaglebone_config_ddr();
+
+	/* UART softreset */
+	uart_base = AM33XX_UART0_BASE;
+
+	regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
+	regVal |= UART_RESET;
+	__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
+	while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
+
+	/* Disable smart idle */
+	regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
+	regVal |= UART_SMART_IDLE_EN;
+	__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
+}
+
+
+/**
+ * @brief The basic entry point for board initialization.
+ *
+ * This is called as part of machine init (after arch init).
+ * This is again called with stack in SRAM, so not too many
+ * constructs possible here.
+ *
+ * @return void
+ */
+static int beaglebone_board_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	/* WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
+	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+	__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
+	while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
+
+	/* Dont reconfigure SDRAM while running in SDRAM! */
+	if (!in_sdram)
+		beaglebone_sram_init();
+
+	/* Enable pin mux */
+	enable_uart0_pin_mux();
+
+	return 0;
+}
+pure_initcall(beaglebone_board_init);

From dc3400f53f3a6edd3de29be055de970871fb9562 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue, 29 Jan 2013 09:06:14 +0100
Subject: [PATCH 14/16] ARM omap3 beagle: Compile xload defconfig in Thumb2
 mode

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/configs/omap3530_beagle_xload_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/configs/omap3530_beagle_xload_defconfig b/arch/arm/configs/omap3530_beagle_xload_defconfig
index d951b1c98..383ea2895 100644
--- a/arch/arm/configs/omap3530_beagle_xload_defconfig
+++ b/arch/arm/configs/omap3530_beagle_xload_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARCH_OMAP=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_MACH_BEAGLE=y
-CONFIG_AEABI=y
+CONFIG_THUMB2_BAREBOX=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 # CONFIG_ARM_EXCEPTIONS is not set
 CONFIG_TEXT_BASE=0x40200000

From 7eed7b91c3e37a73b473adab014f2010622e8dbc Mon Sep 17 00:00:00 2001
From: Antony Pavlov <antonynpavlov@gmail.com>
Date: Thu, 24 Jan 2013 22:55:40 +0400
Subject: [PATCH 15/16] ARM OMAP: use SZ_*M constants in RAM device register
 functions

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/beaglebone/board.c  | 2 +-
 arch/arm/boards/omap343xdsp/board.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c
index 0da61e2de..cb16a3f40 100644
--- a/arch/arm/boards/beaglebone/board.c
+++ b/arch/arm/boards/beaglebone/board.c
@@ -71,7 +71,7 @@ console_initcall(beaglebone_console_init);
 
 static int beaglebone_mem_init(void)
 {
-	omap_add_ram0(256 * 1024 * 1024);
+	omap_add_ram0(SZ_256M);
 
 	return 0;
 }
diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c
index 215fe02ef..654d8c082 100644
--- a/arch/arm/boards/omap343xdsp/board.c
+++ b/arch/arm/boards/omap343xdsp/board.c
@@ -73,7 +73,7 @@ console_initcall(sdp3430_console_init);
 
 static int sdp3430_mem_init(void)
 {
-	omap_add_ram0(128 * 1024 * 1024);
+	omap_add_ram0(SZ_128M);
 
 	return 0;
 }

From 5862bd4faff8b9b3343c8ab9454b0095aee7eb49 Mon Sep 17 00:00:00 2001
From: Jan Weitzel <j.weitzel@phytec.de>
Date: Wed, 30 Jan 2013 08:52:53 +0100
Subject: [PATCH 16/16] pcm049: clean up defconfig

add BAREBOX_MAX_IMAGE_SIZE and rebuild defconfig with savedefconfig

Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/configs/pcm049_defconfig       | 19 +++++++++++--------
 arch/arm/configs/pcm049_xload_defconfig |  3 ++-
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/arm/configs/pcm049_defconfig b/arch/arm/configs/pcm049_defconfig
index adb600fce..19df95a3c 100644
--- a/arch/arm/configs/pcm049_defconfig
+++ b/arch/arm/configs/pcm049_defconfig
@@ -1,13 +1,12 @@
 CONFIG_ARCH_OMAP=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x80000
 CONFIG_ARCH_OMAP4=y
 CONFIG_MACH_PCM049=y
 CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
 CONFIG_TEXT_BASE=0x8f000000
 CONFIG_MALLOC_SIZE=0x2000000
-CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="barebox> "
 CONFIG_LONGHELP=y
@@ -21,11 +20,12 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm049/env"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_AUTOMOUNT=y
+CONFIG_CMD_TFTP=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_LOADB=y
 CONFIG_CMD_IOMEM=y
@@ -36,7 +36,6 @@ CONFIG_CMD_BOOTM_INITRD=y
 CONFIG_CMD_BOOTM_OFTREE=y
 CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
 CONFIG_CMD_UIMAGE=y
-# CONFIG_CMD_BOOTZ is not set
 # CONFIG_CMD_BOOTU is not set
 CONFIG_CMD_RESET=y
 CONFIG_CMD_GO=y
@@ -45,25 +44,29 @@ CONFIG_CMD_PARTITION=y
 CONFIG_CMD_MAGICVAR=y
 CONFIG_CMD_MAGICVAR_HELP=y
 CONFIG_CMD_GPIO=y
-CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
 CONFIG_NET=y
 CONFIG_NET_DHCP=y
 CONFIG_NET_NFS=y
 CONFIG_NET_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_FS_TFTP=y
 CONFIG_DRIVER_SERIAL_NS16550=y
 CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+CONFIG_SMSC_PHY=y
 CONFIG_DRIVER_NET_SMC911X=y
 # CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_OMAP=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_OMAP_GPMC=y
 CONFIG_UBI=y
+CONFIG_USB=y
 CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
 CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_I2C_TWL6030=y
+CONFIG_FS_TFTP=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
 CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/pcm049_xload_defconfig b/arch/arm/configs/pcm049_xload_defconfig
index b6d3a7a37..189c0400b 100644
--- a/arch/arm/configs/pcm049_xload_defconfig
+++ b/arch/arm/configs/pcm049_xload_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARCH_OMAP=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000
 CONFIG_ARCH_OMAP4=y
 CONFIG_OMAP_BUILD_IFT=y
 CONFIG_MACH_PCM049=y
-CONFIG_AEABI=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 # CONFIG_ARM_EXCEPTIONS is not set
+# CONFIG_MEMINFO is not set
 CONFIG_MMU=y
 CONFIG_TEXT_BASE=0x40300000
 CONFIG_MEMORY_LAYOUT_FIXED=y