pinctrl: Add pinctrl driver for i.MX1/21/27
This turns the legacy iomux-v1 support into a full pinctrl driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
c5b7986089
commit
d25cba0090
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@ -8,6 +8,7 @@ config PINCTRL
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support but instead provide their own SoC specific APIs
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config PINCTRL_IMX_IOMUX_V1
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select PINCTRL if OFDEVICE
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bool
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help
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This iomux controller is found on i.MX1,21,27.
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@ -1,5 +1,8 @@
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#include <common.h>
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#include <io.h>
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#include <init.h>
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#include <malloc.h>
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#include <pinctrl.h>
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#include <mach/iomux-v1.h>
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/*
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@ -29,6 +32,11 @@
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static void __iomem *iomuxv1_base;
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struct imx_iomux_v1 {
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void __iomem *base;
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struct pinctrl_device pinctrl;
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};
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void imx_gpio_mode(int gpio_mode)
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{
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unsigned int pin = gpio_mode & GPIO_PIN_MASK;
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@ -114,3 +122,193 @@ void imx_iomuxv1_init(void __iomem *base)
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{
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iomuxv1_base = base;
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}
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/*
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* MUX_ID format defines
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*/
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#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
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#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
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#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
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#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
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#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
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#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
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#define MX1_PORT_STRIDE 0x100
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/*
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* IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
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* control register are seperated into function, output configuration, input
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* configuration A, input configuration B, GPIO in use and data direction.
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*
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* Those controls that are represented by 1 bit have a direct mapping between
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* bit position and pin id. If they are represented by 2 bit, the lower 16 pins
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* are in the first register and the upper 16 pins in the second (next)
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* register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
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*/
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/*
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* Calculates the register offset from a pin_id
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*/
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static void __iomem *imx1_mem(struct imx_iomux_v1 *iomux, unsigned int pin_id)
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{
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unsigned int port = pin_id / 32;
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return iomux->base + port * MX1_PORT_STRIDE;
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}
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/*
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* Write to a register with 2 bits per pin. The function will automatically
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* use the next register if the pin is managed in the second register.
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*/
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static void imx1_write_2bit(struct imx_iomux_v1 *iomux, unsigned int pin_id,
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u32 value, u32 reg_offset)
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{
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void __iomem *reg = imx1_mem(iomux, pin_id) + reg_offset;
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int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
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int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
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u32 old_val;
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u32 new_val;
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dev_dbg(iomux->pinctrl.dev, "write: register 0x%p offset %d value 0x%x\n",
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reg, offset, value);
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/* Use the next register if the pin's port pin number is >=16 */
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if (pin_id % 32 >= 16)
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reg += 0x04;
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/* Get current state of pins */
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old_val = readl(reg);
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old_val &= mask;
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new_val = value & 0x3; /* Make sure value is really 2 bit */
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new_val <<= offset;
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new_val |= old_val;/* Set new state for pin_id */
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writel(new_val, reg);
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}
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static void imx1_write_bit(struct imx_iomux_v1 *iomux, unsigned int pin_id,
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u32 value, u32 reg_offset)
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{
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void __iomem *reg = imx1_mem(iomux, pin_id) + reg_offset;
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int offset = pin_id % 32;
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int mask = ~BIT_MASK(offset);
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u32 old_val;
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u32 new_val;
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/* Get current state of pins */
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old_val = readl(reg);
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old_val &= mask;
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new_val = value & 0x1; /* Make sure value is really 1 bit */
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new_val <<= offset;
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new_val |= old_val;/* Set new state for pin_id */
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writel(new_val, reg);
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}
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static int imx_iomux_v1_set_state(struct pinctrl_device *pdev, struct device_node *np)
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{
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struct imx_iomux_v1 *iomux = container_of(pdev, struct imx_iomux_v1, pinctrl);
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const __be32 *list;
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int npins, size, i;
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dev_dbg(iomux->pinctrl.dev, "set state: %s\n", np->full_name);
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list = of_get_property(np, "fsl,pins", &size);
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if (!list)
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return -EINVAL;
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npins = size / 12;
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for (i = 0; i < npins; i++) {
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unsigned int pin_id = be32_to_cpu(*list++);
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unsigned int mux = be32_to_cpu(*list++);
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unsigned int config = be32_to_cpu(*list++);
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unsigned int afunction = MX1_MUX_FUNCTION(mux);
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unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
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unsigned int direction = MX1_MUX_DIR(mux);
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unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
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unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
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unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
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dev_dbg(pdev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
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np->full_name, pin_id, afunction, gpio_in_use,
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direction, gpio_oconf, gpio_iconfa,
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gpio_iconfb);
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imx1_write_bit(iomux, pin_id, gpio_in_use, GIUS);
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imx1_write_bit(iomux, pin_id, direction, DDIR);
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if (gpio_in_use) {
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imx1_write_2bit(iomux, pin_id, gpio_oconf, OCR1);
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imx1_write_2bit(iomux, pin_id, gpio_iconfa, ICONFA1);
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imx1_write_2bit(iomux, pin_id, gpio_iconfb, ICONFB1);
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} else {
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imx1_write_bit(iomux, pin_id, afunction, GPR);
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}
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imx1_write_bit(iomux, pin_id, config & 0x01, PUEN);
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}
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return 0;
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}
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static struct pinctrl_ops imx_iomux_v1_ops = {
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.set_state = imx_iomux_v1_set_state,
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};
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static int imx_pinctrl_dt(struct device_d *dev, void __iomem *base)
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{
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struct imx_iomux_v1 *iomux;
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int ret;
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iomux = xzalloc(sizeof(*iomux));
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iomux->base = base;
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iomux->pinctrl.dev = dev;
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iomux->pinctrl.ops = &imx_iomux_v1_ops;
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ret = pinctrl_register(&iomux->pinctrl);
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if (ret)
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free(iomux);
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return ret;
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}
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static int imx_iomux_v1_probe(struct device_d *dev)
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{
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int ret = 0;
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if (iomuxv1_base)
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return -EBUSY;
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iomuxv1_base = dev_get_mem_region(dev, 0);
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ret = of_platform_populate(dev->device_node, NULL, NULL);
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if (IS_ENABLED(CONFIG_PINCTRL) && dev->device_node)
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ret = imx_pinctrl_dt(dev, iomuxv1_base);
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return ret;
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}
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static __maybe_unused struct of_device_id imx_iomux_v1_dt_ids[] = {
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{
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.compatible = "fsl,imx27-iomuxc",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d imx_iomux_v1_driver = {
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.name = "imx-iomuxv1",
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.probe = imx_iomux_v1_probe,
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.of_compatible = DRV_OF_COMPAT(imx_iomux_v1_dt_ids),
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};
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static int imx_iomux_v1_init(void)
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{
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return platform_driver_register(&imx_iomux_v1_driver);
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}
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postcore_initcall(imx_iomux_v1_init);
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