ARM: make exception handling optional

On several boards without MMU support the vectors cannot be mapped
to 0x0 and exception support is nonfunctional anyway, so make this
configurable.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arch/arm/Kconfig

@@ -120,9 +120,14 @@ config ARM_OPTIMZED_STRING_FUNCTIONS
 	  These functions work much faster than the normal versions but
 	  increase your binary size.
 
+config ARM_EXCEPTIONS
+	bool "enable arm exception handling support"
+	default y
+
 config ARM_UNWIND
 	bool "enable stack unwinding support"
 	depends on AEABI
+	depends on ARM_EXCEPTIONS
 	help
 	  This option enables stack unwinding support in barebox
 	  using the information automatically generated by the

arch/arm/cpu/Makefile

@@ -1,6 +1,6 @@
 obj-y += cpu.o
-obj-y += exceptions.o
-obj-y += interrupts.o
+obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o
+obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
 obj-y += start.o
 
 #

arch/arm/cpu/start.c

@@ -31,6 +31,7 @@ void __naked __section(.text_entry) exception_vectors(void)
 {
 	__asm__ __volatile__ (
 		"b reset\n"				/* reset */
+#ifdef CONFIG_ARM_EXCEPTIONS
 		"ldr pc, =undefined_instruction\n"	/* undefined instruction */
 		"ldr pc, =software_interrupt\n"		/* software interrupt (SWI) */
 		"ldr pc, =prefetch_abort\n"		/* prefetch abort */
@@ -38,6 +39,15 @@ void __naked __section(.text_entry) exception_vectors(void)
 		"ldr pc, =not_used\n"			/* (reserved) */
 		"ldr pc, =irq\n"			/* irq (interrupt) */
 		"ldr pc, =fiq\n"			/* fiq (fast interrupt) */
+#else
+		"1: bne 1b\n"				/* undefined instruction */
+		"1: bne 1b\n"				/* software interrupt (SWI) */
+		"1: bne 1b\n"				/* prefetch abort */
+		"1: bne 1b\n"				/* data abort */
+		"1: bne 1b\n"				/* (reserved) */
+		"1: bne 1b\n"				/* irq (interrupt) */
+		"1: bne 1b\n"				/* fiq (fast interrupt) */
+#endif
 	);
 }