MIPS: add common MIPS stuff
Add start.S, CP0 clocksource, Makefile, linker script and memory layout function. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Antony Pavlov
Sascha Hauer
parent
9b64050669
commit
d3f66272bf
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@ -0,0 +1,184 @@
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#
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#
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#
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config MIPS
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bool
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select HAS_KALLSYMS
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select HAVE_CONFIGURABLE_MEMORY_LAYOUT
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select HAVE_CONFIGURABLE_TEXT_BASE
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default y
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config SYS_SUPPORTS_BIG_ENDIAN
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bool
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config SYS_SUPPORTS_LITTLE_ENDIAN
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bool
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config CSRC_R4K_LIB
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bool
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config GENERIC_LINKER_SCRIPT
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bool
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default y
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#
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# Endianess selection. Sufficiently obscure so many users don't know what to
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# answer,so we try hard to limit the available choices. Also the use of a
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# choice statement should be more obvious to the user.
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#
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choice
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prompt "Endianess selection"
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help
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Some MIPS machines can be configured for either little or big endian
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byte order. These modes require different barebox images.
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In general there is one preferred byteorder for a
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particular system but some systems are just as commonly used in the
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one or the other endianness.
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config CPU_BIG_ENDIAN
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bool "Big endian"
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depends on SYS_SUPPORTS_BIG_ENDIAN
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config CPU_LITTLE_ENDIAN
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bool "Little endian"
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depends on SYS_SUPPORTS_LITTLE_ENDIAN
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help
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endchoice
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menu "CPU selection"
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choice
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prompt "CPU type"
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default CPU_MIPS32_R2
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config CPU_MIPS32_R1
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bool "MIPS32 Release 1"
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depends on SYS_HAS_CPU_MIPS32_R1
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select CPU_SUPPORTS_32BIT_KERNEL
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help
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Choose this option to build a barebox for release 1 or later of the
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MIPS32 architecture. Most modern embedded systems with a 32-bit
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MIPS processor are based on a MIPS32 processor. If you know the
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specific type of processor in your system, choose those that one
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otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
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Release 2 of the MIPS32 architecture is available since several
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years so chances are you even have a MIPS32 Release 2 processor
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in which case you should choose CPU_MIPS32_R2 instead for better
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performance.
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config CPU_MIPS32_R2
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bool "MIPS32 Release 2"
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depends on SYS_HAS_CPU_MIPS32_R2
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select CPU_SUPPORTS_32BIT_KERNEL
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help
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Choose this option to build a barebox for release 2 or later of the
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MIPS32 architecture. Most modern embedded systems with a 32-bit
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MIPS processor are based on a MIPS32 processor. If you know the
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specific type of processor in your system, choose those that one
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otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
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config CPU_MIPS64_R1
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bool "MIPS64 Release 1"
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depends on SYS_HAS_CPU_MIPS64_R1
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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help
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Choose this option to build a barebox for release 1 or later of the
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MIPS64 architecture. Many modern embedded systems with a 64-bit
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MIPS processor are based on a MIPS64 processor. If you know the
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specific type of processor in your system, choose those that one
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otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
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Release 2 of the MIPS64 architecture is available since several
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years so chances are you even have a MIPS64 Release 2 processor
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in which case you should choose CPU_MIPS64_R2 instead for better
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performance.
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config CPU_MIPS64_R2
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bool "MIPS64 Release 2"
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depends on SYS_HAS_CPU_MIPS64_R2
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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help
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Choose this option to build a barebox for release 2 or later of the
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MIPS64 architecture. Many modern embedded systems with a 64-bit
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MIPS processor are based on a MIPS64 processor. If you know the
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specific type of processor in your system, choose those that one
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otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
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endchoice
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config SYS_HAS_CPU_MIPS32_R1
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bool
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config SYS_HAS_CPU_MIPS32_R2
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bool
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config SYS_HAS_CPU_MIPS64_R1
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bool
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config SYS_HAS_CPU_MIPS64_R2
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bool
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#
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# These two indicate any level of the MIPS32 and MIPS64 architecture
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#
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config CPU_MIPS32
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bool
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
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config CPU_MIPS64
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bool
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default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
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#
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# These two indicate the revision of the architecture, either Release 1 or Release 2
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#
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config CPU_MIPSR1
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bool
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default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
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config CPU_MIPSR2
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bool
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default y if CPU_MIPS32_R2 || CPU_MIPS64_R2
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config SYS_SUPPORTS_32BIT_KERNEL
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bool
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config SYS_SUPPORTS_64BIT_KERNEL
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bool
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config CPU_SUPPORTS_32BIT_KERNEL
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bool
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config CPU_SUPPORTS_64BIT_KERNEL
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bool
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endmenu
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choice
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prompt "Barebox code model"
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help
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You should only select this option if you have a workload that
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actually benefits from 64-bit processing or if your machine has
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large memory. You will only be presented a single option in this
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menu if your system does not support both 32-bit and 64-bit modes.
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config 32BIT
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bool "32-bit barebox"
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depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
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help
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Select this option if you want to build a 32-bit barebox.
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config 64BIT
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bool "64-bit barebox"
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depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
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help
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Select this option if you want to build a 64-bit barebox.
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endchoice
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source common/Kconfig
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source commands/Kconfig
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source net/Kconfig
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source drivers/Kconfig
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source fs/Kconfig
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source lib/Kconfig
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@ -0,0 +1,99 @@
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#
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# Select the object file format to substitute into the linker script.
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#
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ifdef CONFIG_CPU_LITTLE_ENDIAN
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32bit-emul = elf32ltsmip
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64bit-emul = elf64ltsmip
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else
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32bit-emul = elf32btsmip
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64bit-emul = elf64btsmip
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endif
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CPPFLAGS += -D__MIPS__ -fno-strict-aliasing -fno-merge-constants
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cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
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cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \
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-Wno-uninitialized -Wno-format -Wno-main
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ifdef CONFIG_32BIT
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ld-emul = $(32bit-emul)
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cflags-y += -mabi=32
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endif
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ifdef CONFIG_64BIT
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ld-emul = $(64bit-emul)
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cflags-y += -mabi=64
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endif
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undef-all += -UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__
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undef-all += -UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__
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predef-be += -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__
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predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__
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ifdef CONFIG_CPU_BIG_ENDIAN
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cflags-y += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))
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ldflags-y += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB )
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endif
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ifdef CONFIG_CPU_LITTLE_ENDIAN
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cflags-y += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
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ldflags-y += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL )
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endif
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LDFLAGS += $(ldflags-y) -m $(ld-emul)
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#
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# CPU-dependent compiler/assembler options for optimization.
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#
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cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32 -Wa,--trap
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cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap
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cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64 -Wa,--trap
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cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap
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CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
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ifndef CONFIG_MODULES
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# Add cleanup flags
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CPPFLAGS += -fdata-sections -ffunction-sections
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LDFLAGS_barebox += -static --gc-sections
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endif
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LDFLAGS_barebox += -nostdlib
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machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
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ifeq ($(KBUILD_SRC),)
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CPPFLAGS += $(patsubst %,-I%include,$(machdirs))
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else
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CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
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endif
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ifeq ($(incdir-y),)
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incdir-y := $(machine-y)
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endif
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INCDIR := arch-$(incdir-y)
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all: $(KBUILD_IMAGE)
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ifneq ($(board-y),)
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BOARD := arch/mips/boards/$(board-y)/
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else
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BOARD :=
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endif
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ifneq ($(machine-y),)
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MACH := arch/mips/mach-$(machine-y)/
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else
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MACH :=
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endif
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common-y += $(BOARD) $(MACH)
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common-y += arch/mips/lib/
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common-y += arch/mips/boot/
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CPPFLAGS += $(cflags-y)
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CFLAGS += $(cflags-y)
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lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/mips/lib/barebox.lds
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CLEAN_FILES += arch/mips/lib/barebox.lds barebox.map barebox.S
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@ -0,0 +1 @@
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obj-y += start.o
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@ -0,0 +1,143 @@
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/*
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* Startup Code for MIPS CPU
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*
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* Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
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* Used code copyrighted (C) 2009 by Shinya Kuribayashi <skuribay@pobox.com>
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*
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* This file is part of barebox.
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm.h>
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#include <asm-generic/memory_layout.h>
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/*
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* ADR macro instruction (inspired by ARM)
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*
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* ARM architecture doesn't have PC-relative jump instruction
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* like MIPS' B/BAL insns. When ARM makes PC-relative jumps,
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* it uses ADR insn. ADR is used to get a destination address
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* of 'label' against current PC. With this, ARM can safely
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* make PC-relative jumps.
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*/
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.macro ADR rd label temp
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.set push
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.set noreorder
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move \temp, ra # preserve ra beforehand
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bal _pc
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nop
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_pc: addiu \rd, ra, \label - _pc # label is assumed to be
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move ra, \temp # within pc +/- 32KB
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.set pop
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.endm
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.set noreorder
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.text
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.section ".text_bare_init"
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.align 4
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EXPORT(_start)
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/* disable watchpoints */
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mtc0 zero, CP0_WATCHLO
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mtc0 zero, CP0_WATCHHI
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/* disable interrupts */
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mfc0 k0, CP0_STATUS
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li k1, ~ST0_IE
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and k0, k1
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mtc0 k0, CP0_STATUS
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/* copy barebox to link location */
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ADR a0, _start, t1 /* a0 <- pc-relative position of _start */
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la a1, _start /* link (RAM) _start address */
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beq a0, a1, clear_bss
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nop
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la t0, _start
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la t1, __bss_start
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subu t2, t1, t0 /* t2 <- size of barebox */
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addu a2, a0, t2 /* a2 <- source end address */
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#define LONGSIZE 4
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copy_loop:
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/* copy from source address [a0] */
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lw t4, LONGSIZE * 0(a0)
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lw t5, LONGSIZE * 1(a0)
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lw t6, LONGSIZE * 2(a0)
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lw t7, LONGSIZE * 3(a0)
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/* copy fo target address [a1] */
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sw t4, LONGSIZE * 0(a1)
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sw t5, LONGSIZE * 1(a1)
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sw t6, LONGSIZE * 2(a1)
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sw t7, LONGSIZE * 3(a1)
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addi a0, LONGSIZE * 4
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subu t3, a0, a2
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blez t3, copy_loop
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addi a1, LONGSIZE * 4
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clear_bss:
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la t0, __bss_start
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sw zero, (t0)
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la t1, _end - 4
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1:
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addiu t0, LONGSIZE
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sw zero, (t0)
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bne t0, t1, 1b
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nop
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/*
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* Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006
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*
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* 11.2.2 Stack Argument Structure in o32
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* ...
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* At the point where a function is called, sp must be
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* eight-byte-aligned, matching the alignment of the largest
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* basic types -- a long long integer or a floating-point double.
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* The eight-byte alignment is not required by 32-bit MIPS integer
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* hardware, but it's essential for compatibility with CPUs with
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* 64-bit registers, and thus part of the rules. Subroutines fit
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* in with this by always adjusting the stack pointer by a multiple
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* of eight.
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* ...
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* SGI's n32 and n64 standards call for the stack to be maintained
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* with 16-byte alignment.
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*
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*/
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#if (STACK_BASE + STACK_SIZE) % 16 != 0
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#error stack pointer must be 16-byte-aligned
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#endif
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stack_setup:
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la sp, STACK_BASE + STACK_SIZE
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/* reserve four 32-bit argument slots */
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addiu sp, -16
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la v0, start_barebox
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jal v0
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nop
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/* No return */
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__error:
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b __error
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nop
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@ -0,0 +1 @@
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barebox.lds
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@ -0,0 +1,6 @@
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extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds
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obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
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obj-y += lshrdi3.o
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obj-y += ashldi3.o
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obj-y += ashrdi3.o
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obj-y += memory.o
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@ -0,0 +1,76 @@
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/*
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* Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
|
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*
|
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* This file is part of barebox.
|
||||
* See file CREDITS for list of people who contributed to this project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
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|
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#include <asm-generic/barebox.lds.h>
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|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = TEXT_BASE;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
_start = .;
|
||||
*(.text_entry*)
|
||||
_stext = .;
|
||||
_text = .;
|
||||
*(.text_bare_init*)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
PRE_IMAGE
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata*) }
|
||||
|
||||
_etext = .; /* End of text and rodata section */
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got*) }
|
||||
|
||||
. = .;
|
||||
__barebox_cmd_start = .;
|
||||
.barebox_cmd : { BAREBOX_CMDS }
|
||||
__barebox_cmd_end = .;
|
||||
|
||||
__barebox_initcalls_start = .;
|
||||
.barebox_initcalls : { INITCALLS }
|
||||
__barebox_initcalls_end = .;
|
||||
|
||||
__usymtab_start = .;
|
||||
__usymtab : { BAREBOX_SYMS }
|
||||
__usymtab_end = .;
|
||||
|
||||
__early_init_data_begin = .;
|
||||
.early_init_data : { *(.early_init_data) }
|
||||
__early_init_data_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss*) }
|
||||
__bss_end = .;
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
|
||||
*
|
||||
* This file is part of barebox.
|
||||
* See file CREDITS for list of people who contributed to this project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Clocksource based on MIPS CP0 timer
|
||||
*/
|
||||
|
||||
#include <init.h>
|
||||
#include <clock.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
static uint64_t c0_hpt_read(void)
|
||||
{
|
||||
return read_c0_count();
|
||||
}
|
||||
|
||||
static struct clocksource cs = {
|
||||
.read = c0_hpt_read,
|
||||
.mask = 0xffffffff,
|
||||
};
|
||||
|
||||
static int clocksource_init(void)
|
||||
{
|
||||
cs.mult = clocksource_hz2mult(100000000, cs.shift);
|
||||
init_clock(&cs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
core_initcall(clocksource_init);
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
|
||||
*
|
||||
* This file is part of barebox.
|
||||
* See file CREDITS for list of people who contributed to this project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <mem_malloc.h>
|
||||
#include <asm-generic/memory_layout.h>
|
||||
|
||||
static int mips_mem_malloc_init(void)
|
||||
{
|
||||
mem_malloc_init((void *)MALLOC_BASE,
|
||||
(void *)(MALLOC_BASE + MALLOC_SIZE));
|
||||
return 0;
|
||||
}
|
||||
core_initcall(mips_mem_malloc_init);
|
||||
Loading…
Reference in New Issue