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Merge branch 'pu-mx53-l2' into next

This commit is contained in:
Sascha Hauer 2011-11-09 11:13:00 +01:00
parent 03f18f3115 7c5f706f49
commit d471e8549e
1 changed files with 6 additions and 7 deletions
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13
arch/arm/mach-imx/imx53.c
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@ -85,16 +85,11 @@ int mx53_init_lowlevel(void)
u32 r;
/* ARM errata ID #468414 */
__asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
__asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
r |= (1 << 5); /* enable L1NEON bit */
r &= ~(1 << 1); /* explicitly disable L2 cache */
__asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
/* explicitly disable L2 cache */
__asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
r &= ~(1 << 1);
__asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
/* reconfigure L2 cache aux control reg */
r = 0xc0 | /* tag RAM */
0x4 | /* data RAM */
@ -104,6 +99,10 @@ int mx53_init_lowlevel(void)
__asm__ __volatile__("mcr 15, 1, %0, c9, c0, 2" : : "r"(r));
__asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
r |= 1 << 1; /* enable L2 cache */
__asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
/*
* AIPS setup - Only setup MPROTx registers.
* The PACR default values are good.