ARM i.MX: Add Garz+Fricke Vincell Board support
This adds support for the Garz+Fricke Vincell board. This has a i.MX53 Processor with 512MB of DDR3 RAM. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
d117a2d5c8
commit
d476789db6
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@ -148,6 +148,7 @@ board-$(CONFIG_MACH_CCMX51) := ccxmx51
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board-$(CONFIG_MACH_TINY210) := friendlyarm-tiny210
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board-$(CONFIG_MACH_SABRELITE) := freescale-mx6-sabrelite
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board-$(CONFIG_MACH_TX53) := karo-tx53
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board-$(CONFIG_MACH_GUF_VINCELL) := guf-vincell
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machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
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@ -0,0 +1,3 @@
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obj-y += board.o
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obj-y += flash_header.o lowlevel.o
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pbl-y += flash_header.o lowlevel.o
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@ -0,0 +1,322 @@
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <environment.h>
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#include <fcntl.h>
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#include <fec.h>
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#include <fs.h>
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#include <init.h>
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#include <nand.h>
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#include <net.h>
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#include <partition.h>
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#include <sizes.h>
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#include <bbu.h>
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#include <gpio.h>
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#include <io.h>
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#include <i2c/i2c.h>
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#include <linux/clk.h>
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#include <generated/mach-types.h>
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#include <mach/imx53-regs.h>
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#include <mach/iomux-mx53.h>
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#include <mach/devices-imx53.h>
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#include <mach/generic.h>
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#include <mach/imx-nand.h>
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#include <mach/iim.h>
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#include <mach/imx-nand.h>
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#include <mach/bbu.h>
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#include <mach/imx-flash-header.h>
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#include <mach/imx5.h>
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#include <asm/armlinux.h>
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#include <asm/mmu.h>
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static struct fec_platform_data fec_info = {
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.xcv_type = RMII,
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};
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static iomux_v3_cfg_t vincell_pads[] = {
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MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD,
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MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC,
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MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD,
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MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS,
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MX53_PAD_GPIO_8__CAN1_RXCAN,
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MX53_PAD_GPIO_7__CAN1_TXCAN,
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MX53_PAD_KEY_ROW4__CAN2_RXCAN,
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MX53_PAD_KEY_COL4__CAN2_TXCAN,
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MX53_PAD_GPIO_3__CCM_CLKO2,
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MX53_PAD_KEY_COL1__ECSPI1_MISO,
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MX53_PAD_KEY_ROW0__ECSPI1_MOSI,
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MX53_PAD_GPIO_19__ECSPI1_RDY,
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MX53_PAD_KEY_COL0__ECSPI1_SCLK,
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MX53_PAD_KEY_ROW1__GPIO4_9, /* ECSPI1_SS0 */
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MX53_PAD_KEY_COL2__GPIO4_10, /* ECSPI1_SS1 */
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MX53_PAD_KEY_ROW2__GPIO4_11, /* ECSPI1_SS2 */
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MX53_PAD_KEY_COL3__GPIO4_12, /* ECSPI1_SS3 */
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MX53_PAD_CSI0_DAT10__ECSPI2_MISO,
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MX53_PAD_EIM_CS1__ECSPI2_MOSI,
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MX53_PAD_EIM_A25__ECSPI2_RDY,
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MX53_PAD_DISP0_DAT19__ECSPI2_SCLK,
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MX53_PAD_DISP0_DAT18__GPIO5_12, /* ECSPI2_SS0 */
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MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
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MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
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MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
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MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
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MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
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MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
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MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
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MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
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MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8,
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MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9,
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MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10,
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MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11,
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MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12,
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MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13,
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MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14,
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MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15,
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MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
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MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
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MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
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MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
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MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2,
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MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3,
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MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
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MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
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MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
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MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
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MX53_PAD_EIM_A16__EMI_WEIM_A_16,
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MX53_PAD_EIM_A17__EMI_WEIM_A_17,
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MX53_PAD_EIM_A18__EMI_WEIM_A_18,
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MX53_PAD_EIM_A19__EMI_WEIM_A_19,
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MX53_PAD_EIM_A20__EMI_WEIM_A_20,
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MX53_PAD_EIM_CS0__EMI_WEIM_CS_0,
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MX53_PAD_EIM_D16__EMI_WEIM_D_16,
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MX53_PAD_EIM_D17__EMI_WEIM_D_17,
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MX53_PAD_EIM_D18__EMI_WEIM_D_18,
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MX53_PAD_EIM_D19__EMI_WEIM_D_19,
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MX53_PAD_EIM_D20__EMI_WEIM_D_20,
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MX53_PAD_EIM_D21__EMI_WEIM_D_21,
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MX53_PAD_EIM_D22__EMI_WEIM_D_22,
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MX53_PAD_EIM_D23__EMI_WEIM_D_23,
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MX53_PAD_EIM_D24__EMI_WEIM_D_24,
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MX53_PAD_EIM_D25__EMI_WEIM_D_25,
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MX53_PAD_EIM_D26__EMI_WEIM_D_26,
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MX53_PAD_EIM_D27__EMI_WEIM_D_27,
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MX53_PAD_EIM_D28__EMI_WEIM_D_28,
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MX53_PAD_EIM_D29__EMI_WEIM_D_29,
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MX53_PAD_EIM_D30__EMI_WEIM_D_30,
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MX53_PAD_EIM_D31__EMI_WEIM_D_31,
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MX53_PAD_EIM_EB0__EMI_WEIM_EB_0,
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MX53_PAD_EIM_EB1__EMI_WEIM_EB_1,
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MX53_PAD_EIM_OE__EMI_WEIM_OE,
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MX53_PAD_EIM_RW__EMI_WEIM_RW,
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MX53_PAD_SD1_CLK__ESDHC1_CLK,
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MX53_PAD_SD1_CMD__ESDHC1_CMD,
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
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MX53_PAD_DI0_PIN4__ESDHC1_WP,
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MX53_PAD_FEC_MDC__FEC_MDC,
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MX53_PAD_FEC_MDIO__FEC_MDIO,
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MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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MX53_PAD_FEC_TXD0__FEC_TDATA_0,
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MX53_PAD_FEC_TXD1__FEC_TDATA_1,
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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MX53_PAD_FEC_TX_EN__FEC_TX_EN,
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MX53_PAD_SD2_CLK__GPIO1_10,
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MX53_PAD_SD2_DATA3__GPIO1_12,
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MX53_PAD_GPIO_2__GPIO1_2,
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MX53_PAD_GPIO_4__GPIO1_4,
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MX53_PAD_PATA_DATA0__GPIO2_0,
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MX53_PAD_PATA_DATA1__GPIO2_1,
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MX53_PAD_PATA_DATA10__GPIO2_10,
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MX53_PAD_PATA_DATA11__GPIO2_11,
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MX53_PAD_PATA_DATA13__GPIO2_13,
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MX53_PAD_PATA_DATA14__GPIO2_14,
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MX53_PAD_PATA_DATA15__GPIO2_15,
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MX53_PAD_PATA_DATA2__GPIO2_2,
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MX53_PAD_PATA_DATA3__GPIO2_3,
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MX53_PAD_EIM_EB2__GPIO2_30,
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MX53_PAD_PATA_DATA4__PATA_DATA_4,
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MX53_PAD_PATA_DATA5__GPIO2_5,
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MX53_PAD_PATA_DATA6__GPIO2_6,
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MX53_PAD_PATA_DATA7__GPIO2_7,
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MX53_PAD_PATA_DATA8__GPIO2_8,
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MX53_PAD_PATA_DATA9__GPIO2_9,
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MX53_PAD_GPIO_10__GPIO4_0,
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MX53_PAD_GPIO_11__GPIO4_1,
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MX53_PAD_GPIO_12__GPIO4_2,
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MX53_PAD_DISP0_DAT8__GPIO4_29,
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MX53_PAD_GPIO_13__GPIO4_3,
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MX53_PAD_DISP0_DAT16__GPIO5_10,
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MX53_PAD_DISP0_DAT17__GPIO5_11,
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MX53_PAD_CSI0_PIXCLK__GPIO5_18,
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MX53_PAD_CSI0_MCLK__GPIO5_19,
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MX53_PAD_CSI0_DATA_EN__GPIO5_20,
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MX53_PAD_CSI0_VSYNC__GPIO5_21,
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MX53_PAD_CSI0_DAT4__GPIO5_22,
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MX53_PAD_CSI0_DAT5__GPIO5_23,
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MX53_PAD_CSI0_DAT6__GPIO5_24,
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MX53_PAD_DISP0_DAT14__GPIO5_8,
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MX53_PAD_DISP0_DAT15__GPIO5_9,
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MX53_PAD_PATA_DIOW__GPIO6_17,
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MX53_PAD_PATA_DMACK__GPIO6_18,
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MX53_PAD_GPIO_17__GPIO7_12,
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MX53_PAD_GPIO_18__GPIO7_13,
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MX53_PAD_PATA_RESET_B__GPIO7_4,
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MX53_PAD_PATA_IORDY__GPIO7_5,
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MX53_PAD_PATA_DA_0__GPIO7_6,
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MX53_PAD_PATA_DA_2__GPIO7_8,
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MX53_PAD_CSI0_DAT9__I2C1_SCL,
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MX53_PAD_CSI0_DAT8__I2C1_SDA,
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MX53_PAD_KEY_COL3__I2C2_SCL,
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MX53_PAD_KEY_ROW3__I2C2_SDA,
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MX53_PAD_GPIO_5__I2C3_SCL,
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MX53_PAD_GPIO_6__I2C3_SDA,
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MX53_PAD_KEY_COL0__KPP_COL_0,
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MX53_PAD_KEY_COL1__KPP_COL_1,
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MX53_PAD_KEY_COL2__KPP_COL_2,
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MX53_PAD_KEY_COL3__KPP_COL_3,
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MX53_PAD_GPIO_19__KPP_COL_5,
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MX53_PAD_GPIO_9__KPP_COL_6,
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MX53_PAD_SD2_DATA1__KPP_COL_7,
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MX53_PAD_KEY_ROW0__KPP_ROW_0,
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MX53_PAD_KEY_ROW1__KPP_ROW_1,
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MX53_PAD_KEY_ROW2__KPP_ROW_2,
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MX53_PAD_KEY_ROW3__KPP_ROW_3,
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MX53_PAD_SD2_CMD__KPP_ROW_5,
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MX53_PAD_SD2_DATA2__KPP_ROW_6,
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MX53_PAD_SD2_DATA0__KPP_ROW_7,
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MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
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MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
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MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
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MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
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MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
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MX53_PAD_DISP0_DAT8__PWM1_PWMO,
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MX53_PAD_DISP0_DAT9__PWM2_PWMO,
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MX53_PAD_PATA_INTRQ__UART2_CTS,
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MX53_PAD_PATA_DIOR__UART2_RTS,
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
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MX53_PAD_PATA_DA_1__UART3_CTS,
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
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MX53_PAD_CSI0_DAT17__UART4_CTS,
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MX53_PAD_CSI0_DAT16__UART4_RTS,
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MX53_PAD_CSI0_DAT13__UART4_RXD_MUX,
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MX53_PAD_CSI0_DAT12__UART4_TXD_MUX,
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MX53_PAD_CSI0_DAT19__UART5_CTS,
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MX53_PAD_CSI0_DAT18__UART5_RTS,
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MX53_PAD_CSI0_DAT15__UART5_RXD_MUX,
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MX53_PAD_CSI0_DAT14__UART5_TXD_MUX,
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MX53_PAD_GPIO_0__USBOH3_USBH1_PWR,
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MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK,
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MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0,
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MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1,
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MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2,
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MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3,
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MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4,
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MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5,
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MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6,
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MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7,
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MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR,
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MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT,
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MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP,
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MX53_PAD_GPIO_1__WDOG2_WDOG_B,
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};
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#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
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static void vincell_fec_reset(void)
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{
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gpio_direction_output(LOCO_FEC_PHY_RST, 0);
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mdelay(1);
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gpio_set_value(LOCO_FEC_PHY_RST, 1);
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}
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static struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
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};
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static struct i2c_board_info i2c_devices[] = {
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{
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I2C_BOARD_INFO("da9053", 0x48),
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},
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};
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static int vincell_devices_init(void)
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{
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writel(0, MX53_M4IF_BASE_ADDR + 0xc);
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console_flush();
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imx53_init_lowlevel(1000);
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clk_set_rate(clk_lookup("nfc_podf"), 66666667);
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imx53_add_nand(&nand_info);
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imx51_iim_register_fec_ethaddr();
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imx53_add_fec(&fec_info);
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imx53_add_mmc0(NULL);
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i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
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imx53_add_i2c0(NULL);
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vincell_fec_reset();
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armlinux_set_bootparams((void *)0x70000100);
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armlinux_set_architecture(3297);
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devfs_add_partition("nand0", SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", SZ_1M + SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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imx53_bbu_internal_nand_register_handler("nand",
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BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry), 3 * SZ_128K, 0xf8020000);
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return 0;
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}
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device_initcall(vincell_devices_init);
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static int vincell_part_init(void)
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{
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devfs_add_partition("disk0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("disk0", 0x80000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
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return 0;
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}
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late_initcall(vincell_part_init);
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static int vincell_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(vincell_pads, ARRAY_SIZE(vincell_pads));
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imx53_add_uart1();
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return 0;
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}
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console_initcall(vincell_console_init);
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@ -0,0 +1,24 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Global defintions for the ARM i.MX51 based babbage board
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -0,0 +1,10 @@
|
|||
#!/bin/sh
|
||||
|
||||
if [ "$1" = menu ]; then
|
||||
boot-menu-add-entry "$0" "nand (UBI)"
|
||||
exit
|
||||
fi
|
||||
|
||||
global.bootm.image="/dev/nand0.kernel.bb"
|
||||
#global.bootm.oftree="/env/oftree"
|
||||
bootargs-root-ubi -r root -m nand0.root
|
|
@ -0,0 +1,8 @@
|
|||
#!/bin/sh
|
||||
|
||||
if [ "$1" = menu ]; then
|
||||
init-menu-add-entry "$0" "Base bootargs"
|
||||
exit
|
||||
fi
|
||||
|
||||
global.linux.bootargs.base="console=ttymxc0,115200"
|
|
@ -0,0 +1,8 @@
|
|||
#!/bin/sh
|
||||
|
||||
if [ "$1" = menu ]; then
|
||||
init-menu-add-entry "$0" "hostname"
|
||||
exit
|
||||
fi
|
||||
|
||||
global.hostname=vincell
|
|
@ -0,0 +1,11 @@
|
|||
#!/bin/sh
|
||||
|
||||
if [ "$1" = menu ]; then
|
||||
init-menu-add-entry "$0" "NAND partitions"
|
||||
exit
|
||||
fi
|
||||
|
||||
mtdparts="512k(nand0.barebox)ro,512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
|
||||
kernelname="mxc_nand"
|
||||
|
||||
mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <sizes.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/barebox-arm-head.h>
|
||||
#include <mach/imx-flash-header.h>
|
||||
|
||||
void __naked __flash_header_start go(void)
|
||||
{
|
||||
barebox_arm_head();
|
||||
}
|
||||
|
||||
#define APP_DEST 0xf8020000
|
||||
|
||||
struct imx_flash_header_v2 __flash_header_section flash_header = {
|
||||
.header.tag = IVT_HEADER_TAG,
|
||||
.header.length = cpu_to_be16(32),
|
||||
.header.version = IVT_VERSION,
|
||||
|
||||
.entry = APP_DEST + 0x1000,
|
||||
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
|
||||
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
|
||||
.self = APP_DEST + 0x400,
|
||||
|
||||
.boot_data.start = APP_DEST,
|
||||
.boot_data.size = DCD_BAREBOX_SIZE,
|
||||
};
|
|
@ -0,0 +1,149 @@
|
|||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <init.h>
|
||||
#include <mach/imx53-regs.h>
|
||||
#include <mach/imx5.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/esdctl-v4.h>
|
||||
#include <asm/barebox-arm.h>
|
||||
#include <asm/barebox-arm-head.h>
|
||||
#include <io.h>
|
||||
|
||||
#define IOMUX_PADCTL_DDRI_DDR (1 << 9)
|
||||
|
||||
#define IOMUX_PADCTL_DDRDSE(x) ((x) << 19)
|
||||
#define IOMUX_PADCTL_DDRSEL(x) ((x) << 25)
|
||||
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x554
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x558
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x560
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 0x564
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x568
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 0x570
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x574
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 0x578
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x57c
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 0x580
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x588
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x590
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x594
|
||||
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x584
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x6f0
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x6f4
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x6fc
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x710
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x714
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x718
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x71c
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x720
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x724
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x728
|
||||
#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x72c
|
||||
|
||||
|
||||
static void configure_dram_iomux(void)
|
||||
{
|
||||
void __iomem *iomux = (void *)MX53_IOMUXC_BASE_ADDR;
|
||||
u32 r1, r2, r4, r5, r6;
|
||||
|
||||
/* define the INPUT mode for DRAM_D[31:0] */
|
||||
writel(0, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRMODE);
|
||||
|
||||
/*
|
||||
* define the INPUT mode for SDQS[3:0]
|
||||
* (Freescale's documentation suggests DDR-mode for the
|
||||
* control line, but their source actually uses CMOS)
|
||||
*/
|
||||
writel(IOMUX_PADCTL_DDRI_DDR, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL);
|
||||
|
||||
r1 = IOMUX_PADCTL_DDRDSE(5);
|
||||
r2 = IOMUX_PADCTL_DDRDSE(5) | PAD_CTL_PUE;
|
||||
r4 = IOMUX_PADCTL_DDRSEL(2);
|
||||
r5 = IOMUX_PADCTL_DDRDSE(5) | PAD_CTL_PKE | PAD_CTL_PUE | IOMUX_PADCTL_DDRI_DDR | PAD_CTL_PUS_47K_UP;
|
||||
r6 = IOMUX_PADCTL_DDRDSE(4);
|
||||
|
||||
/*
|
||||
* this will adisable the Pull/Keeper for DRAM_x pins EXCEPT,
|
||||
* for DRAM_SDQS[3:0] and DRAM_SDODT[1:0]
|
||||
*/
|
||||
writel(0, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRPKE);
|
||||
|
||||
/* set global drive strength for all DRAM_x pins */
|
||||
writel(r4, iomux + IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE);
|
||||
|
||||
/* set data dqs dqm drive strength */
|
||||
writel(r6, iomux + IOMUXC_SW_PAD_CTL_GRP_B0DS);
|
||||
writel(r6, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0);
|
||||
writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0);
|
||||
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_B1DS);
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1);
|
||||
writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1);
|
||||
|
||||
writel(r6, iomux + IOMUXC_SW_PAD_CTL_GRP_B2DS);
|
||||
writel(r6, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2);
|
||||
writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2);
|
||||
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_B3DS);
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3);
|
||||
writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3);
|
||||
|
||||
/* SDCLK pad drive strength control options */
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0);
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1);
|
||||
|
||||
/* Control and addr bus pad drive strength control options */
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS);
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS);
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_ADDDS);
|
||||
writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_CTLDS);
|
||||
writel(r2, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0);
|
||||
writel(r2, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1);
|
||||
|
||||
/*
|
||||
* enable hysteresis on input pins
|
||||
* (Freescale's documentation suggests that enable hysteresis
|
||||
* would be better, but their source-code doesn't)
|
||||
*/
|
||||
writel(PAD_CTL_HYS, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRHYS);
|
||||
}
|
||||
|
||||
void disable_watchdog(void)
|
||||
{
|
||||
/*
|
||||
* configure WDOG to generate external reset on trigger
|
||||
* and disable power down counter
|
||||
*/
|
||||
writew(0x38, MX53_WDOG1_BASE_ADDR);
|
||||
writew(0x0, MX53_WDOG1_BASE_ADDR + 8);
|
||||
writew(0x38, MX53_WDOG2_BASE_ADDR);
|
||||
writew(0x0, MX53_WDOG2_BASE_ADDR + 8);
|
||||
}
|
||||
|
||||
void sdram_init(void);
|
||||
|
||||
void __bare_init __naked reset(void)
|
||||
{
|
||||
u32 r;
|
||||
|
||||
common_reset();
|
||||
|
||||
/* Skip SDRAM initialization if we run from RAM */
|
||||
r = get_pc();
|
||||
if (r > 0x70000000 && r < 0xf0000000)
|
||||
board_init_lowlevel_return();
|
||||
|
||||
/* Setup a preliminary stack */
|
||||
r = 0xf8000000 + 0x60000 - 16;
|
||||
__asm__ __volatile__("mov sp, %0" : : "r"(r));
|
||||
|
||||
disable_watchdog();
|
||||
|
||||
configure_dram_iomux();
|
||||
|
||||
imx5_init_lowlevel();
|
||||
|
||||
imx_esdctlv4_init();
|
||||
|
||||
board_init_lowlevel_return();
|
||||
}
|
|
@ -0,0 +1,82 @@
|
|||
CONFIG_ARCH_IMX=y
|
||||
CONFIG_ARCH_IMX53=y
|
||||
CONFIG_MACH_GUF_VINCELL=y
|
||||
CONFIG_IMX_IIM=y
|
||||
CONFIG_IMX_IIM_FUSE_BLOW=y
|
||||
CONFIG_THUMB2_BAREBOX=y
|
||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||
CONFIG_ARM_UNWIND=y
|
||||
CONFIG_PBL_IMAGE=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_TEXT_BASE=0x7fe00000
|
||||
CONFIG_MALLOC_SIZE=0x2000000
|
||||
CONFIG_MALLOC_TLSF=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_LONGHELP=y
|
||||
CONFIG_HUSH_FANCY_PROMPT=y
|
||||
CONFIG_CMDLINE_EDITING=y
|
||||
CONFIG_AUTO_COMPLETE=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/guf-vincell/env"
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_CMD_EDIT=y
|
||||
CONFIG_CMD_SLEEP=y
|
||||
CONFIG_CMD_MSLEEP=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
CONFIG_CMD_EXPORT=y
|
||||
CONFIG_CMD_PRINTENV=y
|
||||
CONFIG_CMD_READLINE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_DIRNAME=y
|
||||
CONFIG_CMD_LN=y
|
||||
CONFIG_CMD_READLINK=y
|
||||
CONFIG_CMD_TFTP=y
|
||||
CONFIG_CMD_FILETYPE=y
|
||||
CONFIG_CMD_ECHO_E=y
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_IOMEM=y
|
||||
CONFIG_CMD_CRC=y
|
||||
CONFIG_CMD_CRC_CMP=y
|
||||
CONFIG_CMD_MD5SUM=y
|
||||
CONFIG_CMD_FLASH=y
|
||||
CONFIG_CMD_BOOTM_SHOW_TYPE=y
|
||||
CONFIG_CMD_BOOTM_VERBOSE=y
|
||||
CONFIG_CMD_BOOTM_INITRD=y
|
||||
CONFIG_CMD_BOOTM_OFTREE=y
|
||||
# CONFIG_CMD_BOOTU is not set
|
||||
CONFIG_CMD_RESET=y
|
||||
CONFIG_CMD_GO=y
|
||||
CONFIG_CMD_OFTREE=y
|
||||
CONFIG_CMD_BAREBOX_UPDATE=y
|
||||
CONFIG_CMD_TIMEOUT=y
|
||||
CONFIG_CMD_PARTITION=y
|
||||
CONFIG_CMD_MAGICVAR=y
|
||||
CONFIG_CMD_MAGICVAR_HELP=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_UNCOMPRESS=y
|
||||
CONFIG_CMD_MIITOOL=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_NET_DHCP=y
|
||||
CONFIG_NET_NFS=y
|
||||
CONFIG_NET_PING=y
|
||||
CONFIG_NET_RESOLV=y
|
||||
CONFIG_DRIVER_NET_FEC_IMX=y
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_IMX=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_DEVICE=y
|
||||
CONFIG_NAND=y
|
||||
# CONFIG_NAND_ECC_SOFT is not set
|
||||
# CONFIG_NAND_ECC_HW_SYNDROME is not set
|
||||
# CONFIG_NAND_ECC_HW_NONE is not set
|
||||
CONFIG_NAND_IMX=y
|
||||
CONFIG_MCI=y
|
||||
CONFIG_MCI_STARTUP=y
|
||||
CONFIG_MCI_IMX_ESDHC=y
|
||||
CONFIG_FS_TFTP=y
|
||||
CONFIG_FS_NFS=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_FAT_WRITE=y
|
||||
CONFIG_FS_FAT_LFN=y
|
|
@ -28,6 +28,7 @@ config ARCH_TEXT_BASE
|
|||
default 0x97f00000 if MACH_CCMX51
|
||||
default 0x4fc00000 if MACH_SABRELITE
|
||||
default 0x8fe00000 if MACH_TX53
|
||||
default 0x7fc00000 if MACH_GUF_VINCELL
|
||||
|
||||
config BOARDINFO
|
||||
default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
|
||||
|
@ -55,6 +56,7 @@ config BOARDINFO
|
|||
default "ConnectCore i.MX51" if MACH_CCMX51
|
||||
default "Sabre Lite" if MACH_SABRELITE
|
||||
default "Ka-Ro tx53" if MACH_TX53
|
||||
default "Garz+Fricke Vincell" if MACH_GUF_VINCELL
|
||||
|
||||
choice
|
||||
prompt "Select boot mode"
|
||||
|
@ -469,6 +471,11 @@ config MACH_TX53
|
|||
help
|
||||
Say Y here if you are using the Ka-Ro tx53 board
|
||||
|
||||
config MACH_GUF_VINCELL
|
||||
select HAVE_DEFAULT_ENVIRONMENT_NEW
|
||||
select MACH_HAS_LOWLEVEL_INIT
|
||||
bool "Garz-Fricke Vincell"
|
||||
|
||||
endchoice
|
||||
|
||||
if MACH_TX53
|
||||
|
@ -478,7 +485,9 @@ config TX53_REV_1011
|
|||
bool "1011"
|
||||
config TX53_REV_XX30
|
||||
bool "8030 / 1030"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
endif
|
||||
|
|
Loading…
Reference in New Issue