From debb7354d1ea4f694154818df5e5b523f5c1cc1d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 26 Apr 2006 17:58:56 -0500 Subject: [PATCH 001/101] Initial support for MPC8641 HPCN board. --- Makefile | 11 + board/mpc8641hpcn/Makefile | 57 ++ board/mpc8641hpcn/config.mk | 32 + board/mpc8641hpcn/flash.c | 550 +++++++++++++ board/mpc8641hpcn/init.S | 172 ++++ board/mpc8641hpcn/mpc8641hpcn.c | 315 +++++++ board/mpc8641hpcn/oftree.dts | 186 +++++ board/mpc8641hpcn/u-boot.lds | 148 ++++ common/ft_build.c | 10 +- cpu/mpc86xx/Makefile | 48 ++ cpu/mpc86xx/cache.S | 368 +++++++++ cpu/mpc86xx/config.mk | 26 + cpu/mpc86xx/cpu.c | 669 +++++++++++++++ cpu/mpc86xx/cpu_init.c | 134 +++ cpu/mpc86xx/i2c.c | 273 +++++++ cpu/mpc86xx/interrupts.c | 225 +++++ cpu/mpc86xx/pci.c | 196 +++++ cpu/mpc86xx/resetvec.S | 2 + cpu/mpc86xx/spd_sdram.c | 1017 +++++++++++++++++++++++ cpu/mpc86xx/speed.c | 248 ++++++ cpu/mpc86xx/start.S | 1240 ++++++++++++++++++++++++++++ cpu/mpc86xx/traps.c | 253 ++++++ drivers/pci_auto.c | 2 +- drivers/tsec.c | 69 +- drivers/tsec.h | 20 +- include/asm-ppc/immap_86xx.h | 1362 +++++++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 15 +- include/asm-ppc/processor.h | 18 +- include/asm-ppc/u-boot.h | 2 +- include/common.h | 11 +- include/configs/MPC8641HPCN.h | 629 ++++++++++++++ include/ft_build.h | 4 +- include/mpc86xx.h | 119 +++ include/pci.h | 6 + lib_ppc/board.c | 2 +- net/eth.c | 16 + 36 files changed, 8435 insertions(+), 20 deletions(-) create mode 100644 board/mpc8641hpcn/Makefile create mode 100644 board/mpc8641hpcn/config.mk create mode 100644 board/mpc8641hpcn/flash.c create mode 100644 board/mpc8641hpcn/init.S create mode 100644 board/mpc8641hpcn/mpc8641hpcn.c create mode 100644 board/mpc8641hpcn/oftree.dts create mode 100644 board/mpc8641hpcn/u-boot.lds create mode 100644 cpu/mpc86xx/Makefile create mode 100644 cpu/mpc86xx/cache.S create mode 100644 cpu/mpc86xx/config.mk create mode 100644 cpu/mpc86xx/cpu.c create mode 100644 cpu/mpc86xx/cpu_init.c create mode 100644 cpu/mpc86xx/i2c.c create mode 100644 cpu/mpc86xx/interrupts.c create mode 100644 cpu/mpc86xx/pci.c create mode 100644 cpu/mpc86xx/resetvec.S create mode 100644 cpu/mpc86xx/spd_sdram.c create mode 100644 cpu/mpc86xx/speed.c create mode 100644 cpu/mpc86xx/start.S create mode 100644 cpu/mpc86xx/traps.c create mode 100644 include/asm-ppc/immap_86xx.h create mode 100644 include/configs/MPC8641HPCN.h create mode 100644 include/mpc86xx.h diff --git a/Makefile b/Makefile index 74e94749f..acfa5bd24 100644 --- a/Makefile +++ b/Makefile @@ -114,6 +114,9 @@ endif ifeq ($(CPU),mpc85xx) OBJS += cpu/$(CPU)/resetvec.o endif +ifeq ($(CPU),mpc86xx) +OBJS += cpu/$(CPU)/resetvec.o +endif ifeq ($(CPU),bf533) OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o @@ -1414,6 +1417,14 @@ TQM8560_config: unconfig echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>include/config.h @./mkconfig -a TQM85xx ppc mpc85xx tqm85xx +######################################################################### +## MPC86xx Systems +######################################################################### + +MPC8641HPCN_config: unconfig + @./mkconfig $(@:_config=) ppc mpc86xx mpc8641hpcn + + ######################################################################### ## 74xx/7xx Systems ######################################################################### diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile new file mode 100644 index 000000000..d6037c1c4 --- /dev/null +++ b/board/mpc8641hpcn/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o oftree.o +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +%.dtb: %.dts + dtc -f -V 0x10 -I dts -O dtb $< >$@ + +%.c: %.dtb + xxd -i $< \ + | sed -e "s/^unsigned char/const unsigned char/g" \ + | sed -e "s/^unsigned int/const unsigned int/g" > $@ + + +clean: + rm -f $(OBJS) $(SOBJS) *.dtb oftree.c +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +ifeq ($(filter distclean, $(MAKECMDGOALS)),) +-include .depend +endif + +######################################################################### diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk new file mode 100644 index 000000000..63b9779af --- /dev/null +++ b/board/mpc8641hpcn/config.mk @@ -0,0 +1,32 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Jeff Brown (jeffrey@freescale.com) +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8641hpcn board +# default CCSRBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +#TEXT_BASE = 0xfff01000 +TEXT_BASE = 0x00400000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc8641hpcn/flash.c b/board/mpc8641hpcn/flash.c new file mode 100644 index 000000000..e2f7816e1 --- /dev/null +++ b/board/mpc8641hpcn/flash.c @@ -0,0 +1,550 @@ +/* + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao,(X.Xiao@motorola.com) + * + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if !defined(CFG_NO_FLASH) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#undef DEBUG + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int clear_block_lock_bit(vu_long * addr); +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: enable write, + * or we cannot even write flash commands + */ + for (i=0; i= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); + break; + case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + ulong sector_offset; + +#ifdef DEBUG + printf("Check flash at 0x%08x\n",(uint)addr); +#endif + /* Write "Intelligent Identifier" command: read Manufacturer ID */ + *addr = 0x90909090; + udelay(20); + asm("sync"); + + value = addr[0] & 0x00FF00FF; + +#ifdef DEBUG + printf("manufacturer=0x%x\n",(uint)value); +#endif + switch (value) { + case MT_MANUFACT: /* SHARP, MT or => Intel */ + case INTEL_ALT_MANU: + info->flash_id = FLASH_MAN_INTEL; + break; + default: +#if defined(CONFIG_MPC8641_SIM) + info->flash_id = FLASH_MAN_INTEL; + break; +#else + printf("unknown manufacturer: %x\n", (unsigned int)value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ +#endif + } + + value = addr[1] & 0x00FF00FF; /* device ID */ + +#ifdef DEBUG + printf("deviceID=0x%x\n",(uint)value); +#endif + switch (value) { + case (INTEL_ID_28F016S): + info->flash_id += FLASH_28F016SV; + info->sector_count = 32; + info->size = 0x00400000; + sector_offset = 0x20000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F160S3): + info->flash_id += FLASH_28F160S3; + info->sector_count = 32; + info->size = 0x00400000; + sector_offset = 0x20000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F320S3): + info->flash_id += FLASH_28F320S3; + info->sector_count = 64; + info->size = 0x00800000; + sector_offset = 0x20000; + break; /* => 2x4 MB */ + + case (INTEL_ID_28F640J3A): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x01000000; + sector_offset = 0x40000; + break; /* => 2x8 MB */ + + case SHARP_ID_28F016SCL: + case SHARP_ID_28F016SCZ: + info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + info->sector_count = 32; + info->size = 0x00800000; + sector_offset = 0x40000; + break; /* => 4x2 MB */ + + + default: +#if defined(CONFIG_MPC8641_SIM) + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + info->size = 0x01000000; + sector_offset = 0x40000; + break; /* => 2x8 MB */ +#else + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ +#endif + + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += sector_offset; + /* don't know how to check sector protection */ + info->protect[i] = 0; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + *addr = 0xFFFFFF; /* reset bank to read array mode */ + asm("sync"); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + +#ifdef DEBUG + printf("\nFlash Erase:\n"); +#endif + /* Make Sure Block Lock Bit is not set. */ + if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ + return 1; + } + + /* Start erase on unprotected sectors */ +#if defined(DEBUG) + printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); +#endif + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + asm("sync"); + + last = start = get_timer (0); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + /* Single Block Erase Command */ + *addr = 0x20202020; + asm("sync"); + /* Confirm */ + *addr = 0xD0D0D0D0; + asm("sync"); + + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = 0xD0D0D0D0; + asm("sync"); + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + while ((*addr & 0x00800080) != 0x00800080) { + if(*addr & 0x00200020){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + /* reset to read mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + } + } + + printf ("flash erase done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong start, csr; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = 0x10101010; + asm("sync"); + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + + while (((csr = *addr) & 0x00800080) != 0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x40404040) { + printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + + /* Clear Status Registers Command */ + *addr = 0x50505050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + + return (flag); +} + +/*----------------------------------------------------------------------- + * Clear Block Lock Bit, returns: + * 0 - OK + * 1 - Timeout + */ + +static int clear_block_lock_bit(vu_long * addr) +{ + ulong start, now; + + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + + *addr = 0x60606060; + asm("sync"); + *addr = 0xd0d0d0d0; + asm("sync"); + + start = get_timer (0); + while((*addr & 0x00800080) != 0x00800080){ + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout on clearing Block Lock Bit\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + } + return 0; +} + +#endif /* !CFG_NO_FLASH */ diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S new file mode 100644 index 000000000..9d43de553 --- /dev/null +++ b/board/mpc8641hpcn/init.S @@ -0,0 +1,172 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR1 0 +#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) +/*#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */ +#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR4 ((0xf8100000>>12) & 0xffffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) + +#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) +/*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ +#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) + + #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) + #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) + + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +/* +#ifdef CFG_INIT_RAM_LOCK +#define LAWBAR7 ((CFG_RIO_MEM_BASE>>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#endif +*/ +/* + * Stack at 0xfc00_0000 for 32M on LBC + */ +#if !defined(CFG_INIT_RAM_LOCK) +#define LAWBAR7 ((CFG_INIT_RAM_ADDR>>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#endif + + .section .bootpg, "ax" + .globl law_entry +law_entry: + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + addi r4,r7,0 + addi r5,r7,0 + + /* Skip LAWAR0, start at LAWAR1 */ + lis r6,LAWBAR1@h + ori r6,r6,LAWBAR1@l + stwu r6, 0xc28(r4) + + lis r6,LAWAR1@h + ori r6,r6,LAWAR1@l + stwu r6, 0xc30(r5) + + /* LAWBAR2, LAWAR2 */ + lis r6,LAWBAR2@h + ori r6,r6,LAWBAR2@l + stwu r6, 0x20(r4) + + lis r6,LAWAR2@h + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) + + /* LAWBAR3, LAWAR3 */ + lis r6,LAWBAR3@h + ori r6,r6,LAWBAR3@l + stwu r6, 0x20(r4) + + lis r6,LAWAR3@h + ori r6,r6,LAWAR3@l + stwu r6, 0x20(r5) + + /* LAWBAR4, LAWAR4 */ + lis r6,LAWBAR4@h + ori r6,r6,LAWBAR4@l + stwu r6, 0x20(r4) + + lis r6,LAWAR4@h + ori r6,r6,LAWAR4@l + stwu r6, 0x20(r5) + /* LAWBAR5, LAWAR5 */ + lis r6,LAWBAR5@h + ori r6,r6,LAWBAR5@l + stwu r6, 0x20(r4) + + lis r6,LAWAR5@h + ori r6,r6,LAWAR5@l + stwu r6, 0x20(r5) + + /* LAWBAR6, LAWAR6 */ + lis r6,LAWBAR6@h + ori r6,r6,LAWBAR6@l + stwu r6, 0x20(r4) + + lis r6,LAWAR6@h + ori r6,r6,LAWAR6@l + stwu r6, 0x20(r5) + + /* LAWBAR7, LAWAR7 */ + lis r6,LAWBAR7@h + ori r6,r6,LAWBAR7@l + stwu r6, 0x20(r4) + + lis r6,LAWAR7@h + ori r6,r6,LAWAR7@l + stwu r6, 0x20(r5) + + blr + diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c new file mode 100644 index 000000000..cdfce6c1f --- /dev/null +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -0,0 +1,315 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram(void); + + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts("Board: MPC8641HPCN\n"); + +#ifdef CONFIG_PCI + + /* Sri: Note that at this point we will only test on PCI1 + */ + + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + + + if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + debug ("PCI-EXPRESS 1: %s \n", + pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + } + debug ("\n"); + } else { + printf ("PCI-EXPRESS 1: Disabled\n"); + } + +#else + printf("PCI-EXPRESS1: Disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CFG_RAMBOOT) + puts(" DDR: "); + return dram_size; +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. Currently HPCN doesn't have + * SDRAM but we'll leave this here for now + * in case someone changes their mind + */ +#if !defined(CONFIG_MPC8641HPCN) + // sdram_init(); +#endif + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ +#if !defined(CFG_RAMBOOT) + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr1; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode_1 = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; + +#if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000008D; + ddr->err_sbe = 0x00ff0000; +#endif + asm("sync;isync"); + + udelay(500); + +#if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); +#else + ddr->sdram_cfg_1 = CFG_DDR_CONTROL; + ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; +#endif + asm("sync; isync"); + + udelay(500); +#endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_fsl86xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc86xxcts_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc86xx_init(struct pci_controller *hose); + + pci_mpc86xx_init(&hose); +#endif /* CONFIG_PCI */ +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } + +} +#endif + +void +after_reloc(ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* now, jump to the main U-Boot board init code */ + board_init_r ((gd_t *)gd, dest_addr); + + /* NOTREACHED */ +} + + + diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts new file mode 100644 index 000000000..6c32ade0c --- /dev/null +++ b/board/mpc8641hpcn/oftree.dts @@ -0,0 +1,186 @@ +/* + * MPC8641 HPCn Device Tree Source + * + * Copyright 2006 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +/ { + model = "MPC8641HPCN"; + compatible = "mpc86xx"; + #address-cells = <1>; + #size-cells = <1>; + linux,phandle = <100>; + + cpus { + #cpus = <1>; + #address-cells = <1>; + #size-cells = <0>; + linux,phandle = <200>; + + PowerPC,8641@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <8000>; // L1, 32K + i-cache-size = <8000>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // 166 MHz + clock-frequency = <0>; // 825 MHz, from uboot + 32-bit; + linux,phandle = <201>; + linux,boot-cpu; + }; + }; + + memory { + device_type = "memory"; + linux,phandle = <300>; + reg = <00000000 10000000>; // 256M at 0x0 + }; + + soc8641@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <2>; + device_type = "soc"; + ranges = <0 f8000000 00100000>; + reg = ; // CCSRBAR 1M + bus-frequency = <0>; + + i2c@3000 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3000 100>; + interrupts = <1b 0>; + interrupt-parent = <40000>; + dfsrr; + }; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "mdio"; + compatible = "gianfar"; + reg = <24520 20>; + linux,phandle = <24520>; + ethernet-phy@0 { + linux,phandle = <2452000>; + interrupt-parent = <40000>; + interrupts = <35 0>; + reg = <0>; + device_type = "ethernet-phy"; + }; + ethernet-phy@1 { + linux,phandle = <2452001>; + interrupt-parent = <40000>; + interrupts = <35 0>; + reg = <1>; + device_type = "ethernet-phy"; + }; + ethernet-phy@2 { + linux,phandle = <2452002>; + interrupt-parent = <40000>; + interrupts = <35 0>; + reg = <2>; + device_type = "ethernet-phy"; + }; + ethernet-phy@3 { + linux,phandle = <2452003>; + interrupt-parent = <40000>; + interrupts = <35 0>; + reg = <3>; + device_type = "ethernet-phy"; + }; + }; + + ethernet@24000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <24000 1000>; + address = [ 00 E0 0C 00 73 00 ]; + interrupts = ; + interrupt-parent = <40000>; + phy-handle = <2452000>; + }; + + ethernet@25000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <25000 1000>; + address = [ 00 E0 0C 00 73 01 ]; + interrupts = <13 3 14 3 18 3>; + interrupt-parent = <40000>; + phy-handle = <2452001>; + }; + + ethernet@26000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <26000 1000>; + address = [ 00 E0 0C 00 02 FD ]; + interrupts = ; + interrupt-parent = <40000>; + phy-handle = <2452002>; + }; + + ethernet@27000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <27000 1000>; + address = [ 00 E0 0C 00 03 FD ]; + interrupts = <15 3 16 3 17 3>; + interrupt-parent = <40000>; + phy-handle = <2452003>; + }; + serial@4500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <4500 100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + interrupts = <1a 3>; + interrupt-parent = <40000>; + }; + + serial@4600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <4600 100>; // reg base, size + clock-frequency = <0>; // should we fill in in uboot? + interrupts = <1a 3>; + interrupt-parent = <40000>; + }; + + pic@40000 { + linux,phandle = <40000>; + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <40000 40000>; + built-in; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + }; +}; + diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds new file mode 100644 index 000000000..dbe8e4fab --- /dev/null +++ b/board/mpc8641hpcn/u-boot.lds @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2004, Freescale, Inc. + * (C) Copyright 2002,2003, Motorola,Inc. + * Jeff Brown (jeffrey@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ +/* .resetvec 0xFFF00100 : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFF70000 : + { + cpu/mpc86xx/start.o (.bootpg) + board/mpc8641hpcn/init.o (.bootpg) + } = 0xffff +*/ + /* Read-only sections, merged into text segment: */ + . = + 1024; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + board/mpc8641hpcn/init.o (.text) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + cpu/mpc86xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/common/ft_build.c b/common/ft_build.c index 9e9c906fc..782046dda 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -299,16 +299,16 @@ static void print_data(const void *data, int len) switch (len) { case 1: /* byte */ - printf(" = <0x%02x>", (*(u8 *) data) & 0xff); + printf(" = <%02x>", (*(u8 *) data) & 0xff); break; case 2: /* half-word */ - printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); + printf(" = <%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); break; case 4: /* word */ - printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); + printf(" = <%x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); break; case 8: /* double-word */ - printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data)); + printf(" = <%qx>", be64_to_cpu(*(uint64_t *) data)); break; default: /* anything else... hexdump */ printf(" = ["); @@ -350,7 +350,7 @@ void ft_dump_blob(const void *bphp) if (addr == 0 && size == 0) break; - printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size); + printf("/memreserve/ %qx %qx;\n", addr, size); } p = p_struct; diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile new file mode 100644 index 000000000..0dd099df6 --- /dev/null +++ b/cpu/mpc86xx/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002,2003 Motorola Inc. +# Xianghua Xiao,X.Xiao@motorola.com +# +# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port) +# Jeff Brown (Jeffrey@freescale.com) +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o #resetvec.o +ASOBJS = cache.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ + pci.o i2c.o spd_sdram.o +OBJS = $(COBJS) + +all: .depend $(START) $(ASOBJS) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(ASOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S new file mode 100644 index 000000000..75186b1e4 --- /dev/null +++ b/cpu/mpc86xx/cache.S @@ -0,0 +1,368 @@ +#include +#include +#include + +#include +#include + +#include +#include + +#ifndef CACHE_LINE_SIZE +# define CACHE_LINE_SIZE L1_CACHE_BYTES +#endif + +#if CACHE_LINE_SIZE == 128 +#define LG_CACHE_LINE_SIZE 7 +#elif CACHE_LINE_SIZE == 32 +#define LG_CACHE_LINE_SIZE 5 +#elif CACHE_LINE_SIZE == 16 +#define LG_CACHE_LINE_SIZE 4 +#elif CACHE_LINE_SIZE == 8 +#define LG_CACHE_LINE_SIZE 3 +#else +# error "Invalid cache line size!" +#endif + +/* + * Most of this code is taken from 74xx_7xx/cache.S + * and then cleaned up a bit + */ + +/* + * Invalidate L1 instruction cache. + */ +_GLOBAL(invalidate_l1_instruction_cache) + /* use invalidate-all bit in HID0 */ + mfspr r3,HID0 + ori r3,r3,HID0_ICFI + mtspr HID0,r3 + isync + blr + +/* + * Invalidate L1 data cache. + */ +_GLOBAL(invalidate_l1_data_cache) + mfspr r3,HID0 + ori r3,r3,HID0_DCFI + mtspr HID0,r3 + isync + blr + +/* + * Flush data cache. + */ +_GLOBAL(flush_data_cache) + lis r3,0 + lis r5,CACHE_LINE_SIZE +flush: + cmp 0,1,r3,r5 + bge done + lwz r5,0(r3) + lis r5,CACHE_LINE_SIZE + addi r3,r3,0x4 + b flush +done: + blr +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * This is a no-op on the 601. + * + * flush_icache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_icache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 2b + sync /* additional sync needed on g4 */ + isync + blr +/* + * Write any modified data cache blocks out to memory. + * Does not invalidate the corresponding cache lines (especially for + * any corresponding instruction cache). + * + * clean_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(clean_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 /* align r3 down to cache line */ + subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ + add r4,r4,r5 /* r4 += cache_line_size-1 */ + srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ + beqlr /* if r4 == 0 return */ + mtctr r4 /* ctr = r4 */ + + sync +1: dcbst 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + + sync +1: dcbf 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbf's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,CACHE_LINE_SIZE-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,LG_CACHE_LINE_SIZE + beqlr + mtctr r4 + + sync +1: dcbi 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + +/* + * Flush a particular page from the data cache to RAM. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * + * void __flush_page_to_ram(void *page) + */ +_GLOBAL(__flush_page_to_ram) + rlwinm r3,r3,0,0,19 /* Get page base address */ + li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + mtctr r4 + mr r6,r3 +0: dcbst 0,r3 /* Write line to ram */ + addi r3,r3,CACHE_LINE_SIZE + bdnz 0b + sync + mtctr r4 +1: icbi 0,r6 + addi r6,r6,CACHE_LINE_SIZE + bdnz 1b + sync + isync + blr + +/* + * Flush a particular page from the instruction cache. + * Note: this is necessary because the instruction cache does *not* + * snoop from the data cache. + * + * void __flush_icache_page(void *page) + */ +_GLOBAL(__flush_icache_page) + li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + mtctr r4 +1: icbi 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + sync + isync + blr + +/* + * Clear a page using the dcbz instruction, which doesn't cause any + * memory traffic (except to write out any cache lines which get + * displaced). This only works on cacheable memory. + */ +_GLOBAL(clear_page) + li r0,4096/CACHE_LINE_SIZE + mtctr r0 +1: dcbz 0,r3 + addi r3,r3,CACHE_LINE_SIZE + bdnz 1b + blr + +/* + * Enable L1 Instruction cache + */ +_GLOBAL(icache_enable) + mfspr r3, HID0 + li r5, HID0_ICFI|HID0_ILOCK + andc r3, r3, r5 + ori r3, r3, HID0_ICE + ori r5, r3, HID0_ICFI + mtspr HID0, r5 + mtspr HID0, r3 + isync + blr + +/* + * Disable L1 Instruction cache + */ +_GLOBAL(icache_disable) + mfspr r3, HID0 + li r5, 0 + ori r5, r5, HID0_ICE + andc r3, r3, r5 + mtspr HID0, r3 + isync + blr + +/* + * Is instruction cache enabled? + */ +_GLOBAL(icache_status) + mfspr r3, HID0 + andi. r3, r3, HID0_ICE + blr + + +_GLOBAL(l1dcache_enable) + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync + blr + +/* + * Enable data cache(s) - L1 and optionally L2 + * Calls l2cache_enable. LR saved in r5 + */ +_GLOBAL(dcache_enable) + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync +#ifdef CFG_L2 + mflr r5 + bl l2cache_enable /* uses r3 and r4 */ + sync + mtlr r5 +#endif + blr + + +/* + * Disable data cache(s) - L1 and optionally L2 + * Calls flush_data_cache and l2cache_disable_no_flush. + * LR saved in r4 + */ +_GLOBAL(dcache_disable) + mflr r4 /* save link register */ + bl flush_data_cache /* uses r3 and r5 */ + sync + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + li r5, HID0_DCE|HID0_DCFI + andc r3, r3, r5 /* no enable, no invalidate */ + mtspr HID0, r3 + sync +#ifdef CFG_L2 + bl l2cache_disable_no_flush /* uses r3 */ +#endif + mtlr r4 /* restore link register */ + blr + +/* + * Is data cache enabled? + */ +_GLOBAL(dcache_status) + mfspr r3, HID0 + andi. r3, r3, HID0_DCE + blr + +/* + * Invalidate L2 cache using L2I and polling L2IP + */ +_GLOBAL(l2cache_invalidate) + sync + oris r3, r3, L2CR_L2I@h + sync + mtspr l2cr, r3 + sync +invl2: + mfspr r3, l2cr + andi. r3, r3, L2CR_L2IP + bne invl2 + /* turn off the global invalidate bit */ + mfspr r3, l2cr + rlwinm r3, r3, 0, 11, 9 + sync + mtspr l2cr, r3 + sync + blr + +/* + * Enable L2 cache + * Calls l2cache_invalidate. LR is saved in r4 + */ +_GLOBAL(l2cache_enable) + mflr r4 /* save link register */ + bl l2cache_invalidate /* uses r3 */ + sync + lis r3, L2_ENABLE@h + ori r3, r3, L2_ENABLE@l + mtspr l2cr, r3 + isync + mtlr r4 /* restore link register */ + blr + +/* + * Disable L2 cache + * Calls flush_data_cache. LR is saved in r4 + */ +_GLOBAL(l2cache_disable) + mflr r4 /* save link register */ + bl flush_data_cache /* uses r3 and r5 */ + sync + mtlr r4 /* restore link register */ +l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ + lis r3, L2_INIT@h + ori r3, r3, L2_INIT@l + mtspr l2cr, r3 + isync + blr diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk new file mode 100644 index 000000000..4ef7ace2f --- /dev/null +++ b/cpu/mpc86xx/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2004 Freescale Semiconductor. +# Jeff Brown +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring \ No newline at end of file diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c new file mode 100644 index 000000000..b0fe8abb2 --- /dev/null +++ b/cpu/mpc86xx/cpu.c @@ -0,0 +1,669 @@ +/* + * Copyright 2004 Freescale Semiconductor + * Jeff Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + + +// SS: For debug only, remove after use + +static __inline__ unsigned long get_dbat3u (void) +{ + unsigned long dbat3u; + asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); + return dbat3u; +} + +static __inline__ unsigned long get_dbat3l (void) +{ + unsigned long dbat3l; + asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); + return dbat3l; +} + +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; +} + +extern unsigned long get_board_sys_clk(ulong dummy); + +int checkcpu (void) +{ + sys_info_t sysinfo; + uint pvr, svr; + uint ver; + uint major, minor; + uint lcrr; /* local bus clock ratio register */ + uint clkdiv; /* clock divider portion of lcrr */ + + puts("Freescale PowerPC\n"); + + pvr = get_pvr(); + ver = PVR_VER(pvr); + major = PVR_MAJ(pvr); + minor = PVR_MIN(pvr); + + puts ("CPU:\n"); + + printf(" Core: "); + + switch (ver) { + case PVR_VER(PVR_86xx): + puts("E600"); + break; + default: + puts("Unknown"); + break; + } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + + svr = get_svr(); + ver = SVR_VER(svr); + major = SVR_MAJ(svr); + minor = SVR_MIN(svr); + + puts(" System: "); + switch (ver) { + case SVR_8641: + puts("8641"); + break; + case SVR_8641D: + puts("8641D"); + break; + default: + puts("Unknown"); + break; + } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); + + get_sys_info(&sysinfo); + + puts(" Clocks: "); + printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); + printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); + printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); + +#if defined(CFG_LBC_LCRR) + lcrr = CFG_LBC_LCRR; +#else + { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + + lcrr = lbc->lcrr; + } +#endif + clkdiv = lcrr & 0x0f; + if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { + printf("LBC:%4lu MHz\n", + sysinfo.freqSystemBus / 1000000 / clkdiv); + } else { + printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); + } + + printf(" L2: "); + if (get_l2cr() & 0x80000000) + printf("Enabled\n"); + else + printf("Disabled\n"); + + return (0); +} + + +/* -------------------------------------------------------------------- */ + +static inline void +soft_restart(unsigned long addr) +{ + +#ifndef CONFIG_MPC8641HPCN + + /* SRR0 has system reset vector, SRR1 has default MSR value */ + /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ + + __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); + __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); + __asm__ __volatile__ ("mtspr 27, 4"); + __asm__ __volatile__ ("rfi"); + +#else /* CONFIG_MPC8641HPCN */ + out8(PIXIS_BASE+PIXIS_RST,0); +#endif /* !CONFIG_MPC8641HPCN */ + while(1); /* not reached */ +} + + + +#ifdef CONFIG_MPC8641HPCN + +int set_px_sysclk(ulong sysclk) +{ + u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux,tmp; + + /* Per table 27, page 58 of MPC8641HPCN spec*/ + switch(sysclk) + { + case 33: + sysclk_s = 0x04; + sysclk_r = 0x04; + sysclk_v = 0x07; + sysclk_aux = 0x00; + break; + case 40: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x20; + sysclk_aux = 0x01; + break; + case 50: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x2A; + sysclk_aux = 0x02; + break; + case 66: + sysclk_s = 0x01; + sysclk_r = 0x04; + sysclk_v = 0x04; + sysclk_aux = 0x03; + break; + case 83: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x04; + break; + case 100: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x5C; + sysclk_aux = 0x05; + break; + case 134: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x3B; + sysclk_aux = 0x06; + break; + case 166: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x07; + break; + default: + printf("Unsupported SYSCLK frequency.\n"); + return 0; + } + + vclkh = (sysclk_s << 5) | sysclk_r ; + vclkl = sysclk_v; + out8(PIXIS_BASE+PIXIS_VCLKH,vclkh); + out8(PIXIS_BASE+PIXIS_VCLKL,vclkl); + + out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux); + + return 1; +} + +int set_px_mpxpll(ulong mpxpll) +{ + u8 tmp; + u8 val; + switch(mpxpll) + { + case 2: + case 4: + case 6: + case 8: + case 10: + case 12: + case 14: + case 16: + val = (u8)mpxpll; + break; + default: + printf("Unsupported MPXPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE+PIXIS_VSPEED1); + tmp = (tmp & 0xF0) | (val & 0x0F); + out8(PIXIS_BASE+PIXIS_VSPEED1,tmp); + + return 1; +} + +int set_px_corepll(ulong corepll) +{ + u8 tmp; + u8 val; + + switch((int)corepll) + { + case 20: + val = 0x08; + break; + case 25: + val = 0x0C; + break; + case 30: + val = 0x10; + break; + case 35: + val = 0x1C; + break; + case 40: + val = 0x14; + break; + case 45: + val = 0x0E; + break; + default: + printf("Unsupported COREPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE+PIXIS_VSPEED0); + tmp = (tmp & 0xE0) | (val & 0x1F); + out8(PIXIS_BASE+PIXIS_VSPEED0,tmp); + + return 1; +} + +void read_from_px_regs(int set) +{ + u8 tmp, mask = 0x1C; + tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0); + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); +} + +void read_from_px_regs_altbank(int set) +{ + u8 tmp, mask = 0x04; + tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1); + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); +} + +void set_altbank(void) +{ + u8 tmp; + tmp = in8(PIXIS_BASE+PIXIS_VBOOT); + tmp ^= 0x40; + out8(PIXIS_BASE+PIXIS_VBOOT,tmp); + } + + +void set_px_go(void) +{ + u8 tmp; + tmp = in8(PIXIS_BASE+PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE+PIXIS_VCTL,tmp); + tmp = in8(PIXIS_BASE+PIXIS_VCTL); + tmp = tmp | 0x01; + out8(PIXIS_BASE+PIXIS_VCTL,tmp); +} + +void set_px_go_with_watchdog(void) +{ + u8 tmp; + tmp = in8(PIXIS_BASE+PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE+PIXIS_VCTL,tmp); + tmp = in8(PIXIS_BASE+PIXIS_VCTL); + tmp = tmp | 0x09; + out8(PIXIS_BASE+PIXIS_VCTL,tmp); +} + +/* This function takes the non-integral cpu:mpx pll ratio + * and converts it to an integer that can be used to assign + * FPGA register values. + * input: strptr i.e. argv[2] +*/ + +ulong strfractoint(uchar *strptr) +{ + int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0; + ulong intval =0, decval=0; + uchar intarr[3], decarr[3]; + + /* Assign the integer part to intarr[] + * If there is no decimal point i.e. + * if the ratio is an integral value + * simply create the intarr. + */ + i=0; + while(strptr[i] != 46) + { + if(strptr[i] == 0) + { + no_dec = 1; + break; /* Break from loop once the end of string is reached */ + } + + intarr[i] = strptr[i]; + i++; + } + + intarr_len = i; /* Assign length of integer part to intarr_len*/ + intarr[i] = '\0'; /* */ + + if(no_dec) + { + mulconst=10; /* Currently needed only for single digit corepll ratios */ + decval = 0; + } + else + { + j=0; + i++; /* Skipping the decimal point */ + while ((strptr[i] > 47) && (strptr[i] < 58)) + { + decarr[j] = strptr[i]; + i++; + j++; + } + + decarr_len = j; + decarr[j] = '\0'; + + mulconst=1; + for(i=0; i 1) + { + cmd = argv[1][1]; + switch(cmd) + { + case 'f': /* reset with frequency changed */ + + if (argc < 5) + goto my_usage; + + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10)); + if(val == 3) + { + printf("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } + else + goto my_usage; + + while(1); /* Not reached */ + + case 'l': + if(argv[2][1] == 'f') + { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); + if(val == 3) + { + printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + + } + else + goto my_usage; + + while(1); /* Not reached */ + } + else /* Reset from next bank without changing frequencies */ + { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + } + + default: + goto my_usage; + } +my_usage: + printf("\nUsage: reset cf \n"); + printf(" reset altbank [cf ]\n"); + printf("For example: reset cf 40 2.5 10\n"); + printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); + return; + } + else + out8(PIXIS_BASE+PIXIS_RST,0); + +#endif /* !CONFIG_MPC8641HPCN */ + + while(1); /* not reached */ +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Get timebase clock frequency + */ +unsigned long get_tbclk(void) +{ + sys_info_t sys_info; + + get_sys_info(&sys_info); + return ((sys_info.freqSystemBus + 3L) / 4L); + +} + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_WATCHDOG) +void +watchdog_reset(void) +{ + +} +#endif /* CONFIG_WATCHDOG */ + +/* ------------------------------------------------------------------------- */ + +#if defined(CONFIG_DDR_ECC) +void dma_init(void) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + + dma->satr0 = 0x00040000; + dma->datr0 = 0x00040000; + asm("sync; isync"); + return; +} + +uint dma_check(void) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + volatile uint status = dma->sr0; + + /* While the channel is busy, spin */ + while((status & 4) == 4) { + status = dma->sr0; + } + + if (status != 0) { + printf ("DMA Error: status = %x\n", status); + } + return status; +} + +int dma_xfer(void *dest, uint count, void *src) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; + + dma->dar0 = (uint) dest; + dma->sar0 = (uint) src; + dma->bcr0 = count; + dma->mr0 = 0xf000004; + asm("sync;isync"); + dma->mr0 = 0xf000005; + asm("sync;isync"); + return dma_check(); +} +#endif /* CONFIG_DDR_ECC */ + + +#ifdef CONFIG_OF_FLAT_TREE +void ft_cpu_setup(void *blob, bd_t *bd) +{ + u32 *p; + ulong clock; + int len; + + clock = bd->bi_busfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#if defined(CONFIG_MPC86XX_TSEC1) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); + memcpy(p, bd->bi_enetaddr, 6); +#endif + +#if defined(CONFIG_MPC86XX_TSEC2) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); + memcpy(p, bd->bi_enet1addr, 6); +#endif + +#if defined(CONFIG_MPC86XX_TSEC3) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/address", &len); + memcpy(p, bd->bi_enet2addr, 6); +#endif + +#if defined(CONFIG_MPC86XX_TSEC4) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/address", &len); + memcpy(p, bd->bi_enet3addr, 6); +#endif + +} +#endif diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c new file mode 100644 index 000000000..582ac6ba9 --- /dev/null +++ b/cpu/mpc86xx/cpu_init.c @@ -0,0 +1,134 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * cpu_init.c - low level cpu init + */ + +#include +#include + +/* + * Breathe some life into the CPU... + * + * Set up the memory map + * initialize a bunch of registers + */ + +void cpu_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *memctl = &immap->im_lbc; + //u8 val; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary + * addresses - these have to be modified later when FLASH size + * has been determined + */ + +#if defined(CFG_OR0_REMAP) + memctl->or0 = CFG_OR0_REMAP; +#endif +#if defined(CFG_OR1_REMAP) + memctl->or1 = CFG_OR1_REMAP; +#endif + + /* now restrict to preliminary range */ +#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) + memctl->br0 = CFG_BR0_PRELIM; + memctl->or0 = CFG_OR0_PRELIM; +#endif + +#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) + memctl->or1 = CFG_OR1_PRELIM; + memctl->br1 = CFG_BR1_PRELIM; +#endif + + //#if !defined(CONFIG_MPC86xx) +#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) + memctl->or2 = CFG_OR2_PRELIM; + memctl->br2 = CFG_BR2_PRELIM; +#endif + //#endif + +#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) + memctl->or3 = CFG_OR3_PRELIM; + memctl->br3 = CFG_BR3_PRELIM; +#endif + +#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) + memctl->or4 = CFG_OR4_PRELIM; + memctl->br4 = CFG_BR4_PRELIM; +#endif + +#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) + memctl->or5 = CFG_OR5_PRELIM; + memctl->br5 = CFG_BR5_PRELIM; +#endif + +#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) + memctl->or6 = CFG_OR6_PRELIM; + memctl->br6 = CFG_BR6_PRELIM; +#endif + +#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) + memctl->or7 = CFG_OR7_PRELIM; + memctl->br7 = CFG_BR7_PRELIM; +#endif + + /* enable the timebase bit in HID0 */ + set_hid0(get_hid0() | 0x4000000); + + /* enable SYNCBE | ABE bits in HID1 */ + set_hid1(get_hid1() | 0x00000C00); + + /* Since the bats have been set up at this point and + * the local bus registers have been initialized, we + * turn on the WDEN bit in PIXIS_VCTL + */ +/* val = in8(PIXIS_BASE+PIXIS_VCTL); */ + /* Set the WDEN */ +/* val |= 0x08; */ +/* out8(PIXIS_BASE+PIXIS_VCTL,val); */ +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ + return (0); +} + + + + + diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c new file mode 100644 index 000000000..c5d4642b9 --- /dev/null +++ b/cpu/mpc86xx/i2c.c @@ -0,0 +1,273 @@ +/* + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao + * Adapted for Motorola 85xx chip. + * + * (C) Copyright 2003 + * Gleb Natapov + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk + * + * Modified for MPC86xx by Jeff Brown (jeffrey@freescale.com) + * + * Hardware I2C driver for MPC107 PCI bridge. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_HARD_I2C +#include + +#define TIMEOUT (CFG_HZ/4) + +#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3100)) + +#define I2CADR &I2C_Addr[0] +#define I2CFDR &I2C_Addr[4] +#define I2CCCR &I2C_Addr[8] +#define I2CCSR &I2C_Addr[12] +#define I2CCDR &I2C_Addr[16] +#define I2CDFSRR &I2C_Addr[20] + +#define I2C_READ 1 +#define I2C_WRITE 0 + +void +i2c_init(int speed, int slaveadd) +{ + /* stop I2C controller */ + writeb(0x0, I2CCCR); + + /* set clock */ + writeb(0x3f, I2CFDR); + + /* set default filter */ + writeb(0x10,I2CDFSRR); + + /* write slave address */ + writeb(slaveadd, I2CADR); + + /* clear status register */ + writeb(0x0, I2CCSR); + + /* start I2C controller */ + writeb(MPC86xx_I2CCR_MEN, I2CCCR); +} + +static __inline__ int +i2c_wait4bus (void) +{ + ulong timeval = get_timer (0); + + // debug("I2C: Wait for bus\n"); + while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { + if (get_timer (timeval) > TIMEOUT) { + return -1; + } + } + + return 0; +} + +static __inline__ int +i2c_wait (int write) +{ + u32 csr; + ulong timeval = get_timer (0); + + do { + csr = readb(I2CCSR); + + if (!(csr & MPC86xx_I2CSR_MIF)) + continue; + + writeb(0x0, I2CCSR); + + if (csr & MPC86xx_I2CSR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & MPC86xx_I2CSR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & MPC86xx_I2CSR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } + + return 0; + } while (get_timer (timeval) < TIMEOUT); + + debug("i2c_wait: timed out\n"); + return -1; +} + +static __inline__ int +i2c_write_addr (u8 dev, u8 dir, int rsta) +{ + // debug("I2C: Write Addr\n"); + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX | + (rsta?MPC86xx_I2CCR_RSTA:0), + I2CCCR); + + writeb((dev << 1) | dir, I2CCDR); + + if (i2c_wait (I2C_WRITE) < 0) + return 0; + + return 1; +} + +static __inline__ int +__i2c_write (u8 *data, int length) +{ + int i; + // debug("I2C: __i2c_write\n"); + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX, + I2CCCR); + + for (i=0; i < length; i++) { + writeb(data[i], I2CCDR); + + if (i2c_wait (I2C_WRITE) < 0) + break; + } + + return i; +} + +static __inline__ int +__i2c_read (u8 *data, int length) +{ + int i; + + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | + ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), + I2CCCR); + + /* dummy read */ + readb(I2CCDR); + // debug("length = %d\n", length); + + for (i=0; i < length; i++) { + if (i2c_wait (I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | + MPC86xx_I2CCR_TXAK, + I2CCCR); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR); + + // debug("I2CCR = 0x%08x\n", readb(I2CCCR)); + data[i] = readb(I2CCDR); + // debug("data[i] = 0x%08x\n", data[i]); + } + // debug("Returning i = %d\n", i); + return i; +} + +int +i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr (dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read (data, length); + + exit: + writeb(MPC86xx_I2CCR_MEN, I2CCCR); + + return !(i == length); +} + +int +i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write (data, length); + + exit: + writeb(MPC86xx_I2CCR_MEN, I2CCCR); + + return !(i == length); +} + +int i2c_probe (uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an back. + */ + udelay(10000); + + return i2c_read (chip, 0, 1, (char *)&tmp, 1); +} + +uchar i2c_reg_read (uchar i2c_addr, uchar reg) +{ + char buf[1]; + + i2c_read (i2c_addr, reg, 1, buf, 1); + + return (buf[0]); +} + +void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write (i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c new file mode 100644 index 000000000..759a30f9f --- /dev/null +++ b/cpu/mpc86xx/interrupts.c @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 (440 port) + * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com + * + * (C) Copyright 2003 Motorola Inc. (MPC85xx port) + * Xianghua Xiao (X.Xiao@motorola.com) + * + * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) + * Jeff Brown (Jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ + + +unsigned long timestamp; + +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + + asm volatile ("mfmsr %0":"=r" (msr):); + + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + asm volatile ("mtmsr %0"::"r" (msr)); +} + +static __inline__ unsigned long get_dec (void) +{ + unsigned long val; + + asm volatile ("mfdec %0":"=r" (val):); + + return val; +} + + +static __inline__ void set_dec (unsigned long val) +{ + if (val) + asm volatile ("mtdec %0"::"r" (val)); +} + +/* interrupt is not supported yet */ +int interrupt_init_cpu (unsigned *decrementer_count) +{ + return (0); +} + + +int interrupt_init (void) +{ + int ret; + + /* call cpu specific function from $(CPU)/interrupts.c */ + ret = interrupt_init_cpu (&decrementer_count); + + if (ret) + return ret; + + decrementer_count = get_tbclk()/CFG_HZ; + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); + + set_dec (decrementer_count); + + set_msr (get_msr () | MSR_EE); + + debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); + + return (0); +} + + +void enable_interrupts (void) +{ + set_msr (get_msr () | MSR_EE); +} + +/* returns flag if MSR_EE was set before */ +int disable_interrupts (void) +{ + ulong msr = get_msr (); + + set_msr (msr & ~MSR_EE); + return ((msr & MSR_EE) != 0); +} + + +void increment_timestamp(void) +{ + timestamp++; +} + +/* + * timer_interrupt - gets called when the decrementer overflows, + * with interrupts disabled. + * Trivial implementation - no need to be really accurate. + */ +void +timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} + + +void timer_interrupt (struct pt_regs *regs) +{ + /* call cpu specific function from $(CPU)/interrupts.c */ + timer_interrupt_cpu (regs); + + timestamp++; + + ppcDcbf(×tamp); + + /* Restore Decrementer Count */ + set_dec (decrementer_count); + +#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) + if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) + WATCHDOG_RESET (); +#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ + +#ifdef CONFIG_STATUS_LED + status_led_tick (timestamp); +#endif /* CONFIG_STATUS_LED */ + +#ifdef CONFIG_SHOW_ACTIVITY + board_show_activity (timestamp); +#endif /* CONFIG_SHOW_ACTIVITY */ + + +} + +void reset_timer (void) +{ + timestamp = 0; +} + +ulong get_timer (ulong base) +{ + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* + * Install and free a interrupt handler. Not implemented yet. + */ + +void +irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +{ + return; +} + +void +irq_free_handler(int vec) +{ + return; +} + + + +/******************************************************************************* + * + * irqinfo - print information about PCI devices,not implemented. + * + */ +int +do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf ("\nInterrupt-unsupported:\n"); + + return 0; +} + +/* + * Handle external interrupts + */ +void +external_interrupt(struct pt_regs *regs) +{ + puts("external_interrupt (oops!)\n"); +} + + + + + + diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c new file mode 100644 index 000000000..9cf5f7ca9 --- /dev/null +++ b/cpu/mpc86xx/pci.c @@ -0,0 +1,196 @@ +/* + * Copyright 2005 Freescale Semiconductor. + * Ed Swarthout (ed.swarthout@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PEX Configuration space access support for MPC85xx PEX Bridge + */ +#include +#include + + +#if defined(CONFIG_PCI) + +void +pci_mpc86xx_init(struct pci_controller *hose) +{ + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_host = (host1_agent == 2) || (host1_agent == 3); + + u16 reg16, reg16_1, reg16_2, reg16_3; + u32 reg32, i; + + ulong addr, data; + + + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + + if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + printf ("PCI-EXPRESS 1: Configured as %s \n", + pex1_agent ? "Agent" : "Host"); + printf (" Scanning PCI bus"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + } + debug ("\n"); + } + + + hose->first_busno = 0; + hose->last_busno = 0x7f; + + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + pci_setup_indirect(hose, + (CFG_IMMR+0x8000), + (CFG_IMMR+0x8004)); + + /* + * Hose scan. + */ + pci_register_hose(hose); + + //#define MPC8548_REV1_PEX12_ERRATA +#ifdef MPC8548_REV1_PEX12_ERRATA + /* can only read/write 4 bytes */ + pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®32); + printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32); + + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®32); + reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32); +#else + pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16); + debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16); + pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16); + debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16); + + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); + debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16); + + +#endif + + /* + * Clear non-reserved bits in status register. + */ + // pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + // pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + + pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pex1->powar1 = 0x8004401c; /* 512M MEM space */ + pex1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pex1->potear1 = 0x00000000; + + pex1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pex1->powar2 = 0x80088017; /* 16M IO space */ + pex1->potar2 = 0x00000000; + pex1->potear2 = 0x00000000; + + + if (!pex1->piwar1) { + pex1->pitar1 = 0x00000000; + pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff; + pex1->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, + * Snoop R/W, 2G */ + } + + pex1->pitar2 = 0x00000000; + pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff; + pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, + + + +/* if (pex1_host) { */ +/* #ifdef MPC8548_REV1_PEX12_ERRATA */ +/* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */ +/* #else */ + + + + *(u32 *)(0xf8008000)= 0x80000000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + + + pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); +/* #endif */ + + + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + + + + hose->last_busno = pci_hose_scan(hose); + hose->last_busno = 0x21; + debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); + debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); + + + printf("....PCI scan & enumeration done\n"); + +/* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */ +/* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */ + +/* if (hose->last_busno < 1) { */ +/* hose->last_busno=1; /\*Hack*\/ */ +/* } else { */ +/* hose->last_busno = 0; */ +/* } */ +/*}*/ +/* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, ®32); */ +/* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */ + + +} +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/resetvec.S b/cpu/mpc86xx/resetvec.S new file mode 100644 index 000000000..9a552f662 --- /dev/null +++ b/cpu/mpc86xx/resetvec.S @@ -0,0 +1,2 @@ + .section .resetvec,"ax" + b _start diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c new file mode 100644 index 000000000..9c07f200f --- /dev/null +++ b/cpu/mpc86xx/spd_sdram.c @@ -0,0 +1,1017 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void dma_init(void); +extern uint dma_check(void); +extern int dma_xfer(void *dest, uint count, void *src); +#endif + +#ifdef CONFIG_SPD_EEPROM + +#ifndef CFG_READ_SPD +#define CFG_READ_SPD i2c_read +#endif + +/* + * Convert picoseconds into clock cycles (rounding up if needed). + */ + +int +picos_to_clk(int picos) +{ + int clks; + + clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); + if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks++; + } + + return clks; +} + + +/* + * Calculate the Density of each Physical Rank. + * Returned size is in bytes. + * + * Study these table from Byte 31 of JEDEC SPD Spec. + * + * DDR I DDR II + * Bit Size Size + * --- ----- ------ + * 7 high 512MB 512MB + * 6 256MB 256MB + * 5 128MB 128MB + * 4 64MB 16GB + * 3 32MB 8GB + * 2 16MB 4GB + * 1 2GB 2GB + * 0 low 1GB 1GB + * + * Reorder Table to be linear by stripping the bottom + * 2 or 5 bits off and shifting them up to the top. + */ + +unsigned int +compute_banksize(unsigned int mem_type, unsigned char row_dens) +{ + unsigned int bsize; + + if (mem_type == SPD_MEMTYPE_DDR) { + /* Bottom 2 bits up to the top. */ + bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; + debug("DDR: DDR I rank density = 0x%08x\n", bsize); + } else { + /* Bottom 5 bits up to the top. */ + bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27; + debug("DDR: DDR II rank density = 0x%08x\n", bsize); + } + return bsize; +} + + +/* + * Convert a two-nibble BCD value into a cycle time. + * While the spec calls for nano-seconds, picos are returned. + * + * This implements the tables for bytes 9, 23 and 25 for both + * DDR I and II. No allowance for distinguishing the invalid + * fields absent for DDR I yet present in DDR II is made. + * (That is, cycle times of .25, .33, .66 and .75 ns are + * allowed for both DDR II and I.) + */ + +unsigned int +convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) +{ + /* + * Table look up the lower nibble, allow DDR I & II. + */ + unsigned int tenths_ps[16] = { + 0, + 100, + 200, + 300, + 400, + 500, + 600, + 700, + 800, + 900, + 250, + 330, /* FIXME: Is 333 better/valid? */ + 660, /* FIXME: Is 667 better/valid? */ + 750, + 0, /* undefined */ + 0 /* undefined */ + }; + + unsigned int whole_ns = (spd_val & 0xF0) >> 4; + unsigned int tenth_ns = spd_val & 0x0F; + unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; + + return ps; +} + + +long int +spd_sdram(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_gur_t *gur = &immap->im_gur; + spd_eeprom_t spd; + unsigned int n_ranks; + unsigned int rank_density; + unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_cfg, mode_odt_enable; + unsigned int dqs_cfg; + unsigned char twr_clk, twtr_clk, twr_auto_clk; + unsigned int tCKmin_ps, tCKmax_ps; + unsigned int max_data_rate, effective_data_rate; + unsigned int busfreq; + unsigned sdram_cfg_1; + unsigned int memsize; + unsigned char caslat, caslat_ctrl; + unsigned int trfc, trfc_clk, trfc_low, trfc_high; + unsigned int trcd_clk; + unsigned int trtp_clk; + unsigned char cke_min_clk; + unsigned char add_lat; + unsigned char wr_lat; + unsigned char wr_data_delay; + unsigned char four_act; + unsigned char cpo; + unsigned char burst_len; + unsigned int mode_caslat; + unsigned char sdram_type; + unsigned char d_init; + + + unsigned int law_size; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + + /* + * Read SPD information. + */ + + CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd)); + + /* + * Check for supported memory module types. + */ + if (spd.mem_type != SPD_MEMTYPE_DDR && + spd.mem_type != SPD_MEMTYPE_DDR2) { + printf("Unable to locate DDR I or DDR II module.\n" + " Fundamental memory type is 0x%0x\n", + spd.mem_type); + return 0; + } + + /* + * These test gloss over DDR I and II differences in interpretation + * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks + * are not supported on DDR I; and not encoded on DDR II. + * + * Also note that the 8548 controller can support: + * 12 <= nrow <= 16 + * and + * 8 <= ncol <= 11 (still, for DDR) + * 6 <= ncol <= 9 (for FCRAM) + */ + if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { + printf("DDR: Unsupported number of Row Addr lines: %d.\n", + spd.nrow_addr); + return 0; + } + if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { + printf("DDR: Unsupported number of Column Addr lines: %d.\n", + spd.ncol_addr); + return 0; + } + + /* + * Determine the number of physical banks controlled by + * different Chip Select signals. This is not quite the + * same as the number of DIMM modules on the board. Feh. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + n_ranks = spd.nrows; + } else { + n_ranks = (spd.nrows & 0x7) + 1; + } + + debug("DDR: number of ranks = %d\n", n_ranks); + + if (n_ranks > 2) { + printf("DDR: Only 2 chip selects are supported: %d\n", + n_ranks); + return 0; + } + + /* + * Adjust DDR II IO voltage biasing. It just makes it work. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + gur->ddrioovcr = (0 + | 0x80000000 /* Enable */ + | 0x10000000 /* VSEL to 1.8V */ + ); + } + + /* + * Determine the size of each Rank in bytes. + */ + rank_density = compute_banksize(spd.mem_type, spd.row_dens); + + + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr1->cs0_bnds = (rank_density >> 24) - 1; + + /* + * ODT configuration recommendation from DDR Controller Chapter. + */ + odt_rd_cfg = 0; /* Never assert ODT */ + odt_wr_cfg = 0; /* Never assert ODT */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ + } + + ddr1->cs0_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("\n"); + debug("DDR: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr1->cs0_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg + */ + ddr1->cs1_bnds = ( (rank_density >> 8) + | ((rank_density >> (24 - 1)) - 1) ); + ddr1->cs1_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs1_bnds = 0x%08x\n", ddr1->cs1_bnds); + debug("DDR: cs1_config = 0x%08x\n", ddr1->cs1_config); + } + + + /* + * Find the largest CAS by locating the highest 1 bit + * in the spd.cas_lat field. Translate it to a DDR + * controller field value: + * + * CAS Lat DDR I DDR II Ctrl + * Clocks SPD Bit SPD Bit Value + * ------- ------- ------- ----- + * 1.0 0 0001 + * 1.5 1 0010 + * 2.0 2 2 0011 + * 2.5 3 0100 + * 3.0 4 3 0101 + * 3.5 5 0110 + * 4.0 4 0111 + * 4.5 1000 + * 5.0 5 1001 + */ + caslat = __ilog2(spd.cas_lat); + if ((spd.mem_type == SPD_MEMTYPE_DDR) + && (caslat > 5)) { + printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); + return 0; + + } else if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (caslat < 2 || caslat > 5)) { + printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", + spd.cas_lat); + return 0; + } + debug("DDR: caslat SPD bit is %d\n", caslat); + + /* + * Calculate the Maximum Data Rate based on the Minimum Cycle time. + * The SPD clk_cycle field (tCKmin) is measured in tenths of + * nanoseconds and represented as BCD. + */ + tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle); + debug("DDR: tCKmin = %d ps\n", tCKmin_ps); + + /* + * Double-data rate, scaled 1000 to picoseconds, and back down to MHz. + */ + max_data_rate = 2 * 1000 * 1000 / tCKmin_ps; + debug("DDR: Module max data rate = %d Mhz\n", max_data_rate); + + + /* + * Adjust the CAS Latency to allow for bus speeds that + * are slower than the DDR module. + */ + busfreq = get_bus_freq(0) / 1000000; /* MHz */ + + effective_data_rate = max_data_rate; + if (busfreq < 90) { + /* DDR rate out-of-range */ + puts("DDR: platform frequency is not fit for DDR rate\n"); + return 0; + + } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) { + /* + * busfreq 90~230 range, treated as DDR 200. + */ + effective_data_rate = 200; + if (spd.clk_cycle3 == 0xa0) /* 10 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0xa0) + caslat--; + + } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) { + /* + * busfreq 230~280 range, treated as DDR 266. + */ + effective_data_rate = 266; + if (spd.clk_cycle3 == 0x75) /* 7.5 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x75) + caslat--; + + } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) { + /* + * busfreq 280~350 range, treated as DDR 333. + */ + effective_data_rate = 333; + if (spd.clk_cycle3 == 0x60) /* 6.0 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x60) + caslat--; + + } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) { + /* + * busfreq 350~460 range, treated as DDR 400. + */ + effective_data_rate = 400; + if (spd.clk_cycle3 == 0x50) /* 5.0 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x50) + caslat--; + + } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) { + /* + * busfreq 460~560 range, treated as DDR 533. + */ + effective_data_rate = 533; + if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x3D) + caslat--; + + } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) { + /* + * busfreq 560~700 range, treated as DDR 667. + */ + effective_data_rate = 667; + if (spd.clk_cycle3 == 0x30) /* 3.0 ns */ + caslat -= 2; + else if (spd.clk_cycle2 == 0x30) + caslat--; + + } else if (700 <= busfreq) { + /* + * DDR rate out-of-range + */ + printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", + busfreq, max_data_rate); + return 0; + } + + + /* + * Convert caslat clocks to DDR controller value. + * Force caslat_ctrl to be DDR Controller field-sized. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + caslat_ctrl = (caslat + 1) & 0x07; + } else { + caslat_ctrl = (2 * caslat - 1) & 0x0f; + } + + debug("DDR: effective data rate is %d MHz\n", effective_data_rate); + debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", + caslat, caslat_ctrl); + + /* + * Timing Config 0. + * Avoid writing for DDR I. The new PQ38 DDR controller + * dreams up non-zero default values to be backwards compatible. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + unsigned char taxpd_clk = 8; /* By the book. */ + unsigned char tmrd_clk = 2; /* By the book. */ + unsigned char act_pd_exit = 2; /* Empirical? */ + unsigned char pre_pd_exit = 6; /* Empirical? */ + + ddr1->timing_cfg_0 = (0 + | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ + | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ + | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ + | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ + ); + debug("DDR: timing_cfg_0 = 0x%08x\n", ddr1->timing_cfg_0); + + } else { + } + + + /* + * Some Timing Config 1 values now. + * Sneak Extended Refresh Recovery in here too. + */ + + /* + * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value. + * For DDR II, they are bytes 36 and 37, in quarter nanos. + */ + + if (spd.mem_type == SPD_MEMTYPE_DDR) { + twr_clk = 3; /* Clocks */ + twtr_clk = 1; /* Clocks */ + } else { + twr_clk = picos_to_clk(spd.twr * 250); + twtr_clk = picos_to_clk(spd.twtr * 250); + } + + /* + * Calculate Trfc, in picos. + * DDR I: Byte 42 straight up in ns. + * DDR II: Byte 40 and 42 swizzled some, in ns. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + trfc = spd.trfc * 1000; /* up to ps */ + } else { + unsigned int byte40_table_ps[8] = { + 0, + 250, + 330, + 500, + 660, + 750, + 0, + 0 + }; + + trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 + + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; + } + trfc_clk = picos_to_clk(trfc); + + /* + * Trcd, Byte 29, from quarter nanos to ps and clocks. + */ + trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; + + /* + * Convert trfc_clk to DDR controller fields. DDR I should + * fit in the REFREC field (16-19) of TIMING_CFG_1, but the + * 8548 controller has an extended REFREC field of three bits. + * The controller automatically adds 8 clocks to this value, + * so preadjust it down 8 first before splitting it up. + */ + trfc_low = (trfc_clk - 8) & 0xf; + trfc_high = ((trfc_clk - 8) >> 4) & 0x3; + + /* + * Sneak in some Extended Refresh Recovery. + */ + ddr1->ext_refrec = (trfc_high << 16); + debug("DDR: ext_refrec = 0x%08x\n", ddr1->ext_refrec); + + ddr1->timing_cfg_1 = + (0 + | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ + | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ + | (trcd_clk << 20) /* ACTTORW */ + | (caslat_ctrl << 16) /* CASLAT */ + | (trfc_low << 12) /* REFEC */ + | ((twr_clk & 0x07) << 8) /* WRRREC */ + | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */ + | ((twtr_clk & 0x07) << 0) /* WRTORD */ + ); + + debug("DDR: timing_cfg_1 = 0x%08x\n", ddr1->timing_cfg_1); + + + /* + * Timing_Config_2 + * Was: 0x00000800; + */ + + /* + * Additive Latency + * For DDR I, 0. + * For DDR II, with ODT enabled, use "a value" less than ACTTORW, + * which comes from Trcd, and also note that: + * add_lat + caslat must be >= 4 + */ + add_lat = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (odt_wr_cfg || odt_rd_cfg) + && (caslat < 4)) { + add_lat = 4 - caslat; + if (add_lat > trcd_clk) { + add_lat = trcd_clk - 1; + } + } + + /* + * Write Data Delay + * Historically 0x2 == 4/8 clock delay. + * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. + */ + wr_data_delay = 3; + + /* + * Write Latency + * Read to Precharge + * Minimum CKE Pulse Width. + * Four Activate Window + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + /* + * This is a lie. It should really be 1, but if it is + * set to 1, bits overlap into the old controller's + * otherwise unused ACSM field. If we leave it 0, then + * the HW will magically treat it as 1 for DDR 1. Oh Yea. + */ + wr_lat = 0; + + trtp_clk = 2; /* By the book. */ + cke_min_clk = 1; /* By the book. */ + four_act = 1; /* By the book. */ + + } else { + wr_lat = caslat - 1; + + /* Convert SPD value from quarter nanos to picos. */ + trtp_clk = picos_to_clk(spd.trtp * 250); + + cke_min_clk = 3; /* By the book. */ + four_act = picos_to_clk(37500); /* By the book. 1k pages? */ + } + + /* + * Empirically set ~MCAS-to-preamble override for DDR 2. + * Your milage will vary. + */ + cpo = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (effective_data_rate == 266 || effective_data_rate == 333) { + cpo = 0x7; /* READ_LAT + 5/4 */ + } else if (effective_data_rate == 400) { + cpo = 0x9; /* READ_LAT + 7/4 */ + } else { + /* Pure speculation */ + cpo = 0xb; + } + } + + ddr1->timing_cfg_2 = (0 + | ((add_lat & 0x7) << 28) /* ADD_LAT */ + | ((cpo & 0x1f) << 23) /* CPO */ + | ((wr_lat & 0x7) << 19) /* WR_LAT */ + | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ + | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ + | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ + | ((four_act & 0x1f) << 0) /* FOUR_ACT */ + ); + + debug("DDR: timing_cfg_2 = 0x%08x\n", ddr1->timing_cfg_2); + + + /* + * Determine the Mode Register Set. + * + * This is nominally part specific, but it appears to be + * consistent for all DDR I devices, and for all DDR II devices. + * + * caslat must be programmed + * burst length is always 4 + * burst type is sequential + * + * For DDR I: + * operating mode is "normal" + * + * For DDR II: + * other stuff + */ + + mode_caslat = 0; + + /* + * Table lookup from DDR I or II Device Operation Specs. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + if (1 <= caslat && caslat <= 4) { + unsigned char mode_caslat_table[4] = { + 0x5, /* 1.5 clocks */ + 0x2, /* 2.0 clocks */ + 0x6, /* 2.5 clocks */ + 0x3 /* 3.0 clocks */ + }; + mode_caslat = mode_caslat_table[caslat - 1]; + } else { + puts("DDR I: Only CAS Latencies of 1.5, 2.0, " + "2.5 and 3.0 clocks are supported.\n"); + return 0; + } + + } else { + if (2 <= caslat && caslat <= 5) { + mode_caslat = caslat; + } else { + puts("DDR II: Only CAS Latencies of 2.0, 3.0, " + "4.0 and 5.0 clocks are supported.\n"); + return 0; + } + } + + /* + * Encoded Burst Lenght of 4. + */ + burst_len = 2; /* Fiat. */ + + if (spd.mem_type == SPD_MEMTYPE_DDR) { + twr_auto_clk = 0; /* Historical */ + } else { + /* + * Determine tCK max in picos. Grab tWR and convert to picos. + * Auto-precharge write recovery is: + * WR = roundup(tWR_ns/tCKmax_ns). + * + * Ponder: Is twr_auto_clk different than twr_clk? + */ + tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax); + twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps; + } + + + /* + * Mode Reg in bits 16 ~ 31, + * Extended Mode Reg 1 in bits 0 ~ 15. + */ + mode_odt_enable = 0x0; /* Default disabled */ + if (odt_wr_cfg || odt_rd_cfg) { + /* + * Bits 6 and 2 in Extended MRS(1) + * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. + * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. + */ + mode_odt_enable = 0x40; /* 150 Ohm */ + } + + ddr1->sdram_mode_1 = + (0 + | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ + | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ + | (twr_auto_clk << 9) /* Write Recovery Autopre */ + | (mode_caslat << 4) /* caslat */ + | (burst_len << 0) /* Burst length */ + ); + + debug("DDR: sdram_mode = 0x%08x\n", ddr1->sdram_mode_1); + + + /* + * Clear EMRS2 and EMRS3. + */ + ddr1->sdram_mode_2 = 0; + debug("DDR: sdram_mode_2 = 0x%08x\n", ddr1->sdram_mode_2); + + + /* + * Determine Refresh Rate. Ignore self refresh bit on DDR I. + * Table from SPD Spec, Byte 12, converted to picoseconds and + * filled in with "default" normal values. + */ + { + unsigned int refresh_clk; + unsigned int refresh_time_ns[8] = { + 15625000, /* 0 Normal 1.00x */ + 3900000, /* 1 Reduced .25x */ + 7800000, /* 2 Extended .50x */ + 31300000, /* 3 Extended 2.00x */ + 62500000, /* 4 Extended 4.00x */ + 125000000, /* 5 Extended 8.00x */ + 15625000, /* 6 Normal 1.00x filler */ + 15625000, /* 7 Normal 1.00x filler */ + }; + + refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]); + + /* + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 + */ + ddr1->sdram_interval = + (0 + | (refresh_clk & 0x3fff) << 16 + | 0x100 + ); + debug("DDR: sdram_interval = 0x%08x\n", ddr1->sdram_interval); + } + + /* + * Is this an ECC DDR chip? + * But don't mess with it if the DDR controller will init mem. + */ +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + if (spd.config == 0x02) { + ddr1->err_disable = 0x0000000d; + ddr1->err_sbe = 0x00ff0000; + } + debug("DDR: err_disable = 0x%08x\n", ddr1->err_disable); + debug("DDR: err_sbe = 0x%08x\n", ddr1->err_sbe); +#endif + + asm("sync;isync"); + udelay(500); + + /* + * SDRAM Cfg 2 + */ + + /* + * When ODT is enabled, Chap 9 suggests asserting ODT to + * internal IOs only during reads. + */ + odt_cfg = 0; + if (odt_rd_cfg | odt_wr_cfg) { + odt_cfg = 0x2; /* ODT to IOs during reads */ + } + + /* + * Try to use differential DQS with DDR II. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + dqs_cfg = 0; /* No Differential DQS for DDR I */ + } else { + dqs_cfg = 0x1; /* Differential DQS for DDR II */ + } + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Use the DDR controller to auto initialize memory. + */ + d_init = 1; + ddr1->sdram_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr1->sdram_data_init); +#else + /* + * Memory will be initialized via DMA, or not at all. + */ + d_init = 0; +#endif + + ddr1->sdram_cfg_2 = (0 + | (dqs_cfg << 26) /* Differential DQS */ + | (odt_cfg << 21) /* ODT */ + | (d_init << 4) /* D_INIT auto init DDR */ + ); + + debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr1->sdram_cfg_2); + + +#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL + { + unsigned char clk_adjust; + + /* + * Setup the clock control. + * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 + * SDRAM_CLK_CNTL[5-7] = Clock Adjust + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + clk_adjust = 0x6; + } else { + clk_adjust = 0x7; + } + + ddr1->sdram_clk_cntl = (0 + | 0x80000000 + | (clk_adjust << 23) + ); + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr1->sdram_clk_cntl); + } +#endif + + /* + * Figure out the settings for the sdram_cfg register. + * Build up the entire register in 'sdram_cfg' before writing + * since the write into the register will actually enable the + * memory controller; all settings must be done before enabling. + * + * sdram_cfg[0] = 1 (ddr sdram logic enable) + * sdram_cfg[1] = 1 (self-refresh-enable) + * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) + * 010 DDR 1 SDRAM + * 011 DDR 2 SDRAM + */ + sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; + sdram_cfg_1 = (0 + | (1 << 31) /* Enable */ + | (1 << 30) /* Self refresh */ + | (sdram_type << 24) /* SDRAM type */ + ); + + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable + * A value of 0x26 indicates micron registered DIMMS (micron.com) + */ + if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) { + sdram_cfg_1 |= 0x10000000; /* RD_EN */ + } + +#if defined(CONFIG_DDR_ECC) + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ + if (spd.config == 0x02) { + sdram_cfg_1 |= 0x20000000; /* ECC_EN */ + } +#endif + + /* + * REV1 uses 1T timing. + * REV2 may use 1T or 2T as configured by the user. + */ + { + uint pvr = get_pvr(); + + if (pvr != PVR_85xx_REV1) { +#if defined(CONFIG_DDR_2T_TIMING) + /* + * Enable 2T timing by setting sdram_cfg[16]. + */ + sdram_cfg_1 |= 0x8000; /* 2T_EN */ +#endif + } + } + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + + /* + * Go! + */ + ddr1->sdram_cfg_1 = sdram_cfg_1; + + asm("sync;isync"); + udelay(500); + + debug("DDR: sdram_cfg = 0x%08x\n", ddr1->sdram_cfg_1); + + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + debug("DDR: memory initializing\n"); + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr1->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } + debug("DDR: memory initialized\n"); +#endif + + + /* + * Figure out memory size in Megabytes. + */ + memsize = n_ranks * rank_density / 0x100000; + + + /* + * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. + */ + law_size = 19 + __ilog2(memsize); + + /* + * Set up LAWBAR for all of DDR. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR + | (LAWAR_SIZE & law_size)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LARAR1=0x%08x\n", mcm->lawar1); + + + return memsize * 1024 * 1024; +} + +#endif /* CONFIG_SPD_EEPROM */ + + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + +/* + * Initialize all of memory for ECC, then enable errors. + */ + +void +ddr_enable_ecc(unsigned int dram_size) +{ + uint *p = 0; + uint i = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1= &immap->im_ddr1; + + dma_init(); + + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((unsigned int)p & 0x1f) == 0) { + ppcDcbz((unsigned long) p); + } + *p = (unsigned int)CONFIG_MEM_INIT_VALUE; + if (((unsigned int)p & 0x1c) == 0x1c) { + ppcDcbf((unsigned long) p); + } + } + + /* 8K */ + dma_xfer((uint *)0x2000, 0x2000, (uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000, 0x4000, (uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000, 0x8000, (uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000, 0x10000, (uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000, 0x20000, (uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000, 0x40000, (uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000, 0x80000, (uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); + } + + /* + * Enable errors for ECC. + */ + debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); + ddr1->err_disable = 0x00000000; + asm("sync;isync;msync"); + debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); +} + +#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c new file mode 100644 index 000000000..0f5a6388c --- /dev/null +++ b/cpu/mpc86xx/speed.c @@ -0,0 +1,248 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +unsigned long get_board_sys_clk(ulong dummy); +unsigned long get_sysclk_from_px_regs(void); + + +/* --------------------------------------------------------------- */ + +void get_sys_info (sys_info_t * sysInfo) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint plat_ratio, e600_ratio; + + plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio >>= 1; + + switch(plat_ratio) { + case 0x0: + sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; + break; + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x08: + case 0x09: + case 0x0a: + case 0x0c: + case 0x10: + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + break; + default: + sysInfo->freqSystemBus = 0; + break; + } + + // printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", sysInfo->freqSystemBus, plat_ratio); + e600_ratio = (gur->porpllsr) & 0x003f0000; + e600_ratio >>= 16; + switch(e600_ratio) { + case 0x10: + sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; + break; + case 0x19: + sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; + break; + case 0x20: + sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + break; + case 0x39: + sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; + break; + case 0x28: + sysInfo->freqProcessor = 4*sysInfo->freqSystemBus; + break; + case 0x1d: + sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2; + break; + default: + /* JB - Emulator workaround until real cop is plugged in */ + sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; + //sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + break; + } + // printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", sysInfo->freqProcessor, e600_ratio); + +} + + +/* ------------------------------------------------------------------------- */ + +/* + * Measure CPU clock speed (core clock GCLK1, GCLK2) + * + * (Approx. GCLK frequency in Hz) + */ + +int get_clocks (void) +{ + DECLARE_GLOBAL_DATA_PTR; + sys_info_t sys_info; + + get_sys_info (&sys_info); + gd->cpu_clk = sys_info.freqProcessor; + gd->bus_clk = sys_info.freqSystemBus; + + if(gd->cpu_clk != 0) return (0); + else return (1); +} + +/* ------------------------------------------------------------------------- */ +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + ulong val; + + sys_info_t sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqSystemBus; + + return val; +} + +unsigned long get_sysclk_from_px_regs() +{ + ulong val; + u8 vclkh,vclkl; + + vclkh = in8(PIXIS_BASE+PIXIS_VCLKH); + vclkl = in8(PIXIS_BASE+PIXIS_VCLKL); + + if((vclkh == 0x84) && (vclkl ==0x07)) + { + val = 33000000; + } + if((vclkh == 0x3F) && (vclkl ==0x20)) + { + val = 40000000; + } + if((vclkh == 0x3F) && (vclkl ==0x2A)) + { + val = 50000000; + } + if((vclkh == 0x24) && (vclkl ==0x04)) + { + val = 66000000; + } + if((vclkh == 0x3F) && (vclkl ==0x4B)) + { + val = 83000000; + } + if((vclkh == 0x3F) && (vclkl ==0x5C)) + { + val = 100000000; + } + if((vclkh == 0xDF) && (vclkl ==0x3B)) + { + val = 134000000; + } + if((vclkh == 0xDF) && (vclkl ==0x4B)) + { + val = 166000000; + } + + return val; +} + +/******* From MPC8641HPCN Design Workbook ************ + * + * get_board_sys_clk + * reads the FPGA on board for CONFIG_SYS_CLK_FREQ + * + ********************************************************/ + +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i, go_bit, rd_clks; + ulong val; + + go_bit = in8(PIXIS_BASE+PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE+PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if(go_bit) + { + if(rd_clks == 0x1c) + i = in8(PIXIS_BASE+PIXIS_AUX); + else + i = in8(PIXIS_BASE+PIXIS_SPD); + //val = get_sysclk_from_px_regs(); + } + else + i = in8(PIXIS_BASE+PIXIS_SPD); + + i &= 0x07; + + switch(i) + { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S new file mode 100644 index 000000000..531bd0c5f --- /dev/null +++ b/cpu/mpc86xx/start.S @@ -0,0 +1,1240 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Srikanth Srinivasan + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards + * + * + * The processor starts at 0xfff00100 and the code is executed + * from flash. The code is organized to be at an other address + * in memory, but as long we don't jump around before relocating. + * board_init lies at a quite high address and when the cpu has + * jumped there, everything is ok. + */ +#include +#include +#include + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* We don't want the MMU yet. +*/ +#undef MSR_KERNEL +/* Machine Check and Recoverable Interr. */ +#define MSR_KERNEL ( MSR_ME | MSR_RI ) + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + sync + + . = EXC_OFF_SYS_RESET + 0x10 + + .globl _start_warm +_start_warm: + li r21, BOOTFLAG_WARM /* Software reboot */ + b boot_warm + sync + + /* the boot code is located below the exception table */ + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) + STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) + STD_EXCEPTION(0x1400, DataTLBError, UnknownException) + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) + STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) + STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) + STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x2000 + +boot_cold: +boot_warm: + + /* if this is a multi-core system we need to check which cpu + * this is, if it is not cpu 0 send the cpu to the linux reset + * vector */ +#if (CONFIG_NUM_CPUS > 1) + mfspr r0, MSSCR0 + andi. r0, r0, 0x0020 + rlwinm r0,r0,27,31,31 + mtspr PIR, r0 + beq 1f + + bl secondary_cpu_setup +#endif + + /* disable everything */ +1: li r0, 0 + mtspr HID0, r0 + sync + mtmsr 0 + bl invalidate_bats + sync + +#ifdef CFG_L2 + /* init the L2 cache */ + addis r3, r0, L2_INIT@h + ori r3, r3, L2_INIT@l + sync + mtspr l2cr, r3 +#ifdef CONFIG_ALTIVEC + dssall +#endif + /* invalidate the L2 cache */ + bl l2cache_invalidate + sync +#endif + + /* + * Calculate absolute address in FLASH and jump there + *------------------------------------------------------*/ + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r3 + blr + +in_flash: + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable ! */ + /*------------------------------------------------------*/ + /* perform low-level init */ + + /* enable extended addressing */ + bl enable_ext_addr + + /* setup the bats */ + bl setup_bats + sync + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* setup ccsrbar */ + bl setup_ccsrbar +#endif + + /* setup the law entries */ + bl law_entry + sync + + /* Don't use this feature due to bug in 8641D PD4 */ + /* Disable ERD_DIS */ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x1008 + lwz r4, 0(r3) + oris r4, r4, 0x4000 + stw r4, 0(r3) + sync + +#if (EMULATOR_RUN == 1) + /* On the emulator we want to adjust these ASAP */ + /* otherwise things are sloooow */ + /* Setup OR0 (LALE FIX)*/ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x5004 + li r4, 0x0FF3 + stw r4, 0(r3) + sync + + /* Setup LCRR */ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x50D4 + lis r4, 0x8000 + ori r4, r4, 0x0002 + stw r4, 0(r3) + sync +#endif +#if 1 + /* make sure timer enabled in guts register too */ + lis r3, CFG_CCSRBAR@h + oris r3,r3, 0xE + ori r3,r3,0x0070 /*Jason from 3*/ + lwz r4, 0(r3) + lis r5,0xFFFC /*Jason from 0xffff*/ + ori r5,r5,0x5FFF + and r4,r4,r5 + stw r4,0(r3) +#endif + /* + * Cache must be enabled here for stack-in-cache trick. + * This means we need to enable the BATS. + * Cache should be turned on after BATs, since by default + * everything is write-through. + */ + + /* enable address translation */ + bl enable_addr_trans + sync + + /* enable and invalidate the data cache */ +/* bl l1dcache_enable */ + bl dcache_enable + sync + +#if 1 + bl icache_enable +#endif + +#ifdef CFG_INIT_RAM_LOCK + bl lock_ram_in_cache + sync +#endif + + /* set up the stack pointer in our newly created + * cache-ram (r1) */ + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + GET_GOT /* initialize GOT access */ + + /* run low-level CPU init code (from Flash) */ + bl cpu_init_f + sync + +#ifdef RUN_DIAG + + /* Sri: Code to run the diagnostic automatically */ + + /* Load PX_AUX register address in r4 */ + lis r4, 0xf810 + ori r4, r4, 0x6 + /* Load contents of PX_AUX in r3 bits 24 to 31*/ + lbz r3, 0(r4) + + /* Mask and obtain the bit in r3 */ + rlwinm. r3, r3, 0, 24, 24 + /* If not zero, jump and continue with u-boot */ + bne diag_done + + /* Load back contents of PX_AUX in r3 bits 24 to 31 */ + lbz r3, 0(r4) + /* Set the MSB of the register value */ + ori r3, r3, 0x80 + /* Write value in r3 back to PX_AUX */ + stb r3, 0(r4) + + /* Get the address to jump to in r3*/ + lis r3, CFG_DIAG_ADDR@h + ori r3, r3, CFG_DIAG_ADDR@l + + /* Load the LR with the branch address */ + mtlr r3 + + /* Branch to diagnostic */ + blr + +diag_done: +#endif + + /* bl l2cache_enable*/ + mr r3, r21 + + /* r3: BOOTFLAG */ + /* run 1st part of board init code (from Flash) */ + bl board_init_f + sync + + /* NOTREACHED */ + + .globl invalidate_bats +invalidate_bats: + + /* invalidate BATs */ + mtspr IBAT0U, r0 + mtspr IBAT1U, r0 + mtspr IBAT2U, r0 + mtspr IBAT3U, r0 + mtspr IBAT4U, r0 + mtspr IBAT5U, r0 + mtspr IBAT6U, r0 + mtspr IBAT7U, r0 + + isync + mtspr DBAT0U, r0 + mtspr DBAT1U, r0 + mtspr DBAT2U, r0 + mtspr DBAT3U, r0 + mtspr DBAT4U, r0 + mtspr DBAT5U, r0 + mtspr DBAT6U, r0 + mtspr DBAT7U, r0 + + isync + sync + blr + + + /* setup_bats - set them up to some initial state */ + .globl setup_bats +setup_bats: + + addis r0, r0, 0x0000 + + /* IBAT 0 */ + addis r4, r0, CFG_IBAT0L@h + ori r4, r4, CFG_IBAT0L@l + addis r3, r0, CFG_IBAT0U@h + ori r3, r3, CFG_IBAT0U@l + mtspr IBAT0L, r4 + mtspr IBAT0U, r3 + isync + + /* DBAT 0 */ + addis r4, r0, CFG_DBAT0L@h + ori r4, r4, CFG_DBAT0L@l + addis r3, r0, CFG_DBAT0U@h + ori r3, r3, CFG_DBAT0U@l + mtspr DBAT0L, r4 + mtspr DBAT0U, r3 + isync + + /* IBAT 1 */ + addis r4, r0, CFG_IBAT1L@h + ori r4, r4, CFG_IBAT1L@l + addis r3, r0, CFG_IBAT1U@h + ori r3, r3, CFG_IBAT1U@l + mtspr IBAT1L, r4 + mtspr IBAT1U, r3 + isync + + /* DBAT 1 */ + addis r4, r0, CFG_DBAT1L@h + ori r4, r4, CFG_DBAT1L@l + addis r3, r0, CFG_DBAT1U@h + ori r3, r3, CFG_DBAT1U@l + mtspr DBAT1L, r4 + mtspr DBAT1U, r3 + isync + + /* IBAT 2 */ + addis r4, r0, CFG_IBAT2L@h + ori r4, r4, CFG_IBAT2L@l + addis r3, r0, CFG_IBAT2U@h + ori r3, r3, CFG_IBAT2U@l + mtspr IBAT2L, r4 + mtspr IBAT2U, r3 + isync + + /* DBAT 2 */ + addis r4, r0, CFG_DBAT2L@h + ori r4, r4, CFG_DBAT2L@l + addis r3, r0, CFG_DBAT2U@h + ori r3, r3, CFG_DBAT2U@l + mtspr DBAT2L, r4 + mtspr DBAT2U, r3 + isync + + /* IBAT 3 */ + addis r4, r0, CFG_IBAT3L@h + ori r4, r4, CFG_IBAT3L@l + addis r3, r0, CFG_IBAT3U@h + ori r3, r3, CFG_IBAT3U@l + mtspr IBAT3L, r4 + mtspr IBAT3U, r3 + isync + + /* DBAT 3 */ + addis r4, r0, CFG_DBAT3L@h + ori r4, r4, CFG_DBAT3L@l + addis r3, r0, CFG_DBAT3U@h + ori r3, r3, CFG_DBAT3U@l + mtspr DBAT3L, r4 + mtspr DBAT3U, r3 + isync + + /* IBAT 4 */ + addis r4, r0, CFG_IBAT4L@h + ori r4, r4, CFG_IBAT4L@l + addis r3, r0, CFG_IBAT4U@h + ori r3, r3, CFG_IBAT4U@l + mtspr IBAT4L, r4 + mtspr IBAT4U, r3 + isync + + /* DBAT 4 */ + addis r4, r0, CFG_DBAT4L@h + ori r4, r4, CFG_DBAT4L@l + addis r3, r0, CFG_DBAT4U@h + ori r3, r3, CFG_DBAT4U@l + mtspr DBAT4L, r4 + mtspr DBAT4U, r3 + isync + + /* IBAT 5 */ + addis r4, r0, CFG_IBAT5L@h + ori r4, r4, CFG_IBAT5L@l + addis r3, r0, CFG_IBAT5U@h + ori r3, r3, CFG_IBAT5U@l + mtspr IBAT5L, r4 + mtspr IBAT5U, r3 + isync + + /* DBAT 5 */ + addis r4, r0, CFG_DBAT5L@h + ori r4, r4, CFG_DBAT5L@l + addis r3, r0, CFG_DBAT5U@h + ori r3, r3, CFG_DBAT5U@l + mtspr DBAT5L, r4 + mtspr DBAT5U, r3 + isync + + /* IBAT 6 */ + addis r4, r0, CFG_IBAT6L@h + ori r4, r4, CFG_IBAT6L@l + addis r3, r0, CFG_IBAT6U@h + ori r3, r3, CFG_IBAT6U@l + mtspr IBAT6L, r4 + mtspr IBAT6U, r3 + isync + + /* DBAT 6 */ + addis r4, r0, CFG_DBAT6L@h + ori r4, r4, CFG_DBAT6L@l + addis r3, r0, CFG_DBAT6U@h + ori r3, r3, CFG_DBAT6U@l + mtspr DBAT6L, r4 + mtspr DBAT6U, r3 + isync + + /* IBAT 7 */ + addis r4, r0, CFG_IBAT7L@h + ori r4, r4, CFG_IBAT7L@l + addis r3, r0, CFG_IBAT7U@h + ori r3, r3, CFG_IBAT7U@l + mtspr IBAT7L, r4 + mtspr IBAT7U, r3 + isync + + /* DBAT 7 */ + addis r4, r0, CFG_DBAT7L@h + ori r4, r4, CFG_DBAT7L@l + addis r3, r0, CFG_DBAT7U@h + ori r3, r3, CFG_DBAT7U@l + mtspr DBAT7L, r4 + mtspr DBAT7U, r3 + isync + +1: + addis r3, 0, 0x0000 + addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ + isync + +tlblp: + tlbie r3 + sync + addi r3, r3, 0x1000 + cmp 0, 0, r3, r5 + blt tlblp + + blr + + .globl enable_addr_trans +enable_addr_trans: + /* enable address translation */ + mfmsr r5 + ori r5, r5, (MSR_IR | MSR_DR) + mtmsr r5 + isync + blr + + .globl disable_addr_trans +disable_addr_trans: + /* disable address translation */ + mflr r4 + mfmsr r3 + andi. r0, r3, (MSR_IR | MSR_DR) + beqlr + andc r3, r3, r0 + mtspr SRR0, r4 + mtspr SRR1, r3 + rfi + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + + .globl dc_read +dc_read: + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + + .globl get_svr +get_svr: + mfspr r3, SVR + blr + + +/*------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcSync */ +/* Description: Processor Synchronize */ +/* Input: none. */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcSync +ppcSync: + sync + blr + +/*-----------------------------------------------------------------------*/ +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ +#ifdef CONFIG_ECC + bl board_relocate_rom + sync + mr r3, r10 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ +#else + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b +#endif +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: +#ifdef CONFIG_ECC + bl board_init_ecc +#endif + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +/* clear_bss: */ + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + mr r3, r10 /* Destination Address */ + bl after_reloc + + /* not reached - end relocate_code */ +/*-----------------------------------------------------------------------*/ + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector always at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + /* enable execptions from RAM vectors */ + mfmsr r7 + li r8,MSR_IP + andc r7,r7,r8 + mtmsr r7 + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + sync + isync + + blr + +.globl enable_ext_addr +enable_ext_addr: + mfspr r0, HID0 + lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h + ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l + mtspr HID0, r0 + sync + isync + blr + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) +.globl setup_ccsrbar +setup_ccsrbar: + /* Special sequence needed to update CCSRBAR itself */ + lis r4, CFG_CCSRBAR_DEFAULT@h + ori r4, r4, CFG_CCSRBAR_DEFAULT@l + + lis r5, CFG_CCSRBAR@h + ori r5, r5, CFG_CCSRBAR@l + srwi r6,r5,12 + stw r6, 0(r4) + isync + + lis r5, 0xffff + ori r5,r5,0xf000 + lwz r5, 0(r5) + isync + + lis r3, CFG_CCSRBAR@h + lwz r5, CFG_CCSRBAR@l(r3) + isync + + blr +#endif + +#ifdef CFG_INIT_RAM_LOCK +lock_ram_in_cache: + /* Allocate Initial RAM in data cache. + */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r2 +1: + dcbz r0, r3 + addi r3, r3, 32 + bdnz 1b +#if 1 +/* Lock the data cache */ + mfspr r0, HID0 + ori r0, r0, 0x1000 + sync + mtspr HID0, r0 + sync + blr +#endif +#if 0 + /* Lock the first way of the data cache */ + mfspr r0, LDSTCR + ori r0, r0, 0x0080 +#if defined(CONFIG_ALTIVEC) + dssall +#endif + sync + mtspr LDSTCR, r0 + sync + isync + blr +#endif + +.globl unlock_ram_in_cache +unlock_ram_in_cache: + /* invalidate the INIT_RAM section */ + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r2 +1: icbi r0, r3 + addi r3, r3, 32 + bdnz 1b + sync /* Wait for all icbi to complete on bus */ + isync +#if 1 +/* Unlock the data cache and invalidate it */ + mfspr r0, HID0 + li r3,0x1000 + andc r0,r0,r3 + li r3,0x0400 + or r0,r0,r3 + sync + mtspr HID0, r0 + sync + blr +#endif +#if 0 + /* Unlock the first way of the data cache */ + mfspr r0, LDSTCR + li r3,0x0080 + andc r0,r0,r3 +#ifdef CONFIG_ALTIVEC + dssall +#endif + sync + mtspr LDSTCR, r0 + sync + isync + li r3,0x0400 + or r0,r0,r3 + sync + mtspr HID0, r0 + sync + blr +#endif +#endif + +/* If this is a multi-cpu system then we need to handle the + * 2nd cpu. The assumption is that the 2nd cpu is being + * held in boot holdoff mode until the 1st cpu unlocks it + * from Linux. We'll do some basic cpu init and then pass + * it to the Linux Reset Vector. + * Sri: Much of this initialization is not required. Linux + * rewrites the bats, and the sprs and also enables the L1 cache. + */ +#if (CONFIG_NUM_CPUS > 1) +.globl secondary_cpu_setup +secondary_cpu_setup: + /* Do only core setup on all cores except cpu0 */ + bl invalidate_bats + sync + bl enable_ext_addr + +#ifdef CFG_L2 + /* init the L2 cache */ + addis r3, r0, L2_INIT@h + ori r3, r3, L2_INIT@l + sync + mtspr l2cr, r3 +#ifdef CONFIG_ALTIVEC + dssall +#endif + /* invalidate the L2 cache */ + bl l2cache_invalidate + sync +#endif + + /* setup the bats */ + bl setup_bats + sync + /* enable address translation */ + bl enable_addr_trans + sync + + /* enable and invalidate the data cache */ + bl dcache_enable + sync + + /* enable and invalidate the instruction cache*/ + bl icache_enable + sync + + /* Set up MSR and HID0, HID1*/ + /* Enable interrupts */ +/* mfmsr r28 + li r4,0 + ori r4,r4,MSR_EE + or r28,r28,r4 + mtmsr r28 + */ + + /* TBEN in HID0 */ + mfspr r4, HID0 + oris r4, r4, 0x0400 + mtspr HID0, r4 + sync + isync + + /*SYNCBE|ABE in HID1*/ + mfspr r4, HID1 + ori r4, r4, 0x0C00 + mtspr HID1, r4 + sync + isync + + lis r3, CONFIG_LINUX_RESET_VEC@h + ori r3, r3, CONFIG_LINUX_RESET_VEC@l + mtlr r3 + blr + + /* Never Returns, Running in Linux Now */ +#endif + diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c new file mode 100644 index 000000000..fdfc95dfc --- /dev/null +++ b/cpu/mpc86xx/traps.c @@ -0,0 +1,253 @@ +/* + * linux/arch/ppc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +int (*debugger_exception_handler)(struct pt_regs *) = 0; +#endif + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) + +/* + * Trap & Exception support + */ + +void +print_backtrace(unsigned long *sp) +{ + DECLARE_GLOBAL_DATA_PTR; + + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void +show_regs(struct pt_regs * regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS:" + " %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP:" + " %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void +MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void +AlignmentException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void +ProgramCheckException(struct pt_regs *regs) +{ + unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; + int i, j; + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + + p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0); + p -= 32; + for (i = 0; i < 256; i+=16) { + printf("%08x: ", (unsigned int)p+i); + for (j = 0; j < 16; j++) { + printf("%02x ", p[i+j]); + } + printf("\n"); + } + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void +SoftEmuException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); +} + + +void +UnknownException(struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int +addr_probe(uint *addr) +{ +#if 0 + int retval; + + __asm__ __volatile__( \ + "1: lwz %0,0(%1)\n" \ + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); + + return (retval); +#endif + return 0; +} + + + + + + diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 15f74328f..3c958d3b9 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -186,7 +186,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1); } if (pci_io) { diff --git a/drivers/tsec.c b/drivers/tsec.c index 7ec565ca6..18778c270 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -74,27 +75,33 @@ struct tsec_info_struct { static struct tsec_info_struct tsec_info[] = { #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, +#elif defined(CONFIG_MPC86XX_TSEC1) + {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, #else { 0, 0, 0}, #endif #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, +#elif defined(CONFIG_MPC86XX_TSEC2) + {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, #else { 0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC {FEC_PHY_ADDR, 0, FEC_PHYIDX}, #else -# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) +#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3) {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, -# else +#else { 0, 0, 0}, -# endif -# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) +#endif +#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, -# else +#elif defined(CONFIG_MPC86XX_TSEC4) + {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, +#else { 0, 0, 0}, -# endif +#endif #endif }; @@ -467,6 +474,32 @@ uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv) return 0; } +/* Parse the vsc8244's status register for speed and duplex + * information */ +uint mii_parse_vsc8244(uint mii_reg, struct tsec_private *priv) +{ + uint speed; + + if(mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; + switch(speed) { + case MIIM_VSC8244_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_VSC8244_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; + } + + return 0; +} /* Parse the DM9161's status register for speed and duplex @@ -859,6 +892,29 @@ struct phy_info phy_info_cis8201 = { {miim_end,} }, }; +struct phy_info phy_info_VSC8244 = { + 0x3f1b, + "Vitesse VSC8244", + 6, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; struct phy_info phy_info_dm9161 = { @@ -1001,6 +1057,7 @@ struct phy_info *phy_info[] = { &phy_info_M88E1111S, &phy_info_dm9161, &phy_info_lxt971, + &phy_info_VSC8244, &phy_info_dp83865, NULL }; diff --git a/drivers/tsec.h b/drivers/tsec.h index b55b2992b..31f18675f 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -27,7 +27,7 @@ #define TSEC_SIZE 0x01000 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #elif defined(CONFIG_MPC83XX) #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) @@ -133,6 +133,24 @@ #define MIIM_GBIT_CON 0x09 #define MIIM_GBIT_CON_ADVERT 0x0e00 +/* Entry for Vitesse VSC8244 regs starts here */ +/* Vitesse VSC8244 Auxiliary Control/Status Register */ +#define MIIM_VSC8244_AUX_CONSTAT 0x1c +#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 +#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 +#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 +#define MIIM_VSC8244_AUXCONSTAT_100 0x0008 +#define MIIM_CONTROL_INIT_LOOPBACK 0x4000 + +/* Vitesse VSC8244 Extended PHY Control Register 1 */ +#define MIIM_VSC8244_EPHY_CON 0x17 +#define MIIM_VSC8244_EPHYCON_INIT 0x0006 + +/* Vitesse VSC8244 Serial LED Control Register */ +#define MIIM_VSC8244_LED_CON 0x1b +#define MIIM_VSC8244_LEDCON_INIT 0xF011 + /* 88E1011 PHY Status Register */ #define MIIM_88E1011_PHY_STATUS 0x11 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h new file mode 100644 index 000000000..6bbe072b2 --- /dev/null +++ b/include/asm-ppc/immap_86xx.h @@ -0,0 +1,1362 @@ +/* + * MPC86xx Internal Memory Map + * + * Copyright(c) 2004 Freescale Semiconductor + * Jeff Brown (Jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + */ + +#ifndef __IMMAP_86xx__ +#define __IMMAP_86xx__ + + +/* Local-Access Registers and MCM Registers(0x0000-0x2000) */ +typedef struct ccsr_local_mcm { + uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ + char res1[4]; + uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ + char res2[4]; + uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ + char res3[12]; + uint bptr; /* 0x20 - Boot Page Translation Register */ + char res4[3044]; + uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ + char res5[4]; + uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ + char res6[20]; + uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ + char res7[4]; + uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ + char res8[20]; + uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ + char res9[4]; + uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ + char res10[20]; + uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ + char res11[4]; + uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ + char res12[20]; + uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ + char res13[4]; + uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ + char res14[20]; + uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ + char res15[4]; + uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ + char res16[20]; + uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ + char res17[4]; + uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ + char res18[20]; + uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ + char res19[4]; + uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ + char res20[16]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res21[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res22[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res23[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res24[720]; + uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ + char res25[4]; + uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ + char res26[4]; + uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ + char res27[44]; + uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ + uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ + uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ + uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ + char res28[16]; + uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ + uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ + uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ + char res29[3476]; + uint edr; /* 0x1e00 - MCM Error Detect Register */ + char res30[4]; + uint eer; /* 0x1e08 - MCM Error Enable Register */ + uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ + uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ + uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ + char res31[488]; +} ccsr_local_mcm_t; + +/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ + +typedef struct ccsr_ddr { + uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ + char res1[4]; + uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ + char res2[4]; + uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ + char res3[4]; + uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ + char res4[4]; + uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ + char res5[4]; + uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ + char res6[84]; + uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ + uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ + uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ + uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ + uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ + uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ + char res7[104]; + uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ + uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ + uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ + uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ + uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + char res8[4]; + uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ + char res9[12]; + uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ + uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ + uint init_addr; /* 0x2148 - DDR training initialzation address */ + uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + char res10[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res11[512]; + uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ + uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ + uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ + char res12[20]; + uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ + uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ + uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ + char res13[20]; + uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ + uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ + uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ + uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ + uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ + char res14[164]; + uint debug_1; /* 0x2f00 */ + uint debug_2; + uint debug_3; + uint debug_4; + uint debug_5; + char res15[236]; +} ccsr_ddr_t; + + +/* Daul I2C Registers(0x3000-0x4000) */ + +typedef struct ccsr_i2c { + u_char i2cadr1; /* 0x3000 - I2C 1 Address Register */ +#define MPC86xx_I2CADR_MASK 0xFE + char res1[3]; + u_char i2cfdr1; /* 0x3004 - I2C 1 Frequency Divider Register */ +#define MPC86xx_I2CFDR_MASK 0x3F + char res2[3]; + u_char i2ccr1; /* 0x3008 - I2C 1 Control Register */ +#define MPC86xx_I2CCR_MEN 0x80 +#define MPC86xx_I2CCR_MIEN 0x40 +#define MPC86xx_I2CCR_MSTA 0x20 +#define MPC86xx_I2CCR_MTX 0x10 +#define MPC86xx_I2CCR_TXAK 0x08 +#define MPC86xx_I2CCR_RSTA 0x04 +#define MPC86xx_I2CCR_BCST 0x01 + char res3[3]; + u_char i2csr1; /* 0x300c - I2C 1 Status Register */ +#define MPC86xx_I2CSR_MCF 0x80 +#define MPC86xx_I2CSR_MAAS 0x40 +#define MPC86xx_I2CSR_MBB 0x20 +#define MPC86xx_I2CSR_MAL 0x10 +#define MPC86xx_I2CSR_BCSTM 0x08 +#define MPC86xx_I2CSR_SRW 0x04 +#define MPC86xx_I2CSR_MIF 0x02 +#define MPC86xx_I2CSR_RXAK 0x01 + char res4[3]; + u_char i2cdr1; /* 0x3010 - I2C 1 Data Register */ +#define MPC86xx_I2CDR_DATA 0xFF + char res5[3]; + u_char i2cdfsrr1; /* 0x3014 - I2C 1 Digital Filtering Sampling Rate Register */ +#define MPC86xx_I2CDFSRR 0x3F + char res6[235]; + + u_char i2cadr2; /* 0x3100 - I2C 2 Address Register */ + char res7[3]; + u_char i2cfdr2; /* 0x3104 - I2C 2 Frequency Divider Register */ + char res8[3]; + u_char i2ccr2; /* 0x3108 - I2C 2 Control Register */ + char res9[3]; + u_char i2csr2; /* 0x310c - I2C 2 Status Register */ + char res10[3]; + u_char i2cdr2; /* 0x3110 - I2C 2 Data Register */ + char res11[3]; + u_char i2cdfsrr2; /* 0x3114 - I2C 2 Digital Filtering Sampling Rate Register */ + char res12[3819]; +} ccsr_i2c_t; + +/* DUART Registers(0x4000-0x5000) */ +typedef struct ccsr_duart { + char res1[1280]; + u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ + u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ + u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ + u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ + u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ + u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ + u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ + u_char uscr1; /* 0x4507 - UART1 Scratch Register */ + char res2[8]; + u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ + char res3[239]; + u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ + u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ + u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ + u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ + u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ + u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ + u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ + u_char uscr2; /* 0x4607 - UART2 Scratch Register */ + char res4[8]; + u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ + char res5[2543]; +} ccsr_duart_t; + + +/* Local Bus Controller Registers(0x5000-0x6000) */ +typedef struct ccsr_lbc { + uint br0; /* 0x5000 - LBC Base Register 0 */ + uint or0; /* 0x5004 - LBC Options Register 0 */ + uint br1; /* 0x5008 - LBC Base Register 1 */ + uint or1; /* 0x500c - LBC Options Register 1 */ + uint br2; /* 0x5010 - LBC Base Register 2 */ + uint or2; /* 0x5014 - LBC Options Register 2 */ + uint br3; /* 0x5018 - LBC Base Register 3 */ + uint or3; /* 0x501c - LBC Options Register 3 */ + uint br4; /* 0x5020 - LBC Base Register 4 */ + uint or4; /* 0x5024 - LBC Options Register 4 */ + uint br5; /* 0x5028 - LBC Base Register 5 */ + uint or5; /* 0x502c - LBC Options Register 5 */ + uint br6; /* 0x5030 - LBC Base Register 6 */ + uint or6; /* 0x5034 - LBC Options Register 6 */ + uint br7; /* 0x5038 - LBC Base Register 7 */ + uint or7; /* 0x503c - LBC Options Register 7 */ + char res1[40]; + uint mar; /* 0x5068 - LBC UPM Address Register */ + char res2[4]; + uint mamr; /* 0x5070 - LBC UPMA Mode Register */ + uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ + uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ + char res3[8]; + uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ + uint mdr; /* 0x5088 - LBC UPM Data Register */ + char res4[8]; + uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ + char res5[8]; + uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ + uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ + char res6[8]; + uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ + uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ + uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ + uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ + uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ + char res7[12]; + uint lbcr; /* 0x50d0 - LBC Configuration Register */ + uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ + char res8[3880]; +} ccsr_lbc_t; + +/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ +typedef struct ccsr_pex { + uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ + uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ + char res1[4]; + uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ + char res2[16]; + uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ + uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ + uint pme_msg_dis; /* 0x802C - PEX PME & message disable register */ + char res3[4]; + uint pm_command; /* 0x8030 - PEX PM Command register */ + char res4[3016]; + uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ + uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ + uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ + uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ + char res5[8]; + uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ + char res6[12]; + uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ + uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ + uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ + char res7[4]; + uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ + char res8[12]; + uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ + uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ + uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ + char res9[4]; + uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ + char res10[12]; + uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ + uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ + uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ + char res11[4]; + uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ + char res12[12]; + uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ + uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ + uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ + char res13[4]; + uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ + char res14[268]; + uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ + char res15[4]; + uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ + uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */ + uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ + char res16[12]; + uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ + char res17[4]; + uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ + uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ + uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ + char res18[12]; + uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ + char res19[4]; + uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ + char res20[4]; + uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ + char res21[12]; + uint pedr; /* 0x8e00 - PEX Error Detect Register */ + uint pecdr; /* 0x8e04 - PEX Error Capture Disable Register */ + uint peer; /* 0x8e08 - PEX Error Enable Register */ + uint perr_cap0; /* 0x8e0c - PEX Error Capture Register 0 */ + uint perr_cap1; /* 0x8e10 - PEX Error Capture Register 1 */ + uint perr_cap2; /* 0x8e14 - PEX Error Capture Register 2 */ + uint perr_cap3; /* 0x8e18 - PEX Error Capture Register 3 */ + char res22[100]; + uint perr_stat; /* 0x8e80 - PEX Error Status Register */ + char res23[124]; + uint pdebug; /* 0x8f00 - PEX Debug Register */ + char res24[248]; //Sri: changed this because of adding 4 bytes before 0x?8020. +} ccsr_pex_t; + +/* Hyper Transport Register Block (0xA000-0xB000) */ +typedef struct ccsr_ht { + uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ + uint hcfg_data; /* 0xa004 - HT Configuration Data register */ + char res1[3064]; + uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ + char res2[12]; + uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ + char res3[12]; + uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ + char res4[4]; + uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ + char res5[4]; + uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ + char res6[12]; + uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ + char res7[4]; + uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ + char res8[4]; + uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ + char res9[12]; + uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ + char res10[4]; + uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ + char res11[4]; + uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ + char res12[12]; + uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ + char res13[4]; + uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ + char res14[4]; + uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ + char res15[236]; + uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ + char res16[4]; + uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ + char res17[4]; + uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ + char res18[12]; + uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ + char res19[4]; + uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ + char res20[4]; + uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ + char res21[12]; + uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ + char res22[4]; + uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ + char res23[4]; + uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ + char res24[12]; + uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ + char res25[4]; + uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ + char res26[4]; + uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ + char res27[12]; + uint hedr; /* 0xae00 - HT Error Detect register */ + char res28[4]; + uint heier; /* 0xae08 - HT Error Interrupt Enable register */ + char res29[4]; + uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ + char res30[12]; + uint hecsr; /* 0xae20 - HT Error Capture Status register */ + char res31[4]; + uint hec0; /* 0xae28 - HT Error Capture 0 register */ + uint hec1; /* 0xae2c - HT Error Capture 1 register */ + uint hec2; /* 0xae30 - HT Error Capture 2 register */ + char res32[460]; +} ccsr_ht_t; + +/* DMA Registers(0x2_1000-0x2_2000) */ +typedef struct ccsr_dma { + char res1[256]; + uint mr0; /* 0x21100 - DMA 0 Mode Register */ + uint sr0; /* 0x21104 - DMA 0 Status Register */ + char res2[4]; + uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */ + uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */ + uint sar0; /* 0x21114 - DMA 0 Source Address Register */ + uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */ + uint dar0; /* 0x2111c - DMA 0 Destination Address Register */ + uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */ + char res3[4]; + uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */ + char res4[8]; + uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */ + char res5[4]; + uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */ + uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */ + uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */ + char res6[56]; + uint mr1; /* 0x21180 - DMA 1 Mode Register */ + uint sr1; /* 0x21184 - DMA 1 Status Register */ + char res7[4]; + uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */ + uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */ + uint sar1; /* 0x21194 - DMA 1 Source Address Register */ + uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */ + uint dar1; /* 0x2119c - DMA 1 Destination Address Register */ + uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */ + char res8[4]; + uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */ + char res9[8]; + uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */ + char res10[4]; + uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */ + uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */ + uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */ + char res11[56]; + uint mr2; /* 0x21200 - DMA 2 Mode Register */ + uint sr2; /* 0x21204 - DMA 2 Status Register */ + char res12[4]; + uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */ + uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */ + uint sar2; /* 0x21214 - DMA 2 Source Address Register */ + uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */ + uint dar2; /* 0x2121c - DMA 2 Destination Address Register */ + uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */ + char res13[4]; + uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */ + char res14[8]; + uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */ + char res15[4]; + uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */ + uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */ + uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */ + char res16[56]; + uint mr3; /* 0x21280 - DMA 3 Mode Register */ + uint sr3; /* 0x21284 - DMA 3 Status Register */ + char res17[4]; + uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */ + uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */ + uint sar3; /* 0x21294 - DMA 3 Source Address Register */ + uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */ + uint dar3; /* 0x2129c - DMA 3 Destination Address Register */ + uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */ + char res18[4]; + uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */ + char res19[8]; + uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */ + char res20[4]; + uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */ + uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */ + uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */ + char res21[56]; + uint dgsr; /* 0x21300 - DMA General Status Register */ + char res22[3324]; +} ccsr_dma_t; + +/* tsec1-4: 24000-28000 */ +typedef struct ccsr_tsec { + uint id; /* 0x24000 - Controller ID Register */ + char res1[12]; + uint ievent; /* 0x24010 - Interrupt Event Register */ + uint imask; /* 0x24014 - Interrupt Mask Register */ + uint edis; /* 0x24018 - Error Disabled Register */ + char res2[4]; + uint ecntrl; /* 0x24020 - Ethernet Control Register */ + char res2_1[4]; + uint ptv; /* 0x24028 - Pause Time Value Register */ + uint dmactrl; /* 0x2402c - DMA Control Register */ + uint tbipa; /* 0x24030 - TBI PHY Address Register */ + char res3[88]; + uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ + char res4[8]; + uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ + uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ + char res4_1[4]; + uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ + uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ + char res5[84]; + uint tctrl; /* 0x24100 - Transmit Control Register */ + uint tstat; /* 0x24104 - Transmit Status Register */ + uint dfvlan; /* 0x24108 - Default VLAN control word */ + char res6[4]; + uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ + uint tqueue; /* 0x24114 - Transmit Queue Control Register */ + char res7[40]; + uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ + uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ + char res8[52]; + uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ + char res9[4]; + uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ + char res10[4]; + uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ + char res11[4]; + uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ + char res12[4]; + uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ + char res13[4]; + uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ + char res14[4]; + uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ + char res15[4]; + uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ + char res16[4]; + uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ + char res17[64]; + uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ + uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ + char res18[4]; + uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ + char res19[4]; + uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ + char res20[4]; + uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ + char res21[4]; + uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ + char res22[4]; + uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ + char res23[4]; + uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ + char res24[4]; + uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ + char res25[192]; + uint rctrl; /* 0x24300 - Receive Control Register */ + uint rstat; /* 0x24304 - Receive Status Register */ + char res26[8]; + uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ + uint rqueue; /* 0x24314 - Receive queue control register */ + char res27[24]; + uint rbifx; /* 0x24330 - Receive bit field extract control Register */ + uint rqfar; /* 0x24334 - Receive queue filing table address Register */ + uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ + char res28[56]; + uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ + char res29[4]; + uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ + char res30[4]; + uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ + char res31[4]; + uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ + char res32[4]; + uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ + char res33[4]; + uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ + char res34[4]; + uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ + char res35[4]; + uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ + char res36[4]; + uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ + char res37[64]; + uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ + uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ + char res38[4]; + uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ + char res39[4]; + uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ + char res40[4]; + uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ + char res41[4]; + uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ + char res42[4]; + uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ + char res43[4]; + uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ + char res44[4]; + uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ + char res45[192]; + uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ + uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ + uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ + uint hafdup; /* 0x2450c - Half Duplex Register */ + uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ + char res46[12]; + uint miimcfg; /* 0x24520 - MII Management Configuration Register */ + uint miimcom; /* 0x24524 - MII Management Command Register */ + uint miimadd; /* 0x24528 - MII Management Address Register */ + uint miimcon; /* 0x2452c - MII Management Control Register */ + uint miimstat; /* 0x24530 - MII Management Status Register */ + uint miimind; /* 0x24534 - MII Management Indicator Register */ + uint ifctrl; /* 0x24538 - Interface Contrl Register */ + uint ifstat; /* 0x2453c - Interface Status Register */ + uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ + uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ + uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ + uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ + uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ + uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ + uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ + uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ + uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ + uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ + uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ + uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ + uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ + uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ + uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ + uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ + uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ + uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ + uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ + uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ + uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ + uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ + uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ + uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ + uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ + uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ + uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ + uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ + uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ + uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ + uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ + uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ + char res48[192]; + uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ + uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ + uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ + uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ + uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ + uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ + uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ + uint rbyt; /* 0x2469c - Receive Byte Counter */ + uint rpkt; /* 0x246a0 - Receive Packet Counter */ + uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ + uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ + uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ + uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ + uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ + uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ + uint raln; /* 0x246bc - Receive Alignment Error Counter */ + uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ + uint rcde; /* 0x246c4 - Receive Code Error Counter */ + uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ + uint rund; /* 0x246cc - Receive Undersize Packet Counter */ + uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ + uint rfrg; /* 0x246d4 - Receive Fragments Counter */ + uint rjbr; /* 0x246d8 - Receive Jabber Counter */ + uint rdrp; /* 0x246dc - Receive Drop Counter */ + uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ + uint tpkt; /* 0x246e4 - Transmit Packet Counter */ + uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ + uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ + uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ + uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ + uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ + uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ + uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ + uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ + uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ + uint tncl; /* 0x2470c - Transmit Total Collision Counter */ + char res49[4]; + uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ + uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ + uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ + uint txcf; /* 0x24720 - Transmit Control Frame Counter */ + uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ + uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ + uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ + uint car1; /* 0x24730 - Carry Register One */ + uint car2; /* 0x24734 - Carry Register Two */ + uint cam1; /* 0x24738 - Carry Mask Register One */ + uint cam2; /* 0x2473c - Carry Mask Register Two */ + uint rrej; /* 0x24740 - Receive filer rejected packet counter */ + char res50[188]; + uint iaddr0; /* 0x24800 - Indivdual address register 0 */ + uint iaddr1; /* 0x24804 - Indivdual address register 1 */ + uint iaddr2; /* 0x24808 - Indivdual address register 2 */ + uint iaddr3; /* 0x2480c - Indivdual address register 3 */ + uint iaddr4; /* 0x24810 - Indivdual address register 4 */ + uint iaddr5; /* 0x24814 - Indivdual address register 5 */ + uint iaddr6; /* 0x24818 - Indivdual address register 6 */ + uint iaddr7; /* 0x2481c - Indivdual address register 7 */ + char res51[96]; + uint gaddr0; /* 0x24880 - Global address register 0 */ + uint gaddr1; /* 0x24884 - Global address register 1 */ + uint gaddr2; /* 0x24888 - Global address register 2 */ + uint gaddr3; /* 0x2488c - Global address register 3 */ + uint gaddr4; /* 0x24890 - Global address register 4 */ + uint gaddr5; /* 0x24894 - Global address register 5 */ + uint gaddr6; /* 0x24898 - Global address register 6 */ + uint gaddr7; /* 0x2489c - Global address register 7 */ + char res52[352]; + uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ + char res53[500]; + uint attr; /* 0x24BF8 - DMA Attribute register */ + uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ + char res54[1024]; +} ccsr_tsec_t; + +/* PIC Registers(0x4_0000-0x6_1000) */ + +typedef struct ccsr_pic { + char res1[64]; + uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ + char res2[12]; + uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ + char res3[12]; + uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ + char res4[12]; + uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ + char res5[12]; + uint ctpr; /* 0x40080 - Current Task Priority Register */ + char res6[12]; + uint whoami; /* 0x40090 - Who Am I Register */ + char res7[12]; + uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ + char res8[12]; + uint eoi; /* 0x400b0 - End Of Interrupt Register */ + char res9[3916]; + uint frr; /* 0x41000 - Feature Reporting Register */ + char res10[28]; + uint gcr; /* 0x41020 - Global Configuration Register */ + char res11[92]; + uint vir; /* 0x41080 - Vendor Identification Register */ + char res12[12]; + uint pir; /* 0x41090 - Processor Initialization Register */ + char res13[12]; + uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ + char res14[12]; + uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ + char res15[12]; + uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ + char res16[12]; + uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ + char res17[12]; + uint svr; /* 0x410e0 - Spurious Vector Register */ + char res18[12]; + uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ + char res19[12]; + uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ + char res20[12]; + uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ + char res21[12]; + uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ + char res22[12]; + uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ + char res23[12]; + uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ + char res24[12]; + uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ + char res25[12]; + uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ + char res26[12]; + uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ + char res27[12]; + uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ + char res28[12]; + uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ + char res29[12]; + uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ + char res30[12]; + uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ + char res31[12]; + uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ + char res32[12]; + uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ + char res33[12]; + uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ + char res34[12]; + uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ + char res35[268]; + uint tcr; /* 0x41300 - Timer Control Register */ + char res36[12]; + uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ + char res37[12]; + uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ + char res38[12]; + uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ + char res39[12]; + uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ + char res40[12]; + uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */ + char res41[12]; + uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */ + char res42[12]; + uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */ + char res43[12]; + uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */ + char res44[12]; + uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */ + char res45[12]; + uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ + char res46[12]; + uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ + char res47[12]; + uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ + char res48[60]; + uint msgr0; /* 0x41400 - Message Register 0 */ + char res49[12]; + uint msgr1; /* 0x41410 - Message Register 1 */ + char res50[12]; + uint msgr2; /* 0x41420 - Message Register 2 */ + char res51[12]; + uint msgr3; /* 0x41430 - Message Register 3 */ + char res52[204]; + uint mer; /* 0x41500 - Message Enable Register */ + char res53[12]; + uint msr; /* 0x41510 - Message Status Register */ + char res54[60140]; + uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ + char res55[12]; + uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ + char res56[12]; + uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ + char res57[12]; + uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ + char res58[12]; + uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ + char res59[12]; + uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ + char res60[12]; + uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ + char res61[12]; + uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ + char res62[12]; + uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ + char res63[12]; + uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ + char res64[12]; + uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ + char res65[12]; + uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ + char res66[12]; + uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ + char res67[12]; + uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ + char res68[12]; + uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ + char res69[12]; + uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ + char res70[12]; + uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ + char res71[12]; + uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ + char res72[12]; + uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ + char res73[12]; + uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ + char res74[12]; + uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ + char res75[12]; + uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ + char res76[12]; + uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ + char res77[12]; + uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ + char res78[140]; + uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ + char res79[12]; + uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ + char res80[12]; + uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ + char res81[12]; + uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ + char res82[12]; + uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ + char res83[12]; + uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ + char res84[12]; + uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ + char res85[12]; + uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ + char res86[12]; + uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ + char res87[12]; + uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ + char res88[12]; + uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ + char res89[12]; + uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ + char res90[12]; + uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ + char res91[12]; + uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ + char res92[12]; + uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ + char res93[12]; + uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ + char res94[12]; + uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ + char res95[12]; + uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ + char res96[12]; + uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ + char res97[12]; + uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ + char res98[12]; + uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ + char res99[12]; + uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ + char res100[12]; + uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ + char res101[12]; + uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ + char res102[12]; + uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ + char res103[12]; + uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ + char res104[12]; + uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ + char res105[12]; + uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ + char res106[12]; + uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ + char res107[12]; + uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ + char res108[12]; + uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ + char res109[12]; + uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ + char res110[12]; + uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ + char res111[12]; + uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ + char res112[12]; + uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ + char res113[12]; + uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ + char res114[12]; + uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ + char res115[12]; + uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ + char res116[12]; + uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ + char res117[12]; + uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ + char res118[12]; + uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ + char res119[12]; + uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ + char res120[12]; + uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ + char res121[12]; + uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ + char res122[12]; + uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ + char res123[12]; + uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ + char res124[12]; + uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ + char res125[12]; + uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ + char res126[12]; + uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ + char res127[12]; + uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ + char res128[12]; + uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ + char res129[12]; + uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ + char res130[12]; + uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ + char res131[12]; + uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ + char res132[12]; + uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ + char res133[12]; + uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ + char res134[12]; + uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ + char res135[12]; + uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ + char res136[12]; + uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ + char res137[12]; + uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ + char res138[12]; + uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ + char res139[12]; + uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ + char res140[12]; + uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ + char res141[12]; + uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ + char res142[4108]; + uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ + char res143[12]; + uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ + char res144[12]; + uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ + char res145[12]; + uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ + char res146[12]; + uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ + char res147[12]; + uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ + char res148[12]; + uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ + char res149[12]; + uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ + char res150[59852]; + uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ + char res151[12]; + uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ + char res152[12]; + uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ + char res153[12]; + uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ + char res154[12]; + uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ + char res155[12]; + uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ + char res156[12]; + uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ + char res157[12]; + uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ + char res158[3916]; +} ccsr_pic_t; + +/* RapidIO Registers(0xc_0000-0xe_0000) */ + +typedef struct ccsr_rio { + uint didcar; /* 0xc0000 - Device Identity Capability Register */ + uint dicar; /* 0xc0004 - Device Information Capability Register */ + uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ + uint aicar; /* 0xc000c - Assembly Information Capability Register */ + uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ + uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ + uint socar; /* 0xc0018 - Source Operations Capability Register */ + uint docar; /* 0xc001c - Destination Operations Capability Register */ + char res1[32]; + uint msr; /* 0xc0040 - Mailbox Command And Status Register */ + uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ + char res2[4]; + uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ + char res3[12]; + uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ + uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ + char res4[4]; + uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ + uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ + char res5[144]; + uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ + char res6[28]; + uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ + uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ + char res7[20]; + uint pgccsr; /* 0xc013c - Port General Command and Status Register */ + uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ + uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ + uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ + char res8[12]; + uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ + uint pccsr; /* 0xc015c - Port Control Command and Status Register */ + char res9[1184]; + uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ + char res10[4]; + uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ + uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ + char res11[4]; + uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ + uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ + uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ + char res12[32]; + uint edcsr; /* 0xc0640 - Port 0 error detect status register */ + uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ + uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ + uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ + uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ + char res13[12]; + uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ + uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ + char res14[63892]; + uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ + char res15[12]; + uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ + char res16[12]; + uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ + char res17[92]; + uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ + char res18[124]; + uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ + char res19[28]; + uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ + char res20[12]; + uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ + char res21[12]; + uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ + char res22[20]; + uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ + char res23[4]; + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + char res24[2716]; + uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ + uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ + char res25[8]; + uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + char res26[12]; + uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ + uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ + uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ + char res27[4]; + uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ + uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ + uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ + uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ + uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ + uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ + char res28[4]; + uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ + uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ + uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ + uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ + uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ + uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ + char res29[4]; + uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ + uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ + uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ + uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ + uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ + uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ + char res30[4]; + uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ + uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ + uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ + uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ + uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ + uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ + char res31[4]; + uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ + uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ + uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ + uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ + uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ + uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ + char res32[4]; + uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ + uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ + uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ + uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ + uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ + uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ + char res33[4]; + uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ + uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ + uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ + uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ + uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ + uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ + char res34[4]; + uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ + uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ + uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ + char res35[64]; + uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ + uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ + char res36[4]; + uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + char res37[12]; + uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ + char res38[4]; + uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ + char res39[4]; + uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ + char res40[12]; + uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ + char res41[4]; + uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ + char res42[4]; + uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ + char res43[12]; + uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ + char res44[4]; + uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ + char res45[4]; + uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ + char res46[12]; + uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ + char res47[12]; + uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + char res48[12]; + uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ + uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ + uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ + uint pecr; /* 0xd0e0c - Port Error Control Register */ + uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ + uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + char res49[4]; + uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + char res50[4]; + uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ + char res51[8656]; + uint omr; /* 0xd3000 - Outbound Mode Register */ + uint osr; /* 0xd3004 - Outbound Status Register */ + uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ + uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ + uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ + uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ + uint odpr; /* 0xd3018 - Outbound Destination Port Register */ + uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ + uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ + uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ + uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ + uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ + uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ + uint omlr; /* 0xd3034 - Outbound Multicast List Register */ + char res52[40]; + uint imr; /* 0xd3060 - Outbound Mode Register */ + uint isr; /* 0xd3064 - Inbound Status Register */ + uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ + uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ + uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ + uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ + uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ + char res53[900]; + uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ + uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ + char res54[16]; + uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ + uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ + char res55[12]; + uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ + char res56[48]; + uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ + uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ + uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ + uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ + uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ + uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + char res57[100]; + uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ + uint pwsr; /* 0xd34e4 - Port-Write Status Register */ + uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ + uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ + char res58[51984]; +} ccsr_rio_t; + +/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ +typedef struct ccsr_gur { + uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ + uint porbmsr; /* 0xe0004 - POR boot mode status register */ +#define MPC86xx_PORBMSR_HA 0x00060000 + uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ + uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ +#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000 + uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ + char res1[12]; + uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ + char res2[12]; + uint gpiocr; /* 0xe0030 - GPIO control register */ + char res3[12]; + uint gpoutdr; /* 0xe0040 - General-purpose output data register */ + char res4[12]; + uint gpindr; /* 0xe0050 - General-purpose input data register */ + char res5[12]; + uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + char res6[12]; + uint devdisr; /* 0xe0070 - Device disable control */ +#define MPC86xx_DEVDISR_PCIEX1 0x80000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 + char res7[12]; + uint powmgtcsr; /* 0xe0080 - Power management status and control register */ + char res8[12]; + uint mcpsumr; /* 0xe0090 - Machine check summary register */ + char res9[12]; + uint pvr; /* 0xe00a0 - Processor version register */ + uint svr; /* 0xe00a4 - System version register */ + char res10[3416]; + uint clkocr; /* 0xe0e00 - Clock out select register */ + char res11[12]; + uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ + char res12[12]; + uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ + int res13[57]; + uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ + int res14[6]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15[61656]; +} ccsr_gur_t; + +typedef struct immap { + ccsr_local_mcm_t im_local_mcm; + ccsr_ddr_t im_ddr1; + ccsr_i2c_t im_i2c; + ccsr_duart_t im_duart; + ccsr_lbc_t im_lbc; + ccsr_ddr_t im_ddr2; + char res1[4096]; + ccsr_pex_t im_pex1; + ccsr_pex_t im_pex2; + ccsr_ht_t im_ht; + char res2[90112]; + ccsr_dma_t im_dma; + char res3[8192]; + ccsr_tsec_t im_tsec1; + ccsr_tsec_t im_tsec2; + ccsr_tsec_t im_tsec3; + ccsr_tsec_t im_tsec4; + char res4[98304]; + ccsr_pic_t im_pic; + char res5[389120]; + ccsr_rio_t im_rio; + ccsr_gur_t im_gur; +} immap_t; + +extern immap_t *immr; + +#endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 2606b79a2..612b5df48 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -434,19 +434,28 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_1GB 10 #define BOOKE_PAGESZ_4GB 11 +#if defined(CONFIG_MPC86xx) +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 +#else #define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_EN 0x80000000 #define LAWAR_TRGT_IF 0x00F00000 +#endif +#define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F #define LAWAR_TRGT_IF_PCI 0x00000000 #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 +#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 +#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -469,5 +478,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) #endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 811378383..1848aaf8c 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,6 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -443,6 +444,11 @@ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ #define ESR_ST 0x00800000 /* Store Operation */ +#if defined(CONFIG_MPC86xx) +#define SPRN_MSSCRO 0x3f6 +#endif + + /* Short-hand versions for a number of the above SPRNs */ #define CTR SPRN_CTR /* Counter Register */ @@ -501,10 +507,14 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ -#if defined(CONFIG_E500) +#if defined(CONFIG_MPC86xx) +#define MSSCR0 SPRN_MSSCRO +#endif +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR #endif #define SVR SPRN_SVR /* System-On-Chip Version Register */ @@ -538,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG0 +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R @@ -755,6 +765,8 @@ #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_86xx 0x80040000 +#define PVR_86xx_REV1 (PVR_86xx | 0x0010) /* * For the 8xx processors, all of them report the same PVR family for @@ -808,6 +820,8 @@ #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 +#define SVR_8641 0x8090 +#define SVR_8641D 0x8091 /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index f7aa55f33..f335cd856 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -45,7 +45,7 @@ typedef struct bd_info { unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) diff --git a/include/common.h b/include/common.h index 5d8b15628..83ccf7c98 100644 --- a/include/common.h +++ b/include/common.h @@ -79,6 +79,10 @@ typedef volatile unsigned char vu_char; #endif #include #endif +#ifdef CONFIG_MPC86xx +#include +#include +#endif #ifdef CONFIG_MPC85xx #include #include @@ -366,6 +370,7 @@ void trap_init (ulong); defined (CONFIG_74xx) || \ defined (CONFIG_MPC8220) || \ defined (CONFIG_MPC85xx) || \ + defined (CONFIG_MPC86xx) || \ defined (CONFIG_MPC83XX) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); @@ -454,6 +459,10 @@ ulong get_bus_freq (ulong); typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); #endif +#if defined(CONFIG_MPC86xx) +typedef MPC86xx_SYS_INFO sys_info_t; +void get_sys_info ( sys_info_t * ); +#endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) @@ -468,7 +477,7 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_8xx) || defined(CONFIG_8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) void cpu_init_f (void); #endif diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h new file mode 100644 index 000000000..8d2e08851 --- /dev/null +++ b/include/configs/MPC8641HPCN.h @@ -0,0 +1,629 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8641hpc3 board configuration file + * + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#undef DEBUG + +//#define RUN_DIAG 1 +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif +#define CFG_RESET_ADDRESS 0xfff00100 + +//#define CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE +/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ +/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ + + +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + + +#define CONFIG_ALTIVEC 1 +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + */ + +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +//#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +/* JB - XXX - Are these available on 86xx? */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + +#else + /* + * Manually set up DDR parameters + */ + +/* DDR I */ +#if 1 + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_1 0x39357322 + #define CFG_DDR_TIMING_2 0x14904cc8 + #define CFG_DDR_MODE_1 0x00480432 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_INTERVAL 0x06090100 + #define CFG_DDR_DATA_INIT 0xdeadbeef + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ + #define CFG_DDR_CONTROL2 0x04400000 + + //Not used in fixed_sdram function + + #define CFG_DDR_MODE 0x00000022 + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done + #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done + + + +#endif +#endif + + +/* + * SDRAM on the Local Bus + */ +//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 + * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. + * However, when u-boot comes up, the flash_init needs hard start addresses + * to build its info table. For user convenience, we have the flash addresses + * as fe800000 and ff800000. That way, when we do flash operations, u-boot + * knows where the flash is and the user can download u-boot code from promjet to + * fef00000 <- more intuitive than fe700000. Note that, on switching the boot + * location, fef00000 becomes fff00000. +*/ +#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ +#define CFG_FLASH_BASE2 0xff800000 + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + + +/*Sri: This looks like a good place to init all the Local Bus chip selects*/ + +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ + +#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ + +#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ + +#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + +#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ +#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ +#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/*#define CFG_HPCN_FLASH_CFI_DRIVER */ +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#if !defined(CFG_RAMBOOT) +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#undef CFG_INIT_RAM_LOCK +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/* RapidIO MMU */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +//#define CFG_PCI1_MEM_BASE 0xd0000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +//#define CFG_PCI1_IO_BASE 0xe0000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +//#define CFG_PCI1_IO_BUS 0x00000000 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* For RTL8139 */ +#define _IO_BASE 0x00000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +// #define CFG_PCI1_MEM_BASE 0x80000000 +// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +// #define CFG_PCI1_IO_BASE 0xe2000000 +// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + + + +#if defined(CONFIG_PCI) + + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +//#define CFG_SCSI_SCAN_BUS_REVERSE + + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_RTL8139 + + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ + +#define CONFIG_MPC86XX_TSEC1 1 +#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" +#define CONFIG_MPC86XX_TSEC2 1 +#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" +#define CONFIG_MPC86XX_TSEC3 1 +#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" +#define CONFIG_MPC86XX_TSEC4 1 +#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" + + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + + +/* BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) +//#define CFG_IBAT0L CFG_DBAT0L +//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_IBAT0U CFG_DBAT0U + +/* BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + ** SS - Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + ** SS - Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + + + + +/* + * Environment + */ + #ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + #else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 + #endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 10.82.193.138 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 10.82.193.104 +#define CONFIG_GATEWAYIP 10.82.193.254 +#define CONFIG_NETMASK 255.255.252.0 + +#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ + "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ + "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ + "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ + "pex=run pexstat; run pex1; run pexd\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=2" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575d9..5c5e06309 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -58,7 +58,9 @@ void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); - +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd); +#endif void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); diff --git a/include/mpc86xx.h b/include/mpc86xx.h new file mode 100644 index 000000000..61b527979 --- /dev/null +++ b/include/mpc86xx.h @@ -0,0 +1,119 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeffrey Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + */ + +#ifndef __MPC86xx_H__ +#define __MPC86xx_H__ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ + +/*---------------------------------------------------------------- + * l2cr values. Look in config_.h for the actual setup + */ +#define l2cr 1017 + +#define L2CR_L2E 0x80000000 /* bit 0 - enable */ +#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ +#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ +#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ +#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ +#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ +#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ +#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ + +/*---------------------------------------------------------------- + * BAT settings. Look in config_.h for the actual setup + */ + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +#define HID0_XBSEN 0x00000100 +#define HID0_HIGH_BAT_EN 0x00800000 +#define HID0_XAEN 0x00020000 + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqProcessor; + unsigned long freqSystemBus; +} MPC86xx_SYS_INFO; + +#define l1icache_enable icache_enable + +void l2cache_enable(void); +void l1dcache_enable(void); + +static __inline__ unsigned long get_hid0 (void) +{ + unsigned long hid0; + asm volatile("mfspr %0, 1008" : "=r" (hid0) :); + return hid0; +} + +static __inline__ unsigned long get_hid1 (void) +{ + unsigned long hid1; + asm volatile("mfspr %0, 1009" : "=r" (hid1) :); + return hid1; +} + +static __inline__ void set_hid0 (unsigned long hid0) +{ + asm volatile("mtspr 1008, %0" : : "r" (hid0)); +} + +static __inline__ void set_hid1 (unsigned long hid1) +{ + asm volatile("mtspr 1009, %0" : : "r" (hid1)); +} + + +static __inline__ unsigned long get_l2cr (void) +{ + unsigned long l2cr_val; + asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); + return l2cr_val; +} + +#endif /* _ASMLANGUAGE */ +#endif /* __MPC86xx_H__ */ + + diff --git a/include/pci.h b/include/pci.h index 0fc00e427..705d1fcd8 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,12 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index e68cf1fe7..126102bf9 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -503,7 +503,7 @@ void board_init_f (ulong bootflag) #endif #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ - defined(CONFIG_E500) + defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) diff --git a/net/eth.c b/net/eth.c index 9341e20e9..3039fc81e 100644 --- a/net/eth.c +++ b/net/eth.c @@ -195,6 +195,22 @@ int eth_initialize(bd_t *bis) tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME); # endif #endif +#if defined(CONFIG_MPC86XX_TSEC1) + tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME); +#endif + +#if defined(CONFIG_MPC86XX_TSEC2) + tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME); +#endif + +#if defined(CONFIG_MPC86XX_TSEC3) + tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME); +#endif + +#if defined(CONFIG_MPC86XX_TSEC4) + tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME); +#endif + #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); #endif From a2320a6bf8113a09544c42d160d10ac69d049a03 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 27 Apr 2006 08:22:39 -0500 Subject: [PATCH 002/101] Revert bad PCI prefetch limit change. --- drivers/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 3c958d3b9..15f74328f 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -186,7 +186,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); } if (pci_io) { From 5c9efb36a6b5431423f52888a0e3b4b515fe7eca Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 27 Apr 2006 10:15:16 -0500 Subject: [PATCH 003/101] Cleanup whitespaces and style issues. Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft. --- board/mpc8641hpcn/mpc8641hpcn.c | 33 ++-- board/mpc8641hpcn/oftree.dts | 2 +- cpu/mpc86xx/cpu.c | 258 +++++++++++++++----------------- cpu/mpc86xx/cpu_init.c | 17 +-- cpu/mpc86xx/i2c.c | 68 ++++----- cpu/mpc86xx/interrupts.c | 23 ++- cpu/mpc86xx/pci.c | 105 +++++-------- cpu/mpc86xx/spd_sdram.c | 9 +- cpu/mpc86xx/speed.c | 254 +++++++++++++++---------------- cpu/mpc86xx/start.S | 4 +- cpu/mpc86xx/traps.c | 2 - include/configs/MPC8641HPCN.h | 203 +++++++++++-------------- include/mpc86xx.h | 6 +- 13 files changed, 434 insertions(+), 550 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index cdfce6c1f..ace6d47fd 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -57,9 +57,6 @@ int checkboard (void) #ifdef CONFIG_PCI - /* Sri: Note that at this point we will only test on PCI1 - */ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; volatile ccsr_pex_t *pex1 = &immap->im_pex1; @@ -70,13 +67,16 @@ int checkboard (void) uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - debug ("PCI-EXPRESS 1: %s \n", - pex1_agent ? "Agent" : "Host"); + if ((io_sel==2 || io_sel==3 || io_sel==5 \ + || io_sel==6 || io_sel==7 || io_sel==0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + debug ("PCI-EXPRESS 1: %s \n", + pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); if (pex1->pme_msg_det) { pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); } debug ("\n"); } else { @@ -120,15 +120,6 @@ initdram(int board_type) ddr_enable_ecc(dram_size); #endif - /* - * Initialize SDRAM. Currently HPCN doesn't have - * SDRAM but we'll leave this here for now - * in case someone changes their mind - */ -#if !defined(CONFIG_MPC8641HPCN) - // sdram_init(); -#endif - puts(" DDR: "); return dram_size; } @@ -163,7 +154,7 @@ local_bus_init(void) } #if defined(CFG_DRAM_TEST) -int testdram (void) +int testdram(void) { uint *pstart = (uint *) CFG_MEMTEST_START; uint *pend = (uint *) CFG_MEMTEST_END; @@ -198,10 +189,10 @@ int testdram (void) #if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +long int fixed_sdram(void) { #if !defined(CFG_RAMBOOT) volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 6c32ade0c..8e38047e7 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -1,5 +1,5 @@ /* - * MPC8641 HPCn Device Tree Source + * MPC8641 HPCN Device Tree Source * * Copyright 2006 Freescale Semiconductor Inc. * diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index b0fe8abb2..36da7774e 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -32,31 +32,30 @@ #include #endif +extern unsigned long get_board_sys_clk(ulong dummy); -// SS: For debug only, remove after use static __inline__ unsigned long get_dbat3u (void) { - unsigned long dbat3u; - asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); - return dbat3u; + unsigned long dbat3u; + asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); + return dbat3u; } static __inline__ unsigned long get_dbat3l (void) { - unsigned long dbat3l; - asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); - return dbat3l; + unsigned long dbat3l; + asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); + return dbat3l; } static __inline__ unsigned long get_msr (void) { - unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; + unsigned long msr; + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; } -extern unsigned long get_board_sys_clk(ulong dummy); int checkcpu (void) { @@ -66,7 +65,7 @@ int checkcpu (void) uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ - + puts("Freescale PowerPC\n"); pvr = get_pvr(); @@ -74,10 +73,10 @@ int checkcpu (void) major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); - puts ("CPU:\n"); + puts("CPU:\n"); printf(" Core: "); - + switch (ver) { case PVR_VER(PVR_86xx): puts("E600"); @@ -94,7 +93,7 @@ int checkcpu (void) minor = SVR_MIN(svr); puts(" System: "); - switch (ver) { + switch (ver) { case SVR_8641: puts("8641"); break; @@ -113,7 +112,7 @@ int checkcpu (void) printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); - + #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else @@ -134,11 +133,11 @@ int checkcpu (void) printf(" L2: "); if (get_l2cr() & 0x80000000) - printf("Enabled\n"); + printf("Enabled\n"); else - printf("Disabled\n"); - - return (0); + printf("Disabled\n"); + + return 0; } @@ -149,7 +148,7 @@ soft_restart(unsigned long addr) { #ifndef CONFIG_MPC8641HPCN - + /* SRR0 has system reset vector, SRR1 has default MSR value */ /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ @@ -215,7 +214,7 @@ int set_px_sysclk(ulong sysclk) sysclk_s = 0x06; sysclk_r = 0x1F; sysclk_v = 0x3B; - sysclk_aux = 0x06; + sysclk_aux = 0x06; break; case 166: sysclk_s = 0x06; @@ -227,14 +226,14 @@ int set_px_sysclk(ulong sysclk) printf("Unsupported SYSCLK frequency.\n"); return 0; } - + vclkh = (sysclk_s << 5) | sysclk_r ; vclkl = sysclk_v; out8(PIXIS_BASE+PIXIS_VCLKH,vclkh); out8(PIXIS_BASE+PIXIS_VCLKL,vclkl); out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux); - + return 1; } @@ -262,7 +261,7 @@ int set_px_mpxpll(ulong mpxpll) tmp = in8(PIXIS_BASE+PIXIS_VSPEED1); tmp = (tmp & 0xF0) | (val & 0x0F); out8(PIXIS_BASE+PIXIS_VSPEED1,tmp); - + return 1; } @@ -270,9 +269,8 @@ int set_px_corepll(ulong corepll) { u8 tmp; u8 val; - - switch((int)corepll) - { + + switch ((int)corepll) { case 20: val = 0x08; break; @@ -295,11 +293,11 @@ int set_px_corepll(ulong corepll) printf("Unsupported COREPLL ratio.\n"); return 0; } - + tmp = in8(PIXIS_BASE+PIXIS_VSPEED0); tmp = (tmp & 0xE0) | (val & 0x1F); out8(PIXIS_BASE+PIXIS_VSPEED0,tmp); - + return 1; } @@ -311,7 +309,7 @@ void read_from_px_regs(int set) tmp = tmp | mask; else tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); + out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); } void read_from_px_regs_altbank(int set) @@ -322,7 +320,7 @@ void read_from_px_regs_altbank(int set) tmp = tmp | mask; else tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); + out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); } void set_altbank(void) @@ -342,7 +340,7 @@ void set_px_go(void) out8(PIXIS_BASE+PIXIS_VCTL,tmp); tmp = in8(PIXIS_BASE+PIXIS_VCTL); tmp = tmp | 0x01; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); + out8(PIXIS_BASE+PIXIS_VCTL,tmp); } void set_px_go_with_watchdog(void) @@ -353,7 +351,7 @@ void set_px_go_with_watchdog(void) out8(PIXIS_BASE+PIXIS_VCTL,tmp); tmp = in8(PIXIS_BASE+PIXIS_VCTL); tmp = tmp | 0x09; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); + out8(PIXIS_BASE+PIXIS_VCTL,tmp); } /* This function takes the non-integral cpu:mpx pll ratio @@ -381,11 +379,11 @@ ulong strfractoint(uchar *strptr) no_dec = 1; break; /* Break from loop once the end of string is reached */ } - + intarr[i] = strptr[i]; i++; } - + intarr_len = i; /* Assign length of integer part to intarr_len*/ intarr[i] = '\0'; /* */ @@ -404,14 +402,14 @@ ulong strfractoint(uchar *strptr) i++; j++; } - + decarr_len = j; decarr[j] = '\0'; - + mulconst=1; for(i=0; i 1) - { - cmd = argv[1][1]; - switch(cmd) - { - case 'f': /* reset with frequency changed */ - if (argc < 5) - goto my_usage; - - read_from_px_regs(0); - - val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); - - corepll = strfractoint(argv[3]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10)); - if(val == 3) - { - printf("Setting registers VCFGEN0 and VCTL\n"); - read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); - } - else - goto my_usage; - - while(1); /* Not reached */ - - case 'l': - if(argv[2][1] == 'f') - { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); - if(val == 3) - { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - - } - else - goto my_usage; - - while(1); /* Not reached */ - } - else /* Reset from next bank without changing frequencies */ - { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - } + if (argc > 1) { + cmd = argv[1][1]; + switch(cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], + NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1); /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); + if (val == 3) { + printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + } else + goto my_usage; + + while(1); /* Not reached */ + } else { + /* Reset from next bank without changing frequencies */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + } + + default: + goto my_usage; + } - default: - goto my_usage; - } my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; - } - else - out8(PIXIS_BASE+PIXIS_RST,0); - + printf("\nUsage: reset cf \n"); + printf(" reset altbank [cf ]\n"); + printf("For example: reset cf 40 2.5 10\n"); + printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); + return; + } else + out8(PIXIS_BASE+PIXIS_RST,0); + #endif /* !CONFIG_MPC8641HPCN */ - + while(1); /* not reached */ } -/* ------------------------------------------------------------------------- */ - /* * Get timebase clock frequency */ @@ -566,24 +550,21 @@ unsigned long get_tbclk(void) sys_info_t sys_info; get_sys_info(&sys_info); - return ((sys_info.freqSystemBus + 3L) / 4L); - + return (sys_info.freqSystemBus + 3L) / 4L; } -/* ------------------------------------------------------------------------- */ #if defined(CONFIG_WATCHDOG) void watchdog_reset(void) { - } #endif /* CONFIG_WATCHDOG */ -/* ------------------------------------------------------------------------- */ #if defined(CONFIG_DDR_ECC) -void dma_init(void) { +void dma_init(void) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; @@ -593,7 +574,8 @@ void dma_init(void) { return; } -uint dma_check(void) { +uint dma_check(void) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; volatile uint status = dma->sr0; @@ -609,7 +591,8 @@ uint dma_check(void) { return status; } -int dma_xfer(void *dest, uint count, void *src) { +int dma_xfer(void *dest, uint count, void *src) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; @@ -622,6 +605,7 @@ int dma_xfer(void *dest, uint count, void *src) { asm("sync;isync"); return dma_check(); } + #endif /* CONFIG_DDR_ECC */ @@ -631,7 +615,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) u32 *p; ulong clock; int len; - + clock = bd->bi_busfreq; p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); if (p != NULL) @@ -649,7 +633,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); memcpy(p, bd->bi_enetaddr, 6); #endif - + #if defined(CONFIG_MPC86XX_TSEC2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); memcpy(p, bd->bi_enet1addr, 6); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 582ac6ba9..c816c1897 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -36,13 +36,12 @@ * initialize a bunch of registers */ -void cpu_init_f (void) +void cpu_init_f(void) { DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; - //u8 val; - + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); @@ -72,23 +71,21 @@ void cpu_init_f (void) memctl->br1 = CFG_BR1_PRELIM; #endif - //#if !defined(CONFIG_MPC86xx) #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; memctl->br2 = CFG_BR2_PRELIM; #endif - //#endif - + #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) memctl->or3 = CFG_OR3_PRELIM; memctl->br3 = CFG_BR3_PRELIM; #endif - + #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) memctl->or4 = CFG_OR4_PRELIM; memctl->br4 = CFG_BR4_PRELIM; #endif - + #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) memctl->or5 = CFG_OR5_PRELIM; memctl->br5 = CFG_BR5_PRELIM; @@ -123,9 +120,9 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { - return (0); + return 0; } diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c index c5d4642b9..f2b4b0f6d 100644 --- a/cpu/mpc86xx/i2c.c +++ b/cpu/mpc86xx/i2c.c @@ -74,29 +74,27 @@ i2c_init(int speed, int slaveadd) } static __inline__ int -i2c_wait4bus (void) +i2c_wait4bus(void) { ulong timeval = get_timer (0); - // debug("I2C: Wait for bus\n"); while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { - if (get_timer (timeval) > TIMEOUT) { + if (get_timer(timeval) > TIMEOUT) { return -1; } } - return 0; + return 0; } static __inline__ int -i2c_wait (int write) +i2c_wait(int write) { u32 csr; ulong timeval = get_timer (0); do { csr = readb(I2CCSR); - if (!(csr & MPC86xx_I2CSR_MIF)) continue; @@ -118,7 +116,7 @@ i2c_wait (int write) } return 0; - } while (get_timer (timeval) < TIMEOUT); + } while (get_timer(timeval) < TIMEOUT); debug("i2c_wait: timed out\n"); return -1; @@ -127,14 +125,13 @@ i2c_wait (int write) static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) { - // debug("I2C: Write Addr\n"); - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX | - (rsta?MPC86xx_I2CCR_RSTA:0), + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX + | (rsta ? MPC86xx_I2CCR_RSTA : 0), I2CCCR); writeb((dev << 1) | dir, I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) + if (i2c_wait(I2C_WRITE) < 0) return 0; return 1; @@ -144,14 +141,14 @@ static __inline__ int __i2c_write (u8 *data, int length) { int i; - // debug("I2C: __i2c_write\n"); + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX, I2CCCR); - for (i=0; i < length; i++) { + for (i = 0; i < length; i++) { writeb(data[i], I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) + if (i2c_wait(I2C_WRITE) < 0) break; } @@ -163,33 +160,30 @@ __i2c_read (u8 *data, int length) { int i; - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | - ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA + | ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), I2CCCR); /* dummy read */ readb(I2CCDR); - // debug("length = %d\n", length); - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) + for (i = 0; i < length; i++) { + if (i2c_wait(I2C_READ) < 0) break; /* Generate ack on last next to last byte */ if (i == length - 2) - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | - MPC86xx_I2CCR_TXAK, + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA + | MPC86xx_I2CCR_TXAK, I2CCCR); /* Generate stop on last byte */ if (i == length - 1) writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR); - // debug("I2CCR = 0x%08x\n", readb(I2CCCR)); data[i] = readb(I2CCDR); - // debug("data[i] = 0x%08x\n", data[i]); } - // debug("Returning i = %d\n", i); + return i; } @@ -199,19 +193,19 @@ i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) + if (i2c_wait4bus() < 0) goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) + if (__i2c_write(&a[4 - alen], alen) != alen) goto exit; - if (i2c_write_addr (dev, I2C_READ, 1) == 0) + if (i2c_write_addr(dev, I2C_READ, 1) == 0) goto exit; - i = __i2c_read (data, length); + i = __i2c_read(data, length); exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); @@ -225,16 +219,16 @@ i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) + if (i2c_wait4bus() < 0) goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) + if (__i2c_write(&a[4 - alen], alen) != alen) goto exit; - i = __i2c_write (data, length); + i = __i2c_write(data, length); exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); @@ -253,21 +247,21 @@ int i2c_probe (uchar chip) */ udelay(10000); - return i2c_read (chip, 0, 1, (char *)&tmp, 1); + return i2c_read(chip, 0, 1, (char *)&tmp, 1); } uchar i2c_reg_read (uchar i2c_addr, uchar reg) { char buf[1]; - i2c_read (i2c_addr, reg, 1, buf, 1); + i2c_read(i2c_addr, reg, 1, buf, 1); - return (buf[0]); + return buf[0]; } void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) { - i2c_write (i2c_addr, reg, 1, &val, 1); + i2c_write(i2c_addr, reg, 1, &val, 1); } #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 759a30f9f..b5cd439e5 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -75,7 +75,7 @@ static __inline__ void set_dec (unsigned long val) /* interrupt is not supported yet */ int interrupt_init_cpu (unsigned *decrementer_count) { - return (0); + return 0; } @@ -91,14 +91,14 @@ int interrupt_init (void) decrementer_count = get_tbclk()/CFG_HZ; debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); - + set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); - - return (0); + + return 0; } @@ -113,7 +113,7 @@ int disable_interrupts (void) ulong msr = get_msr (); set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); + return (msr & MSR_EE) != 0; } @@ -131,7 +131,6 @@ void timer_interrupt_cpu (struct pt_regs *regs) { /* nothing to do here */ - return; } @@ -139,14 +138,14 @@ void timer_interrupt (struct pt_regs *regs) { /* call cpu specific function from $(CPU)/interrupts.c */ timer_interrupt_cpu (regs); - + timestamp++; ppcDcbf(×tamp); - + /* Restore Decrementer Count */ set_dec (decrementer_count); - + #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) WATCHDOG_RESET (); @@ -169,8 +168,8 @@ void reset_timer (void) } ulong get_timer (ulong base) -{ - return (timestamp - base); +{ + return timestamp - base; } void set_timer (ulong t) @@ -185,13 +184,11 @@ void set_timer (ulong t) void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) { - return; } void irq_free_handler(int vec) { - return; } diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c index 9cf5f7ca9..05976bdd4 100644 --- a/cpu/mpc86xx/pci.c +++ b/cpu/mpc86xx/pci.c @@ -22,7 +22,7 @@ */ /* - * PEX Configuration space access support for MPC85xx PEX Bridge + * PEX Configuration space access support for PEX Bridge */ #include #include @@ -44,24 +44,25 @@ pci_mpc86xx_init(struct pci_controller *hose) ulong addr, data; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - - if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + + if ((io_sel==2 || io_sel==3 || io_sel==5 + || io_sel==6 || io_sel==7 || io_sel==0xF ) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ printf ("PCI-EXPRESS 1: Configured as %s \n", pex1_agent ? "Agent" : "Host"); printf (" Scanning PCI bus"); debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); if (pex1->pme_msg_det) { pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); } debug ("\n"); } - - + hose->first_busno = 0; hose->last_busno = 0x7f; @@ -88,36 +89,26 @@ pci_mpc86xx_init(struct pci_controller *hose) */ pci_register_hose(hose); - //#define MPC8548_REV1_PEX12_ERRATA -#ifdef MPC8548_REV1_PEX12_ERRATA - /* can only read/write 4 bytes */ - pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®32); - printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32); - - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®32); - reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32); -#else pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY \ + | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16); - -#endif - /* * Clear non-reserved bits in status register. */ - // pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - // pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + /* + * pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + * pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + */ pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; pex1->powar1 = 0x8004401c; /* 512M MEM space */ @@ -129,7 +120,6 @@ pci_mpc86xx_init(struct pci_controller *hose) pex1->potar2 = 0x00000000; pex1->potear2 = 0x00000000; - if (!pex1->piwar1) { pex1->pitar1 = 0x00000000; pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff; @@ -140,57 +130,34 @@ pci_mpc86xx_init(struct pci_controller *hose) pex1->pitar2 = 0x00000000; pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff; pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - + * Snoop R/W, 2G */ - -/* if (pex1_host) { */ -/* #ifdef MPC8548_REV1_PEX12_ERRATA */ -/* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */ -/* #else */ + *(u32 *)(0xf8008000)= 0x80000000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - *(u32 *)(0xf8008000)= 0x80000000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); -/* #endif */ - - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - - - hose->last_busno = pci_hose_scan(hose); - hose->last_busno = 0x21; - debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); - debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); - - - printf("....PCI scan & enumeration done\n"); - -/* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */ -/* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */ - -/* if (hose->last_busno < 1) { */ -/* hose->last_busno=1; /\*Hack*\/ */ -/* } else { */ -/* hose->last_busno = 0; */ -/* } */ -/*}*/ -/* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, ®32); */ -/* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */ - + hose->last_busno = pci_hose_scan(hose); + hose->last_busno = 0x21; + debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); + debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); + printf("....PCI scan & enumeration done\n"); } + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 9c07f200f..9ce31d7c6 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -179,7 +179,7 @@ spd_sdram(void) unsigned int law_size; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; - + /* * Read SPD information. */ @@ -614,7 +614,7 @@ spd_sdram(void) ddr1->timing_cfg_2 = (0 | ((add_lat & 0x7) << 28) /* ADD_LAT */ - | ((cpo & 0x1f) << 23) /* CPO */ + | ((cpo & 0x1f) << 23) /* CPO */ | ((wr_lat & 0x7) << 19) /* WR_LAT */ | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ @@ -806,7 +806,7 @@ spd_sdram(void) /* * Memory will be initialized via DMA, or not at all. */ - d_init = 0; + d_init = 0; #endif ddr1->sdram_cfg_2 = (0 @@ -946,8 +946,7 @@ spd_sdram(void) | (LAWAR_SIZE & law_size)); debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); debug("DDR: LARAR1=0x%08x\n", mcm->lawar1); - - + return memsize * 1024 * 1024; } diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 0f5a6388c..a08ae5f94 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -33,9 +33,7 @@ unsigned long get_board_sys_clk(ulong dummy); unsigned long get_sysclk_from_px_regs(void); -/* --------------------------------------------------------------- */ - -void get_sys_info (sys_info_t * sysInfo) +void get_sys_info (sys_info_t *sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -43,7 +41,7 @@ void get_sys_info (sys_info_t * sysInfo) plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - + switch(plat_ratio) { case 0x0: sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; @@ -65,72 +63,77 @@ void get_sys_info (sys_info_t * sysInfo) break; } - // printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", sysInfo->freqSystemBus, plat_ratio); +#if 0 + printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", + sysInfo->freqSystemBus, plat_ratio); +#endif + e600_ratio = (gur->porpllsr) & 0x003f0000; e600_ratio >>= 16; - switch(e600_ratio) { + + switch (e600_ratio) { case 0x10: - sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; break; - case 0x19: - sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; + case 0x19: + sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2; break; case 0x20: - sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; break; case 0x39: - sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2; break; case 0x28: - sysInfo->freqProcessor = 4*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus; break; case 0x1d: - sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2; break; default: - /* JB - Emulator workaround until real cop is plugged in */ - sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; - //sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + /* JB - Emulator workaround until real cop is plugged in */ + /* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */ + sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; break; } - // printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", sysInfo->freqProcessor, e600_ratio); - +#if 0 + printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", + sysInfo->freqProcessor, e600_ratio); +#endif } -/* ------------------------------------------------------------------------- */ - /* * Measure CPU clock speed (core clock GCLK1, GCLK2) - * * (Approx. GCLK frequency in Hz) */ -int get_clocks (void) +int get_clocks(void) { DECLARE_GLOBAL_DATA_PTR; sys_info_t sys_info; - get_sys_info (&sys_info); + get_sys_info(&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; - - if(gd->cpu_clk != 0) return (0); - else return (1); + + if (gd->cpu_clk != 0) + return 0; + else + return 1; } -/* ------------------------------------------------------------------------- */ -/******************************************** + +/* * get_bus_freq - * return system bus freq in Hz - *********************************************/ -ulong get_bus_freq (ulong dummy) + * Return system bus freq in Hz + */ +ulong get_bus_freq(ulong dummy) { ulong val; - sys_info_t sys_info; - get_sys_info (&sys_info); + get_sys_info(&sys_info); val = sys_info.freqSystemBus; return val; @@ -138,111 +141,100 @@ ulong get_bus_freq (ulong dummy) unsigned long get_sysclk_from_px_regs() { - ulong val; - u8 vclkh,vclkl; - - vclkh = in8(PIXIS_BASE+PIXIS_VCLKH); - vclkl = in8(PIXIS_BASE+PIXIS_VCLKL); - - if((vclkh == 0x84) && (vclkl ==0x07)) - { - val = 33000000; - } - if((vclkh == 0x3F) && (vclkl ==0x20)) - { - val = 40000000; - } - if((vclkh == 0x3F) && (vclkl ==0x2A)) - { - val = 50000000; - } - if((vclkh == 0x24) && (vclkl ==0x04)) - { - val = 66000000; - } - if((vclkh == 0x3F) && (vclkl ==0x4B)) - { - val = 83000000; - } - if((vclkh == 0x3F) && (vclkl ==0x5C)) - { - val = 100000000; - } - if((vclkh == 0xDF) && (vclkl ==0x3B)) - { - val = 134000000; - } - if((vclkh == 0xDF) && (vclkl ==0x4B)) - { - val = 166000000; - } - - return val; + ulong val; + u8 vclkh, vclkl; + + vclkh = in8(PIXIS_BASE + PIXIS_VCLKH); + vclkl = in8(PIXIS_BASE + PIXIS_VCLKL); + + if ((vclkh == 0x84) && (vclkl == 0x07)) { + val = 33000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x20)) { + val = 40000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x2A)) { + val = 50000000; + } + if ((vclkh == 0x24) && (vclkl == 0x04)) { + val = 66000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x4B)) { + val = 83000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x5C)) { + val = 100000000; + } + if ((vclkh == 0xDF) && (vclkl == 0x3B)) { + val = 134000000; + } + if ((vclkh == 0xDF) && (vclkl == 0x4B)) { + val = 166000000; + } + + return val; } -/******* From MPC8641HPCN Design Workbook ************ - * + +/* * get_board_sys_clk - * reads the FPGA on board for CONFIG_SYS_CLK_FREQ - * - ********************************************************/ + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ unsigned long get_board_sys_clk(ulong dummy) { - u8 i, go_bit, rd_clks; - ulong val; + u8 i, go_bit, rd_clks; + ulong val; - go_bit = in8(PIXIS_BASE+PIXIS_VCTL); - go_bit &= 0x01; + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; - rd_clks = in8(PIXIS_BASE+PIXIS_VCFGEN0); - rd_clks &= 0x1C; + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; - /* Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if(go_bit) - { - if(rd_clks == 0x1c) - i = in8(PIXIS_BASE+PIXIS_AUX); - else - i = in8(PIXIS_BASE+PIXIS_SPD); - //val = get_sysclk_from_px_regs(); - } - else - i = in8(PIXIS_BASE+PIXIS_SPD); - - i &= 0x07; - - switch(i) - { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; } diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 531bd0c5f..0a447a76b 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -783,12 +783,12 @@ ppcDcbz: dcbz r0,r3 blr -/*------------------------------------------------------------------------------- */ +/*-------------------------------------------------------------------------- */ /* Function: ppcSync */ /* Description: Processor Synchronize */ /* Input: none. */ /* Output: none. */ -/*------------------------------------------------------------------------------- */ +/*-------------------------------------------------------------------------- */ .globl ppcSync ppcSync: sync diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index fdfc95dfc..8113dfbcc 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -1,6 +1,4 @@ /* - * linux/arch/ppc/kernel/traps.c - * * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) * * Modified by Cort Dougan (cort@cs.nmt.edu) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 8d2e08851..76efd7c60 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,6 @@ -/* - * Copyright 2004 Freescale Semiconductor. +/* + * Copyright 2006 Freescale Semiconductor. + * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -22,8 +23,7 @@ */ /* - * mpc8641hpc3 board configuration file - * + * MPC8641HPCN board configuration file * * Make sure you change the MAC address and other network params first, * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. @@ -38,48 +38,38 @@ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#undef DEBUG +#undef DEBUG -//#define RUN_DIAG 1 #ifdef RUN_DIAG #define CFG_DIAG_ADDR 0xff800000 #endif + #define CFG_RESET_ADDRESS 0xfff00100 -//#define CONFIG_PCI +#undef CONFIG_PCI + #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ -/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ + +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - - #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_ALTIVEC 1 -#define CONFIG_ALTIVEC 1 -/*----------------------------------------------------------------------- +/* * L2CR setup -- make sure this is right for your board! */ - -#define CFG_L2 +#define CFG_L2 #define L2_INIT 0 #define L2_ENABLE (L2CR_L2E) #ifndef CONFIG_SYS_CLK_FREQ -//#define CONFIG_SYS_CLK_FREQ 33000000 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -/* JB - XXX - Are these available on 86xx? */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CFG_DRAM_TEST /* memory test, takes time */ @@ -130,10 +120,10 @@ #define CFG_DDR_INTERVAL 0x06090100 #define CFG_DDR_DATA_INIT 0xdeadbeef #define CFG_DDR_CLK_CTRL 0x03800000 - #define CFG_DDR_OCD_CTRL 0x00000000 - #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ - #define CFG_DDR_CONTROL2 0x04400000 + #define CFG_DDR_CONTROL2 0x04400000 //Not used in fixed_sdram function @@ -143,20 +133,12 @@ #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done - - - #endif #endif /* - * SDRAM on the Local Bus - */ -//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 + * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. * However, when u-boot comes up, the flash_init needs hard start addresses @@ -165,15 +147,12 @@ * knows where the flash is and the user can download u-boot code from promjet to * fef00000 <- more intuitive than fe700000. Note that, on switching the boot * location, fef00000 becomes fff00000. -*/ + */ #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ -#define CFG_FLASH_BASE2 0xff800000 +#define CFG_FLASH_BASE2 0xff800000 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} - -/*Sri: This looks like a good place to init all the Local Bus chip selects*/ - #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ @@ -186,25 +165,24 @@ #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ -#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ -#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ -#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ -#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ #undef CFG_FLASH_CHECKSUM @@ -212,11 +190,9 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -/*#define CFG_HPCN_FLASH_CFI_DRIVER */ #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO - #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else @@ -230,7 +206,7 @@ #undef CONFIG_CLOCKS_IN_MHZ #define CONFIG_L1_INIT_RAM -#undef CFG_INIT_RAM_LOCK +#undef CFG_INIT_RAM_LOCK #ifndef CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ #else @@ -265,20 +241,22 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 /* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_FLAT_TREE_MAX_SIZE 8192 -#define OF_CPU "PowerPC,8641@0" -#define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" -#define CFG_64BIT_VSPRINTF 1 -#define CFG_64BIT_STRTOUL 1 +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ @@ -297,13 +275,10 @@ * Addresses are mapped 1-1. */ #define CFG_PCI1_MEM_BASE 0x80000000 -//#define CFG_PCI1_MEM_BASE 0xd0000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0xe2000000 -//#define CFG_PCI1_IO_BASE 0xe0000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -//#define CFG_PCI1_IO_BUS 0x00000000 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ /* For RTL8139 */ @@ -316,29 +291,18 @@ #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ -// #define CFG_PCI1_MEM_BASE 0x80000000 -// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -// #define CFG_PCI1_IO_BASE 0xe2000000 -// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - - #if defined(CONFIG_PCI) - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -//#define CFG_SCSI_SCAN_BUS_REVERSE - +#undef CFG_SCSI_SCAN_BUS_REVERSE #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_RTL8139 - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -349,7 +313,6 @@ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ @@ -371,7 +334,6 @@ #define CONFIG_MPC86XX_TSEC4 1 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" - #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 @@ -389,12 +351,10 @@ /* BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) -//#define CFG_IBAT0L CFG_DBAT0L -//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) +#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) +#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) #define CFG_IBAT0U CFG_DBAT0U /* BAT1 1G Cache-inhibited, guarded @@ -402,7 +362,8 @@ * 0xa000_0000 512M PCI-Express 2 Memory ** SS - Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U @@ -410,7 +371,8 @@ /* BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U @@ -418,7 +380,8 @@ /* BAT3 4M Cache-inhibited, guarded * 0xf800_0000 4M CCSR */ -#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U @@ -428,7 +391,8 @@ * 0xe300_0000 16M PCI-Express 2 I/0 ** SS - Note that this is at 0xe0000000 */ -#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U @@ -444,12 +408,12 @@ /* BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U CFG_DBAT6U - #define CFG_DBAT7L 0x00000000 #define CFG_DBAT7U 0x00000000 #define CFG_IBAT7L 0x00000000 @@ -461,17 +425,17 @@ /* * Environment */ - #ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 - #endif +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -572,24 +536,25 @@ #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 -#define CONFIG_HAS_ETH3 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 -#define CONFIG_IPADDR 10.82.193.138 +#define CONFIG_IPADDR 10.82.193.138 #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage -#define CONFIG_SERVERIP 10.82.193.104 -#define CONFIG_GATEWAYIP 10.82.193.254 -#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 10.82.193.104 +#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BAUDRATE 115200 @@ -599,7 +564,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=400000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ + "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 61b527979..4edeae164 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2006 Freescale Semiconductor. * Jeffrey Brown (jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) */ @@ -9,7 +9,7 @@ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ -/*---------------------------------------------------------------- +/* * l2cr values. Look in config_.h for the actual setup */ #define l2cr 1017 @@ -23,7 +23,7 @@ #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/*---------------------------------------------------------------- +/* * BAT settings. Look in config_.h for the actual setup */ From 18b6c8cd8af6cc7f35180cedc4adb3236cc1a1b8 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 9 May 2006 08:23:49 -0500 Subject: [PATCH 004/101] Get MPC8641HPCN flash images working. Enable the CFI driver. Remove bogus LAWBAR7 cruft. Use correct TEXT_BASE, Fixup load script. Enable SPD EEPROM during DDR setup. Use generic RFC 1918 IP addresses by default. --- board/mpc8641hpcn/config.mk | 3 +-- board/mpc8641hpcn/init.S | 17 ----------------- board/mpc8641hpcn/u-boot.lds | 4 ++-- include/configs/MPC8641HPCN.h | 30 ++++++++++++++---------------- 4 files changed, 17 insertions(+), 37 deletions(-) diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk index 63b9779af..4bdceec4d 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/mpc8641hpcn/config.mk @@ -25,8 +25,7 @@ # default CCSRBAR is at 0xff700000 # assume U-Boot is less than 0.5MB # -#TEXT_BASE = 0xfff01000 -TEXT_BASE = 0x00400000 +TEXT_BASE = 0xfff01000 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 9d43de553..4d555a509 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -80,23 +80,6 @@ #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -/* -#ifdef CFG_INIT_RAM_LOCK -#define LAWBAR7 ((CFG_RIO_MEM_BASE>>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#endif -*/ -/* - * Stack at 0xfc00_0000 for 32M on LBC - */ -#if !defined(CFG_INIT_RAM_LOCK) -#define LAWBAR7 ((CFG_INIT_RAM_ADDR>>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) -#endif - .section .bootpg, "ax" .globl law_entry law_entry: diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index dbe8e4fab..c5c40e7eb 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -28,7 +28,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/ __DYNAMIC = 0; */ SECTIONS { -/* .resetvec 0xFFF00100 : + .resetvec 0xFFF00100 : { *(.resetvec) } = 0xffff @@ -38,7 +38,7 @@ SECTIONS cpu/mpc86xx/start.o (.bootpg) board/mpc8641hpcn/init.o (.bootpg) } = 0xffff -*/ + /* Read-only sections, merged into text segment: */ . = + 1024; .interp : { *(.interp) } diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 76efd7c60..d4a28edf9 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -51,6 +51,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -102,11 +103,9 @@ #else /* - * Manually set up DDR parameters + * Manually set up DDR1 parameters */ -/* DDR I */ -#if 1 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ #define CFG_DDR_CS0_BNDS 0x0000000F @@ -125,15 +124,14 @@ #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ #define CFG_DDR_CONTROL2 0x04400000 - //Not used in fixed_sdram function + /* Not used in fixed_sdram function */ #define CFG_DDR_MODE 0x00000022 #define CFG_DDR_CS1_BNDS 0x00000000 - #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done - #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done -#endif + #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ #endif @@ -190,6 +188,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO @@ -199,14 +198,14 @@ #undef CFG_RAMBOOT #endif -#if !defined(CFG_RAMBOOT) -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT) +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #endif #undef CONFIG_CLOCKS_IN_MHZ #define CONFIG_L1_INIT_RAM -#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_LOCK 1 #ifndef CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ #else @@ -540,22 +539,21 @@ #define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH3 1 -#define CONFIG_IPADDR 10.82.193.138 +#define CONFIG_IPADDR 192.168.1.100 #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 10.82.193.104 +#define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 From d4dd317b58c126a2a7e73f4764ecc1a7c97f876c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 10 May 2006 09:33:07 -0500 Subject: [PATCH 005/101] Remove unnecessary flash.c file. --- board/mpc8641hpcn/flash.c | 550 -------------------------------------- 1 file changed, 550 deletions(-) delete mode 100644 board/mpc8641hpcn/flash.c diff --git a/board/mpc8641hpcn/flash.c b/board/mpc8641hpcn/flash.c deleted file mode 100644 index e2f7816e1..000000000 --- a/board/mpc8641hpcn/flash.c +++ /dev/null @@ -1,550 +0,0 @@ -/* - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if !defined(CFG_NO_FLASH) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#undef DEBUG - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - - value = addr[0] & 0x00FF00FF; - -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)value); -#endif - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: -#if defined(CONFIG_MPC8641_SIM) - info->flash_id = FLASH_MAN_INTEL; - break; -#else - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ -#endif - } - - value = addr[1] & 0x00FF00FF; /* device ID */ - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case (INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - sector_offset = 0x40000; - break; /* => 2x8 MB */ - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: -#if defined(CONFIG_MPC8641_SIM) - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - sector_offset = 0x40000; - break; /* => 2x8 MB */ -#else - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ -#endif - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - asm("sync"); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x00800080) != 0x00800080) { - if(*addr & 0x00200020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - } - } - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - start = get_timer (0); - while((*addr & 0x00800080) != 0x00800080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CFG_NO_FLASH */ From 6cfea33477b04b63ed47386ed1629529484c33ba Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 10 May 2006 09:38:06 -0500 Subject: [PATCH 006/101] Remove unneeded INIT_RAM_LOCK cache twiddling. Correctly tracks r29 as global data pointer now. Signed-off-by: Haiying Wang --- board/mpc8641hpcn/mpc8641hpcn.c | 11 ----------- common/cmd_bootm.c | 4 ++-- cpu/mpc86xx/start.S | 5 +++-- lib_ppc/board.c | 2 +- 4 files changed, 6 insertions(+), 16 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index ace6d47fd..d02a7eff3 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -291,16 +291,5 @@ ft_board_setup(void *blob, bd_t *bd) } #endif -void -after_reloc(ulong dest_addr) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* now, jump to the main U-Boot board init code */ - board_init_r ((gd_t *)gd, dest_addr); - - /* NOTREACHED */ -} - diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index fdf7180a1..e5d70fa20 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -809,7 +809,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, #ifndef CONFIG_OF_FLAT_TREE -#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) +#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500) || !defined(CONFIG_MPC86xx)) unlock_ram_in_cache(); #endif @@ -827,7 +827,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ -#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) +#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500)||!defined(CONFIG_MPC86xx)) unlock_ram_in_cache(); #endif /* diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 0a447a76b..b96363151 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -955,8 +955,9 @@ in_ram: cmplw 0, r3, r4 bne 5b 6: - mr r3, r10 /* Destination Address */ - bl after_reloc + mr r3, r9 /* Init Date pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r /* not reached - end relocate_code */ /*-----------------------------------------------------------------------*/ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 126102bf9..c367b3ef9 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -676,7 +676,7 @@ void board_init_r (gd_t *id, ulong dest_addr) icache_enable (); /* it's time to enable the instruction cache */ #endif -#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) +#if defined(CFG_INIT_RAM_LOCK) && (defined(CONFIG_E500) || defined(CONFIG_MPC86xx)) unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ #endif From bf690dcb512d34c4fceec0eb1e5c0e88a9db5d54 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 15 May 2006 07:26:56 -0500 Subject: [PATCH 007/101] Update interrupt mapping. --- board/mpc8641hpcn/oftree.dts | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 8e38047e7..ef28fc31e 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -58,7 +58,7 @@ device_type = "i2c"; compatible = "fsl-i2c"; reg = <3000 100>; - interrupts = <1b 0>; + interrupts = <2b 0>; interrupt-parent = <40000>; dfsrr; }; @@ -73,28 +73,28 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = ; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = ; reg = <1>; device_type = "ethernet-phy"; }; ethernet-phy@2 { linux,phandle = <2452002>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = ; reg = <2>; device_type = "ethernet-phy"; }; ethernet-phy@3 { linux,phandle = <2452003>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = ; reg = <3>; device_type = "ethernet-phy"; }; @@ -108,7 +108,7 @@ compatible = "gianfar"; reg = <24000 1000>; address = [ 00 E0 0C 00 73 00 ]; - interrupts = ; + interrupts = <1d 3 1e 3 22 3>; interrupt-parent = <40000>; phy-handle = <2452000>; }; @@ -121,7 +121,7 @@ compatible = "gianfar"; reg = <25000 1000>; address = [ 00 E0 0C 00 73 01 ]; - interrupts = <13 3 14 3 18 3>; + interrupts = <23 3 24 3 28 3>; interrupt-parent = <40000>; phy-handle = <2452001>; }; @@ -134,7 +134,7 @@ compatible = "gianfar"; reg = <26000 1000>; address = [ 00 E0 0C 00 02 FD ]; - interrupts = ; + interrupts = <1F 3 20 3 21 3>; interrupt-parent = <40000>; phy-handle = <2452002>; }; @@ -147,7 +147,7 @@ compatible = "gianfar"; reg = <27000 1000>; address = [ 00 E0 0C 00 03 FD ]; - interrupts = <15 3 16 3 17 3>; + interrupts = <25 3 26 3 27 3>; interrupt-parent = <40000>; phy-handle = <2452003>; }; @@ -156,7 +156,7 @@ compatible = "ns16550"; reg = <4500 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <2a 3>; interrupt-parent = <40000>; }; @@ -165,7 +165,7 @@ compatible = "ns16550"; reg = <4600 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <2a 3>; interrupt-parent = <40000>; }; From f35ec68fb066cec0e36294bfe07dec2d4e8ad3a8 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 12:33:09 -0500 Subject: [PATCH 008/101] Enable 2nd CPU and I2C. --- board/mpc8641hpcn/oftree.dts | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index ef28fc31e..d4e40b8a2 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -18,7 +18,7 @@ linux,phandle = <100>; cpus { - #cpus = <1>; + #cpus = <2>; #address-cells = <1>; #size-cells = <0>; linux,phandle = <200>; @@ -31,18 +31,31 @@ d-cache-size = <8000>; // L1, 32K i-cache-size = <8000>; // L1, 32K timebase-frequency = <0>; // 33 MHz, from uboot - bus-frequency = <0>; // 166 MHz - clock-frequency = <0>; // 825 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot 32-bit; linux,phandle = <201>; linux,boot-cpu; }; + PowerPC,8641@1 { + device_type = "cpu"; + reg = <1>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <8000>; // L1, 32K + i-cache-size = <8000>; // L1, 32K + timebase-frequency = <0>; // 33 MHz, from uboot + bus-frequency = <0>; // From uboot + clock-frequency = <0>; // From uboot + 32-bit; + linux,phandle = <202>; + }; }; memory { device_type = "memory"; linux,phandle = <300>; - reg = <00000000 10000000>; // 256M at 0x0 + reg = <00000000 40000000>; // 1G at 0x0, replaced by uboot }; soc8641@f8000000 { @@ -63,6 +76,15 @@ dfsrr; }; + i2c@3100 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3100 100>; + interrupts = <2b 0>; + interrupt-parent = <40000>; + dfsrr; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; From cccce5d0581bb0ba4602799a4b5112e58d1579cb Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:14:15 -0500 Subject: [PATCH 009/101] Remove L2 Cache invalidate polling. --- cpu/mpc86xx/cache.S | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index 75186b1e4..f316b3ec1 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -28,7 +28,7 @@ * Most of this code is taken from 74xx_7xx/cache.S * and then cleaned up a bit */ - + /* * Invalidate L1 instruction cache. */ @@ -316,24 +316,30 @@ _GLOBAL(dcache_status) blr /* - * Invalidate L2 cache using L2I and polling L2IP + * Invalidate L2 cache using L2I, assume L2 is enabled */ _GLOBAL(l2cache_invalidate) - sync - oris r3, r3, L2CR_L2I@h + mfspr r3, l2cr + rlwinm. r3, r3, 0, 0, 0 + beq 1f + + mfspr r3, l2cr + rlwinm r3, r3, 0, 1, 31 + +#ifdef CONFIG_ALTIVEC + dssall +#endif sync mtspr l2cr, r3 sync +1: mfspr r3, l2cr + oris r3, r3, L2CR_L2I@h + mtspr l2cr, r3 + invl2: mfspr r3, l2cr - andi. r3, r3, L2CR_L2IP + andi. r3, r3, L2CR_L2I@h bne invl2 - /* turn off the global invalidate bit */ - mfspr r3, l2cr - rlwinm r3, r3, 0, 11, 9 - sync - mtspr l2cr, r3 - sync blr /* From 586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:22:44 -0500 Subject: [PATCH 010/101] Update 86xx address map and LAWBARs. --- board/mpc8641hpcn/init.S | 25 +++++++++++++---- include/asm-ppc/immap_86xx.h | 4 +-- include/configs/MPC8641HPCN.h | 52 +++++++++++++++++++++-------------- 3 files changed, 54 insertions(+), 27 deletions(-) diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 4d555a509..5f19fdfb6 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -36,11 +36,10 @@ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xf800_0000 0xf80f_ffff CCSRBAR 1M + * 0xf810_0000 0xf81f_ffff PIXIS 1M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * * Notes: @@ -76,9 +75,16 @@ /*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) - #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) - #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR8 0 +#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif .section .bootpg, "ax" .globl law_entry @@ -151,5 +157,14 @@ law_entry: ori r6,r6,LAWAR7@l stwu r6, 0x20(r5) + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + blr diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 6bbe072b2..9e81b4707 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -52,7 +52,7 @@ typedef struct ccsr_local_mcm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[16]; + char res20[20]; uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ char res21[4]; uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ @@ -60,7 +60,7 @@ typedef struct ccsr_local_mcm { uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ char res23[4]; uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ - char res24[720]; + char res24[716]; uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ char res25[4]; uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d4a28edf9..aaf99c150 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -136,15 +136,16 @@ /* - * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 - * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. + * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. * However, when u-boot comes up, the flash_init needs hard start addresses - * to build its info table. For user convenience, we have the flash addresses - * as fe800000 and ff800000. That way, when we do flash operations, u-boot - * knows where the flash is and the user can download u-boot code from promjet to - * fef00000 <- more intuitive than fe700000. Note that, on switching the boot - * location, fef00000 becomes fff00000. + * to build its info table. For user convenience, the flash addresses is + * fe800000 and ff800000. That way, u-boot knows where the flash is + * and the user can download u-boot code from promjet to fef00000, a + * more intuitive location than fe700000. + * + * Note that, on switching the boot location, fef00000 becomes fff00000. */ #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ #define CFG_FLASH_BASE2 0xff800000 @@ -257,14 +258,18 @@ #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 -/* I2C */ +/* + * I2C + */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -/* RapidIO MMU */ +/* + * RapidIO MMU + */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ @@ -347,19 +352,21 @@ #endif /* CONFIG_TSEC_ENET */ -/* BAT0 2G Cacheable, non-guarded +/* + * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ #define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) -#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) +#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) #define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) #define CFG_IBAT0U CFG_DBAT0U -/* BAT1 1G Cache-inhibited, guarded +/* + * BAT1 1G Cache-inhibited, guarded * 0x8000_0000 512M PCI-Express 1 Memory * 0xa000_0000 512M PCI-Express 2 Memory - ** SS - Changed it for operating from 0xd0000000 + * Changed it for operating from 0xd0000000 */ #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -367,7 +374,8 @@ #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U -/* BAT2 512M Cache-inhibited, guarded +/* + * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ @@ -376,7 +384,8 @@ #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U -/* BAT3 4M Cache-inhibited, guarded +/* + * BAT3 4M Cache-inhibited, guarded * 0xf800_0000 4M CCSR */ #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ @@ -385,10 +394,11 @@ #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U -/* BAT4 32M Cache-inhibited, guarded +/* + * BAT4 32M Cache-inhibited, guarded * 0xe200_0000 16M PCI-Express 1 I/O * 0xe300_0000 16M PCI-Express 2 I/0 - ** SS - Note that this is at 0xe0000000 + * Note that this is at 0xe0000000 */ #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -396,7 +406,8 @@ #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U -/* BAT5 128K Cacheable, non-guarded +/* + * BAT5 128K Cacheable, non-guarded * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) */ #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) @@ -404,7 +415,8 @@ #define CFG_IBAT5L CFG_DBAT5L #define CFG_IBAT5U CFG_DBAT5U -/* BAT6 32M Cache-inhibited, guarded +/* + * BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ #define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ @@ -427,7 +439,7 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ From 9a655876e5995be80f49054e2509500e871e4d3a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:26:34 -0500 Subject: [PATCH 011/101] Enable dual DDR controllers and interleaving. --- cpu/mpc86xx/spd_sdram.c | 675 ++++++++++++++++++++++++++-------- include/configs/MPC8641HPCN.h | 12 +- 2 files changed, 535 insertions(+), 152 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 9ce31d7c6..130c8fc39 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -41,6 +41,15 @@ extern int dma_xfer(void *dest, uint count, void *src); #define CFG_READ_SPD i2c_read #endif +/* + * Only one of the following three should be 1; others should be 0 + * By default the cache line interleaving is selected if + * the CONFIG_DDR_INTERLEAVE flag is defined in MPC8641HPCN.h + */ +#define CFG_PAGE_INTERLEAVING 0 +#define CFG_BANK_INTERLEAVING 0 +#define CFG_SUPER_BANK_INTERLEAVING 0 + /* * Convert picoseconds into clock cycles (rounding up if needed). */ @@ -144,10 +153,11 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) long int -spd_sdram(void) +spd_init(unsigned char i2c_address, unsigned int ddr_num, + unsigned int dimm_num, unsigned int start_addr) { volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_ddr_t *ddr; volatile ccsr_gur_t *gur = &immap->im_gur; spd_eeprom_t spd; unsigned int n_ranks; @@ -175,28 +185,41 @@ spd_sdram(void) unsigned int mode_caslat; unsigned char sdram_type; unsigned char d_init; + unsigned int law_size; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; - - unsigned int law_size; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + if (ddr_num == 1) + ddr = &immap->im_ddr1; + else + ddr = &immap->im_ddr2; /* * Read SPD information. */ - CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd)); + debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address); + memset((void *)&spd, 0, sizeof(spd)); + CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd)); /* * Check for supported memory module types. */ if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { - printf("Unable to locate DDR I or DDR II module.\n" - " Fundamental memory type is 0x%0x\n", - spd.mem_type); + debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n" + " Fundamental memory type is 0x%0x\n", + dimm_num, + ddr_num, + spd.mem_type); return 0; } + debug("\nFound memory of type 0x%02lx ", spd.mem_type); + if (spd.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + /* * These test gloss over DDR I and II differences in interpretation * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks @@ -253,11 +276,7 @@ spd_sdram(void) */ rank_density = compute_banksize(spd.mem_type, spd.row_dens); - - /* - * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg - */ - ddr1->cs0_bnds = (rank_density >> 24) - 1; + debug("Start address for this controller is 0x%08lx\n", start_addr); /* * ODT configuration recommendation from DDR Controller Chapter. @@ -268,30 +287,133 @@ spd_sdram(void) odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ } - ddr1->cs0_config = ( 1 << 31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 - | (spd.ncol_addr - 8) ); - debug("\n"); - debug("DDR: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); - debug("DDR: cs0_config = 0x%08x\n", ddr1->cs0_config); - - if (n_ranks == 2) { +#ifdef CONFIG_DDR_INTERLEAVE +#ifdef CONFIG_MPC8641HPCN + if (dimm_num != 1) { + printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num); + return 0; + } else { /* - * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg + * Since interleaved memory only uses CS0, the + * memory sticks have to be identical in size and quantity + * of ranks. That essentially gives double the size on + * one rank, i.e on CS0 for both controllers put together. + * Confirm this??? */ - ddr1->cs1_bnds = ( (rank_density >> 8) - | ((rank_density >> (24 - 1)) - 1) ); - ddr1->cs1_config = ( 1<<31 + rank_density *= 2; + + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + start_addr = 0; + ddr->cs0_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + /* + * Default interleaving mode to cache-line interleaving. + */ + ddr->cs0_config = ( 1 << 31 +#if (CFG_PAGE_INTERLEAVING == 1) + | (PAGE_INTERLEAVING) +#elif (CFG_BANK_INTERLEAVING == 1) + | (BANK_INTERLEAVING) +#elif (CFG_SUPER_BANK_INTERLEAVING == 1) + | (SUPER_BANK_INTERLEAVING) +#else + | (CACHE_LINE_INTERLEAVING) +#endif | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); - debug("DDR: cs1_bnds = 0x%08x\n", ddr1->cs1_bnds); - debug("DDR: cs1_config = 0x%08x\n", ddr1->cs1_config); - } + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + /* + * Adjustment for dual rank memory to get correct memory + * size (return value of this function). + */ + if (n_ranks == 2) { + n_ranks = 1; + rank_density /= 2; + } else { + rank_density /= 2; + } + } +#endif /* CONFIG_MPC8641HPCN */ + +#else /* CONFIG_DDR_INTERLEAVE */ + + if (dimm_num == 1) { + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs0_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + + ddr->cs0_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); + debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, + * second 256 Meg + */ + ddr->cs1_bnds = (((start_addr + rank_density) >> 8) + | (( start_addr + 2*rank_density - 1) + >> 24)); + ddr->cs1_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); + debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config); + } + + } else { + /* + * This is the 2nd DIMM slot for this controller + */ + /* + * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg + */ + ddr->cs2_bnds = (start_addr >> 8) + | (((start_addr + rank_density - 1) >> 24)); + + ddr->cs2_config = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + + debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds); + debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config); + + if (n_ranks == 2) { + /* + * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, + * second 256 Meg + */ + ddr->cs3_bnds = (((start_addr + rank_density) >> 8) + | (( start_addr + 2*rank_density - 1) + >> 24)); + ddr->cs3_config = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) + | (spd.nrow_addr - 12) << 8 + | (spd.ncol_addr - 8) ); + debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds); + debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config); + } + } +#endif /* CONFIG_DDR_INTERLEAVE */ /* * Find the largest CAS by locating the highest 1 bit @@ -447,15 +569,14 @@ spd_sdram(void) unsigned char act_pd_exit = 2; /* Empirical? */ unsigned char pre_pd_exit = 6; /* Empirical? */ - ddr1->timing_cfg_0 = (0 + ddr->timing_cfg_0 = (0 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ ); - debug("DDR: timing_cfg_0 = 0x%08x\n", ddr1->timing_cfg_0); + debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); - } else { } @@ -520,10 +641,10 @@ spd_sdram(void) /* * Sneak in some Extended Refresh Recovery. */ - ddr1->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr1->ext_refrec); + ddr->ext_refrec = (trfc_high << 16); + debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); - ddr1->timing_cfg_1 = + ddr->timing_cfg_1 = (0 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ @@ -535,7 +656,7 @@ spd_sdram(void) | ((twtr_clk & 0x07) << 0) /* WRTORD */ ); - debug("DDR: timing_cfg_1 = 0x%08x\n", ddr1->timing_cfg_1); + debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); /* @@ -612,7 +733,7 @@ spd_sdram(void) } } - ddr1->timing_cfg_2 = (0 + ddr->timing_cfg_2 = (0 | ((add_lat & 0x7) << 28) /* ADD_LAT */ | ((cpo & 0x1f) << 23) /* CPO */ | ((wr_lat & 0x7) << 19) /* WR_LAT */ @@ -622,7 +743,7 @@ spd_sdram(void) | ((four_act & 0x1f) << 0) /* FOUR_ACT */ ); - debug("DDR: timing_cfg_2 = 0x%08x\n", ddr1->timing_cfg_2); + debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); /* @@ -673,7 +794,7 @@ spd_sdram(void) } /* - * Encoded Burst Lenght of 4. + * Encoded Burst Length of 4. */ burst_len = 2; /* Fiat. */ @@ -706,7 +827,7 @@ spd_sdram(void) mode_odt_enable = 0x40; /* 150 Ohm */ } - ddr1->sdram_mode_1 = + ddr->sdram_mode_1 = (0 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ @@ -715,14 +836,14 @@ spd_sdram(void) | (burst_len << 0) /* Burst length */ ); - debug("DDR: sdram_mode = 0x%08x\n", ddr1->sdram_mode_1); + debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1); /* * Clear EMRS2 and EMRS3. */ - ddr1->sdram_mode_2 = 0; - debug("DDR: sdram_mode_2 = 0x%08x\n", ddr1->sdram_mode_2); + ddr->sdram_mode_2 = 0; + debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); /* @@ -749,12 +870,12 @@ spd_sdram(void) * Set BSTOPRE to 0x100 for page mode * If auto-charge is used, set BSTOPRE = 0 */ - ddr1->sdram_interval = + ddr->sdram_interval = (0 | (refresh_clk & 0x3fff) << 16 | 0x100 ); - debug("DDR: sdram_interval = 0x%08x\n", ddr1->sdram_interval); + debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); } /* @@ -763,11 +884,11 @@ spd_sdram(void) */ #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) if (spd.config == 0x02) { - ddr1->err_disable = 0x0000000d; - ddr1->err_sbe = 0x00ff0000; + ddr->err_disable = 0x0000000d; + ddr->err_sbe = 0x00ff0000; } - debug("DDR: err_disable = 0x%08x\n", ddr1->err_disable); - debug("DDR: err_sbe = 0x%08x\n", ddr1->err_sbe); + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); + debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); #endif asm("sync;isync"); @@ -800,8 +921,8 @@ spd_sdram(void) * Use the DDR controller to auto initialize memory. */ d_init = 1; - ddr1->sdram_data_init = CONFIG_MEM_INIT_VALUE; - debug("DDR: ddr_data_init = 0x%08x\n", ddr1->sdram_data_init); + ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init); #else /* * Memory will be initialized via DMA, or not at all. @@ -809,13 +930,13 @@ spd_sdram(void) d_init = 0; #endif - ddr1->sdram_cfg_2 = (0 + ddr->sdram_cfg_2 = (0 | (dqs_cfg << 26) /* Differential DQS */ | (odt_cfg << 21) /* ODT */ | (d_init << 4) /* D_INIT auto init DDR */ ); - debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr1->sdram_cfg_2); + debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2); #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL @@ -835,121 +956,373 @@ spd_sdram(void) clk_adjust = 0x7; } - ddr1->sdram_clk_cntl = (0 + ddr->sdram_clk_cntl = (0 | 0x80000000 | (clk_adjust << 23) ); - debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr1->sdram_clk_cntl); + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); } #endif - /* - * Figure out the settings for the sdram_cfg register. - * Build up the entire register in 'sdram_cfg' before writing - * since the write into the register will actually enable the - * memory controller; all settings must be done before enabling. - * - * sdram_cfg[0] = 1 (ddr sdram logic enable) - * sdram_cfg[1] = 1 (self-refresh-enable) - * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) - * 010 DDR 1 SDRAM - * 011 DDR 2 SDRAM - */ - sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; - sdram_cfg_1 = (0 - | (1 << 31) /* Enable */ - | (1 << 30) /* Self refresh */ - | (sdram_type << 24) /* SDRAM type */ - ); - - /* - * sdram_cfg[3] = RD_EN - registered DIMM enable - * A value of 0x26 indicates micron registered DIMMS (micron.com) - */ - if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) { - sdram_cfg_1 |= 0x10000000; /* RD_EN */ - } - -#if defined(CONFIG_DDR_ECC) - /* - * If the user wanted ECC (enabled via sdram_cfg[2]) - */ - if (spd.config == 0x02) { - sdram_cfg_1 |= 0x20000000; /* ECC_EN */ - } -#endif - - /* - * REV1 uses 1T timing. - * REV2 may use 1T or 2T as configured by the user. - */ - { - uint pvr = get_pvr(); - - if (pvr != PVR_85xx_REV1) { -#if defined(CONFIG_DDR_2T_TIMING) - /* - * Enable 2T timing by setting sdram_cfg[16]. - */ - sdram_cfg_1 |= 0x8000; /* 2T_EN */ -#endif - } - } - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - - /* - * Go! - */ - ddr1->sdram_cfg_1 = sdram_cfg_1; - - asm("sync;isync"); - udelay(500); - - debug("DDR: sdram_cfg = 0x%08x\n", ddr1->sdram_cfg_1); - - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - debug("DDR: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr1->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); - } - debug("DDR: memory initialized\n"); -#endif - /* * Figure out memory size in Megabytes. */ + debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density); memsize = n_ranks * rank_density / 0x100000; + return memsize; +} - /* - * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. - */ - law_size = 19 + __ilog2(memsize); +unsigned int enable_ddr(unsigned int ddr_num) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + spd_eeprom_t spd1,spd2; + volatile ccsr_ddr_t *ddr; + unsigned sdram_cfg_1; + unsigned char sdram_type, mem_type, config, mod_attr; + unsigned char d_init; + unsigned int no_dimm1=0, no_dimm2=0; + + /* Set up pointer to enable the current ddr controller */ + if (ddr_num == 1) + ddr = &immap->im_ddr1; + else + ddr = &immap->im_ddr2; /* - * Set up LAWBAR for all of DDR. + * Read both dimm slots and decide whether + * or not to enable this controller. */ - mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - mcm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR - | (LAWAR_SIZE & law_size)); - debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); - debug("DDR: LARAR1=0x%08x\n", mcm->lawar1); + memset((void *)&spd1,0,sizeof(spd1)); + memset((void *)&spd2,0,sizeof(spd2)); - return memsize * 1024 * 1024; + if (ddr_num == 1) { + CFG_READ_SPD(SPD_EEPROM_ADDRESS1, + 0, 1, (uchar *) &spd1, sizeof(spd1)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS2, + 0, 1, (uchar *) &spd2, sizeof(spd2)); + } else { + CFG_READ_SPD(SPD_EEPROM_ADDRESS3, + 0, 1, (uchar *) &spd1, sizeof(spd1)); + CFG_READ_SPD(SPD_EEPROM_ADDRESS4, + 0, 1, (uchar *) &spd2, sizeof(spd2)); + } + + /* + * Check for supported memory module types. + */ + if (spd1.mem_type != SPD_MEMTYPE_DDR + && spd1.mem_type != SPD_MEMTYPE_DDR2) { + no_dimm1 = 1; + } else { + debug("\nFound memory of type 0x%02lx ",spd1.mem_type ); + if (spd1.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + } + + if (spd2.mem_type != SPD_MEMTYPE_DDR && + spd2.mem_type != SPD_MEMTYPE_DDR2) { + no_dimm2 = 1; + } else { + debug("\nFound memory of type 0x%02lx ",spd2.mem_type ); + if (spd2.mem_type == SPD_MEMTYPE_DDR) + debug("DDR I\n"); + else + debug("DDR II\n"); + } + +#ifdef CONFIG_DDR_INTERLEAVE + if (no_dimm1) { + printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n"); + return 0; + } +#endif + + /* + * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn + */ + if (no_dimm1 && no_dimm2) { + printf("No memory modules found for DDR controller %d!!\n", ddr_num); + return 0; + } else { + mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type; + + /* + * Figure out the settings for the sdram_cfg register. + * Build up the entire register in 'sdram_cfg' before + * writing since the write into the register will + * actually enable the memory controller; all settings + * must be done before enabling. + * + * sdram_cfg[0] = 1 (ddr sdram logic enable) + * sdram_cfg[1] = 1 (self-refresh-enable) + * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) + * 010 DDR 1 SDRAM + * 011 DDR 2 SDRAM + */ + sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; + sdram_cfg_1 = (0 + | (1 << 31) /* Enable */ + | (1 << 30) /* Self refresh */ + | (sdram_type << 24) /* SDRAM type */ + ); + + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable + * A value of 0x26 indicates micron registered + * DIMMS (micron.com) + */ + mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr; + if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) { + sdram_cfg_1 |= 0x10000000; /* RD_EN */ + } + +#if defined(CONFIG_DDR_ECC) + + config = no_dimm2 ? spd1.config : spd2.config; + + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ + if (config == 0x02) { + sdram_cfg_1 |= 0x20000000; /* ECC_EN */ + } +#endif + + /* + * REV1 uses 1T timing. + * REV2 may use 1T or 2T as configured by the user. + */ + { + uint pvr = get_pvr(); + + if (pvr != PVR_85xx_REV1) { +#if defined(CONFIG_DDR_2T_TIMING) + /* + * Enable 2T timing by setting sdram_cfg[16]. + */ + sdram_cfg_1 |= 0x8000; /* 2T_EN */ +#endif + } + } + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + + /* + * Go! + */ + ddr->sdram_cfg_1 = sdram_cfg_1; + + asm volatile("sync;isync"); + udelay(500); + + debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1); + + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR: memory initializing\n"); + + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } + debug("DDR: memory initialized\n\n"); +#endif + + debug("Enabled DDR Controller %d\n", ddr_num); + return 1; + } } + +long int +spd_sdram(void) +{ + int memsize_ddr1_dimm1 = 0; + int memsize_ddr1_dimm2 = 0; + int memsize_ddr2_dimm1 = 0; + int memsize_ddr2_dimm2 = 0; + int memsize_total = 0; + int memsize_ddr1 = 0; + int memsize_ddr2 = 0; + unsigned int ddr1_enabled = 0; + unsigned int ddr2_enabled = 0; + unsigned int law_size_ddr1; + unsigned int law_size_ddr2; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; + volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; + volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + +#ifdef CONFIG_DDR_INTERLEAVE + unsigned int law_size_interleaved; + + memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, + 1, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm1; + + memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, + 2, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm1; + + if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) { + if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1) + memsize_total -= memsize_ddr1_dimm1; + else + memsize_total -= memsize_ddr2_dimm1; + debug("Total memory available for interleaving 0x%08lx\n", + memsize_total * 1024 * 1024); + debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n"); + ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; + ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; + debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); + debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds); + } + + ddr1_enabled = enable_ddr(1); + ddr2_enabled = enable_ddr(2); + + /* + * Both controllers need to be enabled for interleaving. + */ + if (ddr1_enabled && ddr2_enabled) { + law_size_interleaved = 19 + __ilog2(memsize_total); + + /* + * Set up LAWBAR for DDR 1 space. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR_INTERLEAVED + | (LAWAR_SIZE & law_size_interleaved)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); + debug("Interleaved memory size is 0x%08lx\n", memsize_total); + +#ifdef CONFIG_DDR_INTERLEAVE +#if (CFG_PAGE_INTERLEAVING == 1) + printf("Page "); +#elif (CFG_BANK_INTERLEAVING == 1) + printf("Bank "); +#elif (CFG_SUPER_BANK_INTERLEAVING == 1) + printf("Super-bank "); +#else + printf("Cache-line "); +#endif +#endif + printf("Interleaved"); + return memsize_total * 1024 * 1024; + } else { + printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n"); + return 0; + } + +#else + /* + * Call spd_sdram() routine to init ddr1 - pass I2c address, + * controller number, dimm number, and starting address. + */ + memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, + 1, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm1; + + memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, + 1, 2, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr1_dimm2; + + /* + * Enable the DDR controller - pass ddr controller number. + */ + ddr1_enabled = enable_ddr(1); + + /* Keep track of memory to be addressed by DDR1 */ + memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2; + + /* + * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. + */ + if (ddr1_enabled) { + law_size_ddr1 = 19 + __ilog2(memsize_ddr1); + + /* + * Set up LAWBAR for DDR 1 space. + */ + mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + mcm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR1 + | (LAWAR_SIZE & law_size_ddr1)); + debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); + debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); + } + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, + 2, 1, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm1; + + memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4, + 2, 2, + (unsigned int)memsize_total * 1024*1024); + memsize_total += memsize_ddr2_dimm2; + + ddr2_enabled = enable_ddr(2); + + /* Keep track of memory to be addressed by DDR2 */ + memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2; + + if (ddr2_enabled) { + law_size_ddr2 = 19 + __ilog2(memsize_ddr2); + + /* + * Set up LAWBAR for DDR 2 space. + */ + if (ddr1_enabled) + mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) + & 0xfffff); + else + mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + + mcm->lawar8 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR2 + | (LAWAR_SIZE & law_size_ddr2)); + debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); + debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); + } +#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ + + debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", + memsize_ddr1, memsize_ddr2); + + /* + * If neither DDR controller is enabled return 0. + */ + if (!ddr1_enabled && !ddr2_enabled) + return 0; + else { + printf("Non-interleaved"); + return memsize_total * 1024 * 1024; + } + +#endif /* CONFIG_DDR_INTERLEAVE */ +} + + #endif /* CONFIG_SPD_EEPROM */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aaf99c150..2a197be29 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -57,6 +57,13 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +/* #define CONFIG_DDR_INTERLEAVE 1 */ +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + #define CONFIG_ALTIVEC 1 @@ -99,7 +106,10 @@ /* * Determine DDR configuration from I2C interface. */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ #else /* From 14e37081ff3cac7ebe6e93836523429853b6b292 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 19 May 2006 13:28:39 -0500 Subject: [PATCH 012/101] Change arbitration to round-robin for SMP linux. --- cpu/mpc86xx/start.S | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index b96363151..07e75572b 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -207,11 +207,7 @@ boot_warm: /* init the L2 cache */ addis r3, r0, L2_INIT@h ori r3, r3, L2_INIT@l - sync mtspr l2cr, r3 -#ifdef CONFIG_ALTIVEC - dssall -#endif /* invalidate the L2 cache */ bl l2cache_invalidate sync @@ -245,6 +241,13 @@ in_flash: bl setup_ccsrbar #endif + /* Fix for SMP linux - Changing arbitration to round-robin */ + lis r3, CFG_CCSRBAR@h + ori r3, r3, 0x1000 + xor r4, r4, r4 + li r4, 0x1000 + stw r4, 0(r3) + /* setup the law entries */ bl law_entry sync @@ -280,9 +283,9 @@ in_flash: /* make sure timer enabled in guts register too */ lis r3, CFG_CCSRBAR@h oris r3,r3, 0xE - ori r3,r3,0x0070 /*Jason from 3*/ + ori r3,r3,0x0070 lwz r4, 0(r3) - lis r5,0xFFFC /*Jason from 0xffff*/ + lis r5,0xFFFC ori r5,r5,0x5FFF and r4,r4,r5 stw r4,0(r3) From 3033ebb20fd7c372c7bca3c9955a4692bb2240b7 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 26 May 2006 10:01:16 -0500 Subject: [PATCH 013/101] Allow args on reset command. Signed-off-by: Jon Loeliger --- common/cmd_boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_boot.c b/common/cmd_boot.c index e68f16f9d..182e2ab98 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -83,7 +83,7 @@ U_BOOT_CMD( extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( - reset, 1, 0, do_reset, + reset, CFG_MAXARGS, 1, do_reset, "reset - Perform RESET of the CPU\n", NULL ); From ed45d6c930b5939718a87ee12e25cf9a05978d4a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 26 May 2006 10:13:04 -0500 Subject: [PATCH 014/101] Added pci@8000 block. Updated ethernet interrupt mappings (moved up 48). Cleaned up a few comments. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/oftree.dts | 130 ++++++++++++++++++++++++++++++++--- 1 file changed, 119 insertions(+), 11 deletions(-) diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index d4e40b8a2..26ce6618a 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -30,7 +30,7 @@ i-cache-line-size = <20>; // 32 bytes d-cache-size = <8000>; // L1, 32K i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot + timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot 32-bit; @@ -44,7 +44,7 @@ i-cache-line-size = <20>; // 32 bytes d-cache-size = <8000>; // L1, 32K i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot + timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot 32-bit; @@ -55,7 +55,7 @@ memory { device_type = "memory"; linux,phandle = <300>; - reg = <00000000 40000000>; // 1G at 0x0, replaced by uboot + reg = <00000000 40000000>; // 1G at 0x0 }; soc8641@f8000000 { @@ -95,28 +95,28 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <1>; device_type = "ethernet-phy"; }; ethernet-phy@2 { linux,phandle = <2452002>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <2>; device_type = "ethernet-phy"; }; ethernet-phy@3 { linux,phandle = <2452003>; interrupt-parent = <40000>; - interrupts = ; + interrupts = <3a 0>; reg = <3>; device_type = "ethernet-phy"; }; @@ -176,8 +176,8 @@ serial@4500 { device_type = "serial"; compatible = "ns16550"; - reg = <4500 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + reg = <4500 100>; + clock-frequency = <0>; interrupts = <2a 3>; interrupt-parent = <40000>; }; @@ -185,12 +185,120 @@ serial@4600 { device_type = "serial"; compatible = "ns16550"; - reg = <4600 100>; // reg base, size - clock-frequency = <0>; // should we fill in in uboot? + reg = <4600 100>; + clock-frequency = <0>; interrupts = <2a 3>; interrupt-parent = <40000>; }; + pci@8000 { + compatible = "86xx"; + device_type = "pci"; + linux,phandle = <8000>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + bus-range = <0 fe>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <1fca055>; + interrupt-parent = <40000>; + interrupts = <8 0>; + interrupt-map-mask = ; + interrupt-map = < + /* IDSEL 0x11 */ + 8800 0 0 1 40000 3 0 + 8800 0 0 2 40000 4 0 + 8800 0 0 3 40000 5 0 + 8800 0 0 4 40000 6 0 + + /* IDSEL 0x12 */ + 9000 0 0 1 40000 4 0 + 9000 0 0 2 40000 5 0 + 9000 0 0 3 40000 6 0 + 9000 0 0 4 40000 3 0 + + /* IDSEL 0x13 */ + 9800 0 0 1 40000 5 0 + 9800 0 0 2 40000 6 0 + 9800 0 0 3 40000 3 0 + 9800 0 0 4 40000 4 0 + + /* IDSEL 0x14 */ + a000 0 0 1 40000 6 0 + a000 0 0 2 40000 3 0 + a000 0 0 3 40000 4 0 + a000 0 0 4 40000 5 0 + + /* IDSEL 0x15 */ + a800 0 0 1 40000 0 0 + a800 0 0 2 40000 0 0 + a800 0 0 3 40000 0 0 + a800 0 0 4 40000 0 0 + + /* IDSEL 0x16 */ + b000 0 0 1 40000 0 0 + b000 0 0 2 40000 0 0 + b000 0 0 3 40000 0 0 + b000 0 0 4 40000 0 0 + + /* IDSEL 0x17 */ + b800 0 0 1 40000 0 0 + b800 0 0 2 40000 0 0 + b800 0 0 3 40000 0 0 + b800 0 0 4 40000 0 0 + + /* IDSEL 0x18 */ + c000 0 0 1 40000 0 0 + c000 0 0 2 40000 0 0 + c000 0 0 3 40000 0 0 + c000 0 0 4 40000 0 0 + + /* IDSEL 0x19 */ + c800 0 0 1 40000 0 0 + c800 0 0 2 40000 0 0 + c800 0 0 3 40000 0 0 + c800 0 0 4 40000 0 0 + + /* IDSEL 0x1a */ + d000 0 0 1 40000 0 0 + d000 0 0 2 40000 0 0 + d000 0 0 3 40000 0 0 + d000 0 0 4 40000 0 0 + + + /* IDSEL 0x1b */ + d800 0 0 1 40000 0 0 + d800 0 0 2 40000 0 0 + d800 0 0 3 40000 0 0 + d800 0 0 4 40000 0 0 + + /* IDSEL 0x1c */ + e000 0 0 1 40000 0 0 + e000 0 0 2 40000 0 0 + e000 0 0 3 40000 0 0 + e000 0 0 4 40000 0 0 + + /* IDSEL 0x1d */ + e800 0 0 1 40000 0 0 + e800 0 0 2 40000 0 0 + e800 0 0 3 40000 0 0 + e800 0 0 4 40000 0 0 + + /* IDSEL 0x1e */ + f000 0 0 1 40000 0 0 + f000 0 0 2 40000 0 0 + f000 0 0 3 40000 0 0 + f000 0 0 4 40000 0 0 + + /* IDSEL 0x1f */ + f800 0 0 1 40000 6 0 + f800 0 0 2 40000 6 0 + f800 0 0 3 40000 6 0 + f800 0 0 4 40000 6 0 + >; + }; pic@40000 { linux,phandle = <40000>; clock-frequency = <0>; From d11fec5015334deb2010e36ce00bb118cc5429a5 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 26 May 2006 10:24:48 -0500 Subject: [PATCH 015/101] Add first draft of the MPC8641HPCN doc/README. Signed-off-by: Jon Loeliger --- doc/README.mpc8641hpcn | 123 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 doc/README.mpc8641hpcn diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn new file mode 100644 index 000000000..907a911ed --- /dev/null +++ b/doc/README.mpc8641hpcn @@ -0,0 +1,123 @@ +Freescale MPC8641HPCN board +=========================== + +Created 05/24/2006 Haiying Wang +------------------------------- + +1. Building U-Boot +------------------ +The 86xx HPCN code base is known to compile using: + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + + $ make MPC8641HPCN_config + Configuring for MPC8641HPCN board... + + $ make + + +2. Switch and Jumper Setting +---------------------------- +Jumpers: + J14 Pins 1-2 (near plcc32 socket) + +Switches: + SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1 + 01100 :: CORE = 2.5:1 + 10000 :: CORE = 3:1 + 11100 :: CORE = 3.5:1 + 10100 :: CORE = 4:1 + 01110 :: CORE = 4.5:1 + SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz + 001 :: SYSCLK = 40MHz + + SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X + 0100 :: 4X + 0110 :: 6X + 1000 :: 8X + 1010 :: 10X + 1100 :: 12X + 1110 :: 14X + 0000 :: 16X + SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus + + SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V + 0100000 :: VCORE = 1.11V + SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V + 1 :: VCC_PLAT = 1.0V + + SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root + SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq + SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX + + SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash + 0 :: boot from PromJet + SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower + halves (virtual banks) + 0 :: normal + SW5(3) = 0 CFG_FLASHWP = 0 :: not protected + SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4 + 1:1 for PD6 + SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined + SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined + + SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff + SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation + SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ + SW6(6) = 1 CFG_SERROM_ADDR= 1 :: + SW6(7) = 1 CFG_MEMDEBUG = 1 :: + SW6(8) = 1 CFG_DDRDEBUG = 1 :: + + SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49 + SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled + SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode + SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz + SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode + SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled + SW8(7) = 1 ACPWR = 1 :: non-battery + SW8(8) = 0 CFG_IDWP = 0 :: write enable + + +3. Flash U-Boot +--------------- +The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves. +It is possible to use either half to boot using u-boot. Switch 5 bit 2 +is used for this purpose. + +0xFF800000 to 0xFFBFFFFF - 4MB +0xFFC00000 to 0xFFFFFFFF - 4MB +When this bit is 0, U-Boot is at 0xFFF00000. +When this bit is 1, U-Boot is at 0xFFB00000. + +Use the above mentioned flash commands to program the other half, and +use switch 5, bit 2 to alternate between the halves. Note: The booting +version of U-Boot will always be at 0xFFF00000. + +To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF): + + tftp 1000000 u-boot.bin + protect off all + erase fff00000 ffffffff + cp.b 1000000 fff00100 80000 + +To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): + + tftp 1000000 u-boot.bin + erase ffb00000 ffbfffff + cp.b 1000000 ffb00100 80000 + + +4. Memory Map +------------- + + Memory Range Device Size + ------------ ------ ---- + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M + 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M + 0xf800_0000 0xf80f_ffff CCSR 1M + 0xf810_0000 0xf81f_ffff PIXIS 1M + 0xf840_0000 0xf840_3fff Stack space 32K + 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 512M + 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 512M + 0xfe00_0000 0xfeff_ffff Flash(alternate)16M + 0xff00_0000 0xffff_ffff Flash(boot bank)16M From 70205e5a6ddc8528b11db9eb4d3fa0209d9fce2a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 30 May 2006 08:51:19 -0500 Subject: [PATCH 016/101] Fix two SDRAM setup bugs. Fix ECC setup bug. Enable 1T/2T based on number of DIMMs present. Signed-off-by: Haiying Wang --- cpu/mpc86xx/spd_sdram.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 130c8fc39..f30bbbd7e 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -1088,24 +1088,24 @@ unsigned int enable_ddr(unsigned int ddr_num) * If the user wanted ECC (enabled via sdram_cfg[2]) */ if (config == 0x02) { + ddr->err_disable = 0x00000000; + asm("sync;isync;"); + ddr->err_sbe = 0x00ff0000; + ddr->err_int_en = 0x0000000d; sdram_cfg_1 |= 0x20000000; /* ECC_EN */ } #endif /* - * REV1 uses 1T timing. - * REV2 may use 1T or 2T as configured by the user. + * Set 1T or 2T timing based on 1 or 2 modules */ { - uint pvr = get_pvr(); - - if (pvr != PVR_85xx_REV1) { -#if defined(CONFIG_DDR_2T_TIMING) + if (!(no_dimm1 || no_dimm2)) { /* + * 2T timing,because both DIMMS are present. * Enable 2T timing by setting sdram_cfg[16]. */ sdram_cfg_1 |= 0x8000; /* 2T_EN */ -#endif } } From 38cee12dcfcc257371c901c7e13e58ecab0a35d8 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 30 May 2006 09:10:32 -0500 Subject: [PATCH 017/101] Improve "reset" command's interaction with watchdog. "reset altbank" will reset another bank WITHOUT watch dog timer enabled "reset altbank wd" will reset another bank WITH watch dog enabled "diswd" will disable watch dog after u-boot boots up successfully Signed-off-by: Haiying Wang --- cpu/mpc86xx/cpu.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 36da7774e..5c6c2ee40 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -169,7 +169,7 @@ soft_restart(unsigned long addr) int set_px_sysclk(ulong sysclk) { - u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux,tmp; + u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; /* Per table 27, page 58 of MPC8641HPCN spec*/ switch(sysclk) @@ -354,6 +354,24 @@ void set_px_go_with_watchdog(void) out8(PIXIS_BASE+PIXIS_VCTL,tmp); } +int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 tmp; + tmp = in8(PIXIS_BASE+PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE+PIXIS_VCTL,tmp); + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */ + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + return 0; +} + +U_BOOT_CMD( + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL +); + /* This function takes the non-integral cpu:mpx pll ratio * and converts it to an integer that can be used to assign * FPGA register values. @@ -509,18 +527,27 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) goto my_usage; while(1); /* Not reached */ - } else { - /* Reset from next bank without changing frequencies */ + } else if(argv[2][1] == 'd'){ + /* Reset from next bank without changing frequencies but with watchdog timer enabled */ read_from_px_regs(0); read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); set_altbank(); read_from_px_regs_altbank(1); printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); set_px_go_with_watchdog(); while(1); /* Not reached */ + } else { + /* Reset from next bank without changing frequency and without watchdog timer enabled */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Resetting board to boot from the other bank....\n"); + set_px_go(); } default: From 126aa70f10ba3d20e0a6f4d32328250513b77770 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 30 May 2006 17:47:00 -0500 Subject: [PATCH 018/101] Move mpc86xx PIXIS code to board directory First cut at moving the PIXIS platform code out of the 86xx cpu directory and into board/mpc8641hpcn where it belongs. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/Makefile | 2 +- board/mpc8641hpcn/pixis.c | 324 +++++++++++++++++++++++++++++++++++++ board/mpc8641hpcn/pixis.h | 33 ++++ cpu/mpc86xx/cpu.c | 308 ++--------------------------------- 4 files changed, 373 insertions(+), 294 deletions(-) create mode 100644 board/mpc8641hpcn/pixis.c create mode 100644 board/mpc8641hpcn/pixis.h diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index d6037c1c4..261373040 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o oftree.o +OBJS := $(BOARD).o pixis.o oftree.o SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c new file mode 100644 index 000000000..f226b3e8d --- /dev/null +++ b/board/mpc8641hpcn/pixis.c @@ -0,0 +1,324 @@ +/* + * Copyright 2006 Freescale Semiconductor + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "pixis.h" + + +/* + * Per table 27, page 58 of MPC8641HPCN spec. + */ +int set_px_sysclk(ulong sysclk) +{ + u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; + + switch (sysclk) { + case 33: + sysclk_s = 0x04; + sysclk_r = 0x04; + sysclk_v = 0x07; + sysclk_aux = 0x00; + break; + case 40: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x20; + sysclk_aux = 0x01; + break; + case 50: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x2A; + sysclk_aux = 0x02; + break; + case 66: + sysclk_s = 0x01; + sysclk_r = 0x04; + sysclk_v = 0x04; + sysclk_aux = 0x03; + break; + case 83: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x04; + break; + case 100: + sysclk_s = 0x01; + sysclk_r = 0x1F; + sysclk_v = 0x5C; + sysclk_aux = 0x05; + break; + case 134: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x3B; + sysclk_aux = 0x06; + break; + case 166: + sysclk_s = 0x06; + sysclk_r = 0x1F; + sysclk_v = 0x4B; + sysclk_aux = 0x07; + break; + default: + printf("Unsupported SYSCLK frequency.\n"); + return 0; + } + + vclkh = (sysclk_s << 5) | sysclk_r ; + vclkl = sysclk_v; + + out8(PIXIS_BASE + PIXIS_VCLKH, vclkh); + out8(PIXIS_BASE + PIXIS_VCLKL, vclkl); + + out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux); + + return 1; +} + + +int set_px_mpxpll(ulong mpxpll) +{ + u8 tmp; + u8 val; + + switch (mpxpll) { + case 2: + case 4: + case 6: + case 8: + case 10: + case 12: + case 14: + case 16: + val = (u8)mpxpll; + break; + default: + printf("Unsupported MPXPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE + PIXIS_VSPEED1); + tmp = (tmp & 0xF0) | (val & 0x0F); + out8(PIXIS_BASE + PIXIS_VSPEED1, tmp); + + return 1; +} + + +int set_px_corepll(ulong corepll) +{ + u8 tmp; + u8 val; + + switch ((int)corepll) { + case 20: + val = 0x08; + break; + case 25: + val = 0x0C; + break; + case 30: + val = 0x10; + break; + case 35: + val = 0x1C; + break; + case 40: + val = 0x14; + break; + case 45: + val = 0x0E; + break; + default: + printf("Unsupported COREPLL ratio.\n"); + return 0; + } + + tmp = in8(PIXIS_BASE + PIXIS_VSPEED0); + tmp = (tmp & 0xE0) | (val & 0x1F); + out8(PIXIS_BASE + PIXIS_VSPEED0, tmp); + + return 1; +} + + +void read_from_px_regs(int set) +{ + u8 mask = 0x1C; + u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0); + + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp); +} + + +void read_from_px_regs_altbank(int set) +{ + u8 mask = 0x04; + u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1); + + if (set) + tmp = tmp | mask; + else + tmp = tmp & ~mask; + out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp); +} + + +void set_altbank(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VBOOT); + tmp ^= 0x40; + + out8(PIXIS_BASE + PIXIS_VBOOT, tmp); +} + + +void set_px_go(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp | 0x01; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); +} + + +void set_px_go_with_watchdog(void) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp | 0x09; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); +} + + +int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 tmp; + + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + /* setting VCTL[WDEN] to 0 to disable watch dog */ + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp &= ~ 0x08; + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + + return 0; +} + + +U_BOOT_CMD( + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL +); + + +/* + * This function takes the non-integral cpu:mpx pll ratio + * and converts it to an integer that can be used to assign + * FPGA register values. + * input: strptr i.e. argv[2] + */ + +ulong strfractoint(uchar *strptr) +{ + int i, j, retval; + int mulconst; + int intarr_len = 0, decarr_len = 0, no_dec = 0; + ulong intval = 0, decval = 0; + uchar intarr[3], decarr[3]; + + /* Assign the integer part to intarr[] + * If there is no decimal point i.e. + * if the ratio is an integral value + * simply create the intarr. + */ + i = 0; + while (strptr[i] != 46) { + if (strptr[i] == 0) { + no_dec = 1; + break; + } + intarr[i] = strptr[i]; + i++; + } + + /* Assign length of integer part to intarr_len. */ + intarr_len = i; + intarr[i] = '\0'; + + if (no_dec) { + /* Currently needed only for single digit corepll ratios */ + mulconst=10; + decval = 0; + } else { + j = 0; + i++; /* Skipping the decimal point */ + while ((strptr[i] > 47) && (strptr[i] < 58)) { + decarr[j] = strptr[i]; + i++; + j++; + } + + decarr_len = j; + decarr[j] = '\0'; + + mulconst = 1; + for (i = 0; i < decarr_len; i++) + mulconst *= 10; + decval = simple_strtoul(decarr, NULL, 10); + } + + intval = simple_strtoul(intarr, NULL, 10); + intval = intval * mulconst; + + retval = intval + decval; + + return retval; +} diff --git a/board/mpc8641hpcn/pixis.h b/board/mpc8641hpcn/pixis.h new file mode 100644 index 000000000..cd9a45db8 --- /dev/null +++ b/board/mpc8641hpcn/pixis.h @@ -0,0 +1,33 @@ +/* + * Copyright 2006 Freescale Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +extern int set_px_sysclk(ulong sysclk); +extern int set_px_mpxpll(ulong mpxpll); +extern int set_px_corepll(ulong corepll); +extern void read_from_px_regs(int set); +extern void read_from_px_regs_altbank(int set); +extern void set_altbank(void); +extern void set_px_go(void); +extern void set_px_go_with_watchdog(void); +extern int disable_watchdog(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]); +extern ulong strfractoint(uchar *strptr); diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 5c6c2ee40..e21b05126 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -32,7 +32,7 @@ #include #endif -extern unsigned long get_board_sys_clk(ulong dummy); +#include "../board/mpc8641hpcn/pixis.h" static __inline__ unsigned long get_dbat3u (void) @@ -131,10 +131,10 @@ int checkcpu (void) printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } - printf(" L2: "); - if (get_l2cr() & 0x80000000) + printf(" L2: "); + if (get_l2cr() & 0x80000000) printf("Enabled\n"); - else + else printf("Disabled\n"); return 0; @@ -158,298 +158,21 @@ soft_restart(unsigned long addr) __asm__ __volatile__ ("rfi"); #else /* CONFIG_MPC8641HPCN */ - out8(PIXIS_BASE+PIXIS_RST,0); + out8(PIXIS_BASE+PIXIS_RST,0); #endif /* !CONFIG_MPC8641HPCN */ while(1); /* not reached */ } - -#ifdef CONFIG_MPC8641HPCN - -int set_px_sysclk(ulong sysclk) -{ - u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; - - /* Per table 27, page 58 of MPC8641HPCN spec*/ - switch(sysclk) - { - case 33: - sysclk_s = 0x04; - sysclk_r = 0x04; - sysclk_v = 0x07; - sysclk_aux = 0x00; - break; - case 40: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x20; - sysclk_aux = 0x01; - break; - case 50: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x2A; - sysclk_aux = 0x02; - break; - case 66: - sysclk_s = 0x01; - sysclk_r = 0x04; - sysclk_v = 0x04; - sysclk_aux = 0x03; - break; - case 83: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x04; - break; - case 100: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x5C; - sysclk_aux = 0x05; - break; - case 134: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x3B; - sysclk_aux = 0x06; - break; - case 166: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x07; - break; - default: - printf("Unsupported SYSCLK frequency.\n"); - return 0; - } - - vclkh = (sysclk_s << 5) | sysclk_r ; - vclkl = sysclk_v; - out8(PIXIS_BASE+PIXIS_VCLKH,vclkh); - out8(PIXIS_BASE+PIXIS_VCLKL,vclkl); - - out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux); - - return 1; -} - -int set_px_mpxpll(ulong mpxpll) -{ - u8 tmp; - u8 val; - switch(mpxpll) - { - case 2: - case 4: - case 6: - case 8: - case 10: - case 12: - case 14: - case 16: - val = (u8)mpxpll; - break; - default: - printf("Unsupported MPXPLL ratio.\n"); - return 0; - } - - tmp = in8(PIXIS_BASE+PIXIS_VSPEED1); - tmp = (tmp & 0xF0) | (val & 0x0F); - out8(PIXIS_BASE+PIXIS_VSPEED1,tmp); - - return 1; -} - -int set_px_corepll(ulong corepll) -{ - u8 tmp; - u8 val; - - switch ((int)corepll) { - case 20: - val = 0x08; - break; - case 25: - val = 0x0C; - break; - case 30: - val = 0x10; - break; - case 35: - val = 0x1C; - break; - case 40: - val = 0x14; - break; - case 45: - val = 0x0E; - break; - default: - printf("Unsupported COREPLL ratio.\n"); - return 0; - } - - tmp = in8(PIXIS_BASE+PIXIS_VSPEED0); - tmp = (tmp & 0xE0) | (val & 0x1F); - out8(PIXIS_BASE+PIXIS_VSPEED0,tmp); - - return 1; -} - -void read_from_px_regs(int set) -{ - u8 tmp, mask = 0x1C; - tmp = in8(PIXIS_BASE+PIXIS_VCFGEN0); - if (set) - tmp = tmp | mask; - else - tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); -} - -void read_from_px_regs_altbank(int set) -{ - u8 tmp, mask = 0x04; - tmp = in8(PIXIS_BASE+PIXIS_VCFGEN1); - if (set) - tmp = tmp | mask; - else - tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); -} - -void set_altbank(void) -{ - u8 tmp; - tmp = in8(PIXIS_BASE+PIXIS_VBOOT); - tmp ^= 0x40; - out8(PIXIS_BASE+PIXIS_VBOOT,tmp); - } - - -void set_px_go(void) -{ - u8 tmp; - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp & 0x1E; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp | 0x01; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); -} - -void set_px_go_with_watchdog(void) -{ - u8 tmp; - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp & 0x1E; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp | 0x09; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); -} - -int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - u8 tmp; - tmp = in8(PIXIS_BASE+PIXIS_VCTL); - tmp = tmp & 0x1E; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); - tmp = in8(PIXIS_BASE + PIXIS_VCTL); - tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */ - out8(PIXIS_BASE + PIXIS_VCTL, tmp); - return 0; -} - -U_BOOT_CMD( - diswd, 1, 0, disable_watchdog, - "diswd - Disable watchdog timer \n", - NULL -); - -/* This function takes the non-integral cpu:mpx pll ratio - * and converts it to an integer that can be used to assign - * FPGA register values. - * input: strptr i.e. argv[2] -*/ - -ulong strfractoint(uchar *strptr) -{ - int i,j,retval,intarr_len=0, decarr_len=0, mulconst, no_dec=0; - ulong intval =0, decval=0; - uchar intarr[3], decarr[3]; - - /* Assign the integer part to intarr[] - * If there is no decimal point i.e. - * if the ratio is an integral value - * simply create the intarr. - */ - i=0; - while(strptr[i] != 46) - { - if(strptr[i] == 0) - { - no_dec = 1; - break; /* Break from loop once the end of string is reached */ - } - - intarr[i] = strptr[i]; - i++; - } - - intarr_len = i; /* Assign length of integer part to intarr_len*/ - intarr[i] = '\0'; /* */ - - if(no_dec) - { - mulconst=10; /* Currently needed only for single digit corepll ratios */ - decval = 0; - } - else - { - j=0; - i++; /* Skipping the decimal point */ - while ((strptr[i] > 47) && (strptr[i] < 58)) - { - decarr[j] = strptr[i]; - i++; - j++; - } - - decarr_len = j; - decarr[j] = '\0'; - - mulconst=1; - for(i=0; i 1) { + if (argc > 1) { cmd = argv[1][1]; switch(cmd) { case 'f': /* reset with frequency changed */ @@ -560,7 +283,7 @@ my_usage: printf("For example: reset cf 40 2.5 10\n"); printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); return; - } else + } else out8(PIXIS_BASE+PIXIS_RST,0); #endif /* !CONFIG_MPC8641HPCN */ @@ -598,7 +321,6 @@ void dma_init(void) dma->satr0 = 0x00040000; dma->datr0 = 0x00040000; asm("sync; isync"); - return; } uint dma_check(void) From b2a941de060350ad15878d8219825f4950e9bb8e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 10:07:28 -0500 Subject: [PATCH 019/101] Remove dead debug code. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/cpu.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index e21b05126..504ba6240 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -35,28 +35,6 @@ #include "../board/mpc8641hpcn/pixis.h" -static __inline__ unsigned long get_dbat3u (void) -{ - unsigned long dbat3u; - asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); - return dbat3u; -} - -static __inline__ unsigned long get_dbat3l (void) -{ - unsigned long dbat3l; - asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); - return dbat3l; -} - -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - - int checkcpu (void) { sys_info_t sysinfo; @@ -141,8 +119,6 @@ int checkcpu (void) } -/* -------------------------------------------------------------------- */ - static inline void soft_restart(unsigned long addr) { From 4d3d729c16c392d2982d3266b659d333c927697d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 11:24:28 -0500 Subject: [PATCH 020/101] Moved mpc8641hpcn_board_reset() out of cpu/ into board/. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 93 +++++++++++++++++++++++++++++++++ cpu/mpc86xx/cpu.c | 90 +++---------------------------- 2 files changed, 99 insertions(+), 84 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index d02a7eff3..dbc9b5e9b 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -25,6 +25,7 @@ */ #include +#include #include #include #include @@ -35,6 +36,9 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #endif +#include "pixis.h" + + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -292,4 +296,93 @@ ft_board_setup(void *blob, bd_t *bd) #endif +void +mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + ulong val; + ulong corepll; + if (argc > 1) { + cmd = argv[1][1]; + switch (cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1); /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + } else + goto my_usage; + + while(1); /* Not reached */ + + } else if(argv[2][1] == 'd'){ + /* Reset from next bank without changing frequencies but with watchdog timer enabled */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + + } else { + /* Reset from next bank without changing frequency and without watchdog timer enabled */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Resetting board to boot from the other bank....\n"); + set_px_go(); + } + + default: + goto my_usage; + } + + my_usage: + printf("\nUsage: reset cf \n"); + printf(" reset altbank [cf ]\n"); + printf("For example: reset cf 40 2.5 10\n"); + printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); + return; + + } else + out8(PIXIS_BASE+PIXIS_RST,0); +} diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 504ba6240..60ce29ccd 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -32,7 +32,10 @@ #include #endif -#include "../board/mpc8641hpcn/pixis.h" +#ifdef CONFIG_MPC8641HPCN +extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[]); +#endif int checkcpu (void) @@ -146,9 +149,7 @@ soft_restart(unsigned long addr) void do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - char cmd; - ulong addr, val; - ulong corepll; + ulong addr; #ifdef CFG_RESET_ADDRESS addr = CFG_RESET_ADDRESS; @@ -181,86 +182,7 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #else /* CONFIG_MPC8641HPCN */ - if (argc > 1) { - cmd = argv[1][1]; - switch(cmd) { - case 'f': /* reset with frequency changed */ - if (argc < 5) - goto my_usage; - read_from_px_regs(0); - - val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); - - corepll = strfractoint(argv[3]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4], - NULL, 10)); - if (val == 3) { - printf("Setting registers VCFGEN0 and VCTL\n"); - read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); - } else - goto my_usage; - - while (1); /* Not reached */ - - case 'l': - if (argv[2][1] == 'f') { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); - if (val == 3) { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - } else - goto my_usage; - - while(1); /* Not reached */ - } else if(argv[2][1] == 'd'){ - /* Reset from next bank without changing frequencies but with watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - } else { - /* Reset from next bank without changing frequency and without watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Resetting board to boot from the other bank....\n"); - set_px_go(); - } - - default: - goto my_usage; - } - -my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; - } else - out8(PIXIS_BASE+PIXIS_RST,0); + mpc8641_reset_board(cmdtp, flag, argc, argv); #endif /* !CONFIG_MPC8641HPCN */ From 3d5c5be547445dd3bd2eb7368d80df03ea437970 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 11:39:34 -0500 Subject: [PATCH 021/101] Removed unneeded local_bus_init() from 8641HPCN board. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 34 --------------------------------- 1 file changed, 34 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index dbc9b5e9b..0b08df203 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -45,7 +45,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); extern long int spd_sdram(void); -void local_bus_init(void); void sdram_init(void); long int fixed_sdram(void); @@ -91,11 +90,6 @@ int checkboard (void) printf("PCI-EXPRESS1: Disabled\n"); #endif - /* - * Initialize local bus. - */ - local_bus_init(); - return 0; } @@ -129,34 +123,6 @@ initdram(int board_type) } -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; -} - #if defined(CFG_DRAM_TEST) int testdram(void) { From cb5965fb95b77a49f4e6af95248e0c849f4af03e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 12:44:44 -0500 Subject: [PATCH 022/101] White space cleanup. Some 80-column cleanups. Convert printf() to puts() where possible. Use #include "spd_sdram.h" as needed. Enhanced reset command usage message a bit. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 221 ++++++++++++++++---------------- cpu/mpc86xx/cpu.c | 27 ++-- 2 files changed, 127 insertions(+), 121 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 0b08df203..5cd3e9779 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -38,12 +38,13 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #include "pixis.h" - #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif -extern long int spd_sdram(void); +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif void sdram_init(void); long int fixed_sdram(void); @@ -51,7 +52,7 @@ long int fixed_sdram(void); int board_early_init_f (void) { - return 0; + return 0; } int checkboard (void) @@ -60,34 +61,32 @@ int checkboard (void) #ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - - if ((io_sel==2 || io_sel==3 || io_sel==5 \ - || io_sel==6 || io_sel==7 || io_sel==0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - debug ("PCI-EXPRESS 1: %s \n", - pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug ("\n"); - } else { - printf ("PCI-EXPRESS 1: Disabled\n"); - } + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); + } + debug ("\n"); + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } #else - printf("PCI-EXPRESS1: Disabled\n"); + puts("PCI-EXPRESS1: Disabled\n"); #endif return 0; @@ -98,7 +97,6 @@ long int initdram(int board_type) { long dram_size = 0; - extern long spd_sdram (void); #if defined(CONFIG_SPD_EEPROM) dram_size = spd_sdram (); @@ -110,7 +108,7 @@ initdram(int board_type) puts(" DDR: "); return dram_size; #endif - + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. @@ -130,7 +128,7 @@ int testdram(void) uint *pend = (uint *) CFG_MEMTEST_END; uint *p; - printf("SDRAM test phase 1:\n"); + puts("SDRAM test phase 1:\n"); for (p = pstart; p < pend; p++) *p = 0xaaaaaaaa; @@ -141,7 +139,7 @@ int testdram(void) } } - printf("SDRAM test phase 2:\n"); + puts("SDRAM test phase 2:\n"); for (p = pstart; p < pend; p++) *p = 0x55555555; @@ -152,7 +150,7 @@ int testdram(void) } } - printf("SDRAM test passed.\n"); + puts("SDRAM test passed.\n"); return 0; } #endif @@ -177,9 +175,9 @@ long int fixed_sdram(void) ddr->sdram_mode_1 = CFG_DDR_MODE_1; ddr->sdram_mode_2 = CFG_DDR_MODE_2; ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; - ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; #if defined (CONFIG_DDR_ECC) @@ -187,7 +185,7 @@ long int fixed_sdram(void) ddr->err_sbe = 0x00ff0000; #endif asm("sync;isync"); - + udelay(500); #if defined (CONFIG_DDR_ECC) @@ -198,7 +196,7 @@ long int fixed_sdram(void) ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; #endif asm("sync; isync"); - + udelay(500); #endif return CFG_SDRAM_SIZE * 1024 * 1024; @@ -251,13 +249,12 @@ ft_board_setup(void *blob, bd_t *bd) int len; ft_cpu_setup(blob, bd); - + p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } - } #endif @@ -269,86 +266,96 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong val; ulong corepll; - if (argc > 1) { - cmd = argv[1][1]; - switch (cmd) { - case 'f': /* reset with frequency changed */ - if (argc < 5) - goto my_usage; + /* + * No args is a simple reset request. + */ + if (argv <= 0) { + out8(PIXIS_BASE + PIXIS_RST, 0); + /* not reached */ + } + + cmd = argv[1][1]; + switch (cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1); /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); - val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); - - corepll = strfractoint(argv[3]); + corepll = strfractoint(argv[4]); val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); if (val == 3) { - printf("Setting registers VCFGEN0 and VCTL\n"); + puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); } else goto my_usage; - while (1); /* Not reached */ + while(1); /* Not reached */ - case 'l': - if (argv[2][1] == 'f') { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + } else if(argv[2][1] == 'd'){ + /* + * Reset from alternate bank without changing + * frequencies but with watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + puts("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); - if (val == 3) { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - } else - goto my_usage; - - while(1); /* Not reached */ - - } else if(argv[2][1] == 'd'){ - /* Reset from next bank without changing frequencies but with watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - - } else { - /* Reset from next bank without changing frequency and without watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Resetting board to boot from the other bank....\n"); - set_px_go(); - } - - default: - goto my_usage; + } else { + /* + * Reset from next bank without changing + * frequency and without watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Resetting board to boot from the other bank....\n"); + set_px_go(); } - my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; + default: + goto my_usage; + } - } else - out8(PIXIS_BASE+PIXIS_RST,0); + my_usage: + puts("\nUsage: reset cf \n"); + puts(" reset altbank [cf ]\n"); + puts(" reset altbank [wd]\n"); + puts("For example: reset cf 40 2.5 10\n"); + puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 60ce29ccd..fc77d9949 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -1,6 +1,6 @@ /* - * Copyright 2004 Freescale Semiconductor - * Jeff Brown (jeffrey@freescale.com) + * Copyright 2006 Freescale Semiconductor + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -55,8 +55,7 @@ int checkcpu (void) minor = PVR_MIN(pvr); puts("CPU:\n"); - - printf(" Core: "); + puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): @@ -112,11 +111,11 @@ int checkcpu (void) printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } - printf(" L2: "); + puts(" L2: "); if (get_l2cr() & 0x80000000) - printf("Enabled\n"); + puts("Enabled\n"); else - printf("Disabled\n"); + puts("Disabled\n"); return 0; } @@ -125,7 +124,6 @@ int checkcpu (void) static inline void soft_restart(unsigned long addr) { - #ifndef CONFIG_MPC8641HPCN /* SRR0 has system reset vector, SRR1 has default MSR value */ @@ -137,8 +135,11 @@ soft_restart(unsigned long addr) __asm__ __volatile__ ("rfi"); #else /* CONFIG_MPC8641HPCN */ - out8(PIXIS_BASE+PIXIS_RST,0); + + out8(PIXIS_BASE + PIXIS_RST, 0); + #endif /* !CONFIG_MPC8641HPCN */ + while(1); /* not reached */ } @@ -149,10 +150,10 @@ soft_restart(unsigned long addr) void do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong addr; +#ifndef CONFIG_MPC8641HPCN #ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; + ulong addr = CFG_RESET_ADDRESS; #else /* * note: when CFG_MONITOR_BASE points to a RAM address, @@ -160,11 +161,9 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * address. Better pick an address known to be invalid on your * system and assign it to CFG_RESET_ADDRESS. */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + ulong addr = CFG_MONITOR_BASE - sizeof(ulong); #endif -#ifndef CONFIG_MPC8641HPCN - /* flush and disable I/D cache */ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); From c934f655f9aeca70a5c5f88b465d9e9d57a8d22e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 13:55:35 -0500 Subject: [PATCH 023/101] Review cleanups. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/config.mk | 2 +- board/mpc8641hpcn/init.S | 26 ++++++------- board/mpc8641hpcn/mpc8641hpcn.c | 4 +- board/mpc8641hpcn/u-boot.lds | 2 +- cpu/mpc86xx/Makefile | 4 +- cpu/mpc86xx/config.mk | 4 +- cpu/mpc86xx/cpu_init.c | 11 +----- cpu/mpc86xx/i2c.c | 6 +-- cpu/mpc86xx/interrupts.c | 42 +++++++++----------- cpu/mpc86xx/speed.c | 69 +++++---------------------------- 10 files changed, 53 insertions(+), 117 deletions(-) diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk index 4bdceec4d..989a40b01 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/mpc8641hpcn/config.mk @@ -1,5 +1,5 @@ # Copyright 2004 Freescale Semiconductor. -# Modified by Jeff Brown (jeffrey@freescale.com) +# Modified by Jeff Brown # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 5f19fdfb6..69954a81a 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -59,7 +59,6 @@ #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) -/*#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */ #define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) /* @@ -72,7 +71,6 @@ #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) #define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) -/*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) @@ -86,7 +84,7 @@ #define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) #endif - .section .bootpg, "ax" + .section .bootpg, "ax" .globl law_entry law_entry: lis r7,CFG_CCSRBAR@h @@ -110,8 +108,8 @@ law_entry: stwu r6, 0x20(r4) lis r6,LAWAR2@h - ori r6,r6,LAWAR2@l - stwu r6, 0x20(r5) + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) /* LAWBAR3, LAWAR3 */ lis r6,LAWBAR3@h @@ -127,7 +125,7 @@ law_entry: ori r6,r6,LAWBAR4@l stwu r6, 0x20(r4) - lis r6,LAWAR4@h + lis r6,LAWAR4@h ori r6,r6,LAWAR4@l stwu r6, 0x20(r5) /* LAWBAR5, LAWAR5 */ @@ -157,14 +155,14 @@ law_entry: ori r6,r6,LAWAR7@l stwu r6, 0x20(r5) - /* LAWBAR8, LAWAR8 */ - lis r6,LAWBAR8@h - ori r6,r6,LAWBAR8@l - stwu r6, 0x20(r4) + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) - lis r6,LAWAR8@h - ori r6,r6,LAWAR8@l - stwu r6, 0x20(r5) + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) blr diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5cd3e9779..c6b2a5b3b 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * (C) Copyright 2002 Scott McNutt @@ -352,7 +352,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) goto my_usage; } - my_usage: +my_usage: puts("\nUsage: reset cf \n"); puts(" reset altbank [cf ]\n"); puts(" reset altbank [wd]\n"); diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index c5c40e7eb..b34de8e0a 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -1,7 +1,7 @@ /* * (C) Copyright 2004, Freescale, Inc. * (C) Copyright 2002,2003, Motorola,Inc. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * * See file CREDITS for list of people who contributed to this * project. diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index 0dd099df6..ab6255a7d 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -3,7 +3,7 @@ # Xianghua Xiao,X.Xiao@motorola.com # # (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port) -# Jeff Brown (Jeffrey@freescale.com) +# Jeff Brown # See file CREDITS for list of people who contributed to this # project. # @@ -30,7 +30,7 @@ LIB = lib$(CPU).a START = start.o #resetvec.o ASOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o i2c.o spd_sdram.o + pci.o i2c.o spd_sdram.o OBJS = $(COBJS) all: .depend $(START) $(ASOBJS) $(LIB) diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk index 4ef7ace2f..3c54f4ad3 100644 --- a/cpu/mpc86xx/config.mk +++ b/cpu/mpc86xx/config.mk @@ -1,6 +1,6 @@ # # (C) Copyright 2004 Freescale Semiconductor. -# Jeff Brown +# Jeff Brown # # See file CREDITS for list of people who contributed to this # project. @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring \ No newline at end of file +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index c816c1897..93b73381f 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -106,15 +106,6 @@ void cpu_init_f(void) /* enable SYNCBE | ABE bits in HID1 */ set_hid1(get_hid1() | 0x00000C00); - - /* Since the bats have been set up at this point and - * the local bus registers have been initialized, we - * turn on the WDEN bit in PIXIS_VCTL - */ -/* val = in8(PIXIS_BASE+PIXIS_VCTL); */ - /* Set the WDEN */ -/* val |= 0x08; */ -/* out8(PIXIS_BASE+PIXIS_VCTL,val); */ } /* diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c index f2b4b0f6d..b3ac848a4 100644 --- a/cpu/mpc86xx/i2c.c +++ b/cpu/mpc86xx/i2c.c @@ -7,7 +7,7 @@ * Gleb Natapov * Some bits are taken from linux driver writen by adrian@humboldt.co.uk * - * Modified for MPC86xx by Jeff Brown (jeffrey@freescale.com) + * Modified for MPC86xx by Jeff Brown * * Hardware I2C driver for MPC107 PCI bridge. * @@ -207,7 +207,7 @@ i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_read(data, length); - exit: +exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); return !(i == length); @@ -230,7 +230,7 @@ i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_write(data, length); - exit: +exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); return !(i == length); diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index b5cd439e5..a8bcb98b8 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -9,7 +9,7 @@ * Xianghua Xiao (X.Xiao@motorola.com) * * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) - * Jeff Brown (Jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -37,11 +37,10 @@ #include #include -unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ - - +unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ unsigned long timestamp; + static __inline__ unsigned long get_msr (void) { unsigned long msr; @@ -75,7 +74,7 @@ static __inline__ void set_dec (unsigned long val) /* interrupt is not supported yet */ int interrupt_init_cpu (unsigned *decrementer_count) { - return 0; + return 0; } @@ -89,14 +88,14 @@ int interrupt_init (void) if (ret) return ret; - decrementer_count = get_tbclk()/CFG_HZ; - debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); + decrementer_count = get_tbclk()/CFG_HZ; + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); - set_dec (decrementer_count); + set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); - debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); + debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); return 0; } @@ -119,7 +118,7 @@ int disable_interrupts (void) void increment_timestamp(void) { - timestamp++; + timestamp++; } /* @@ -136,15 +135,15 @@ timer_interrupt_cpu (struct pt_regs *regs) void timer_interrupt (struct pt_regs *regs) { - /* call cpu specific function from $(CPU)/interrupts.c */ - timer_interrupt_cpu (regs); + /* call cpu specific function from $(CPU)/interrupts.c */ + timer_interrupt_cpu (regs); - timestamp++; + timestamp++; - ppcDcbf(×tamp); + ppcDcbf(×tamp); - /* Restore Decrementer Count */ - set_dec (decrementer_count); + /* Restore Decrementer Count */ + set_dec (decrementer_count); #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) @@ -164,17 +163,17 @@ void timer_interrupt (struct pt_regs *regs) void reset_timer (void) { - timestamp = 0; + timestamp = 0; } ulong get_timer (ulong base) { - return timestamp - base; + return timestamp - base; } void set_timer (ulong t) { - timestamp = t; + timestamp = t; } /* @@ -192,11 +191,8 @@ irq_free_handler(int vec) } - -/******************************************************************************* - * +/* * irqinfo - print information about PCI devices,not implemented. - * */ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index a08ae5f94..5e05ab81f 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * (C) Copyright 2000-2002 @@ -29,9 +29,6 @@ #include #include -unsigned long get_board_sys_clk(ulong dummy); -unsigned long get_sysclk_from_px_regs(void); - void get_sys_info (sys_info_t *sysInfo) { @@ -39,11 +36,11 @@ void get_sys_info (sys_info_t *sysInfo) volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio, e600_ratio; - plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; switch(plat_ratio) { - case 0x0: + case 0x0: sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; break; case 0x02: @@ -55,19 +52,14 @@ void get_sys_info (sys_info_t *sysInfo) case 0x09: case 0x0a: case 0x0c: - case 0x10: - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; - break; + case 0x10: + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + break; default: sysInfo->freqSystemBus = 0; break; } -#if 0 - printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", - sysInfo->freqSystemBus, plat_ratio); -#endif - e600_ratio = (gur->porpllsr) & 0x003f0000; e600_ratio >>= 16; @@ -75,13 +67,13 @@ void get_sys_info (sys_info_t *sysInfo) case 0x10: sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; break; - case 0x19: + case 0x19: sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2; break; case 0x20: sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; break; - case 0x39: + case 0x39: sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2; break; case 0x28: @@ -90,16 +82,10 @@ void get_sys_info (sys_info_t *sysInfo) case 0x1d: sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2; break; - default: - /* JB - Emulator workaround until real cop is plugged in */ - /* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */ + default: sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; break; } -#if 0 - printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", - sysInfo->freqProcessor, e600_ratio); -#endif } @@ -128,6 +114,7 @@ int get_clocks(void) * get_bus_freq * Return system bus freq in Hz */ + ulong get_bus_freq(ulong dummy) { ulong val; @@ -139,42 +126,6 @@ ulong get_bus_freq(ulong dummy) return val; } -unsigned long get_sysclk_from_px_regs() -{ - ulong val; - u8 vclkh, vclkl; - - vclkh = in8(PIXIS_BASE + PIXIS_VCLKH); - vclkl = in8(PIXIS_BASE + PIXIS_VCLKL); - - if ((vclkh == 0x84) && (vclkl == 0x07)) { - val = 33000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x20)) { - val = 40000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x2A)) { - val = 50000000; - } - if ((vclkh == 0x24) && (vclkl == 0x04)) { - val = 66000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x4B)) { - val = 83000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x5C)) { - val = 100000000; - } - if ((vclkh == 0xDF) && (vclkl == 0x3B)) { - val = 134000000; - } - if ((vclkh == 0xDF) && (vclkl == 0x4B)) { - val = 166000000; - } - - return val; -} - /* * get_board_sys_clk From c83ae9ea6d93abbe751bf8a3396236a084e56f87 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 6 Jun 2006 16:54:29 -0400 Subject: [PATCH 024/101] Modify the IRQ of DUART2 --- board/mpc8641hpcn/oftree.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 26ce6618a..a11c32171 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -187,7 +187,7 @@ compatible = "ns16550"; reg = <4600 100>; clock-frequency = <0>; - interrupts = <2a 3>; + interrupts = <1c 3>; interrupt-parent = <40000>; }; From d9bf4858fca5aa4d651b283270f77da72ebadfd5 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 7 Jun 2006 10:52:49 -0500 Subject: [PATCH 025/101] Allow DTC path to be passed in. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 261373040..060db84ef 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -31,8 +31,12 @@ SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) +ifndef DTC +DTC := dtc +endif + %.dtb: %.dts - dtc -f -V 0x10 -I dts -O dtb $< >$@ + $(DTC) -f -V 0x10 -I dts -O dtb $< >$@ %.c: %.dtb xxd -i $< \ From 8ecc971618f56029ad99d3516f8b297a6ed58971 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 7 Jun 2006 10:53:55 -0500 Subject: [PATCH 026/101] Fix a get_board_sys_clk() use-before-def warning. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/speed.c | 128 ++++++++++++++++++++++---------------------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 5e05ab81f..6775a1143 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -30,6 +30,70 @@ #include +/* + * get_board_sys_clk + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ + +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i, go_bit, rd_clks; + ulong val = 0; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} + + void get_sys_info (sys_info_t *sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; @@ -125,67 +189,3 @@ ulong get_bus_freq(ulong dummy) return val; } - - -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val; - - go_bit = in8(PIXIS_BASE + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in8(PIXIS_BASE + PIXIS_AUX); - else - i = in8(PIXIS_BASE + PIXIS_SPD); - } else { - i = in8(PIXIS_BASE + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; -} From 0e4c2a17ca34001ed36d259f13cb88ada4611a8c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 15 Jun 2006 21:33:37 -0500 Subject: [PATCH 027/101] Do not enable address translation on secondary CPUs. Do not set up BATs on secondary CPUs. Let Linux do the nasty. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/start.S | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 07e75572b..12bf75b2e 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -1196,13 +1196,6 @@ secondary_cpu_setup: sync #endif - /* setup the bats */ - bl setup_bats - sync - /* enable address translation */ - bl enable_addr_trans - sync - /* enable and invalidate the data cache */ bl dcache_enable sync @@ -1211,14 +1204,6 @@ secondary_cpu_setup: bl icache_enable sync - /* Set up MSR and HID0, HID1*/ - /* Enable interrupts */ -/* mfmsr r28 - li r4,0 - ori r4,r4,MSR_EE - or r28,r28,r4 - mtmsr r28 - */ /* TBEN in HID0 */ mfspr r4, HID0 From 8be429a5ddbf0ebe2d94174ba58fcfc7a24285dc Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Tue, 20 Jun 2006 17:47:15 +0800 Subject: [PATCH 028/101] Reworked IRQ mapping in OF-tree. --- board/mpc8641hpcn/oftree.dts | 94 +++++++++++++++++++++--------------- 1 file changed, 55 insertions(+), 39 deletions(-) diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index a11c32171..32ba36747 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -71,7 +71,7 @@ device_type = "i2c"; compatible = "fsl-i2c"; reg = <3000 100>; - interrupts = <2b 0>; + interrupts = <2b 2>; interrupt-parent = <40000>; dfsrr; }; @@ -80,7 +80,7 @@ device_type = "i2c"; compatible = "fsl-i2c"; reg = <3100 100>; - interrupts = <2b 0>; + interrupts = <2b 2>; interrupt-parent = <40000>; dfsrr; }; @@ -95,28 +95,28 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = <3a 0>; + interrupts = <4a 1>; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = <3a 0>; + interrupts = <4a 1>; reg = <1>; device_type = "ethernet-phy"; }; ethernet-phy@2 { linux,phandle = <2452002>; interrupt-parent = <40000>; - interrupts = <3a 0>; + interrupts = <4a 1>; reg = <2>; device_type = "ethernet-phy"; }; ethernet-phy@3 { linux,phandle = <2452003>; interrupt-parent = <40000>; - interrupts = <3a 0>; + interrupts = <4a 1>; reg = <3>; device_type = "ethernet-phy"; }; @@ -130,7 +130,7 @@ compatible = "gianfar"; reg = <24000 1000>; address = [ 00 E0 0C 00 73 00 ]; - interrupts = <1d 3 1e 3 22 3>; + interrupts = <1d 2 1e 2 22 2>; interrupt-parent = <40000>; phy-handle = <2452000>; }; @@ -143,7 +143,7 @@ compatible = "gianfar"; reg = <25000 1000>; address = [ 00 E0 0C 00 73 01 ]; - interrupts = <23 3 24 3 28 3>; + interrupts = <23 2 24 2 28 2>; interrupt-parent = <40000>; phy-handle = <2452001>; }; @@ -156,7 +156,7 @@ compatible = "gianfar"; reg = <26000 1000>; address = [ 00 E0 0C 00 02 FD ]; - interrupts = <1F 3 20 3 21 3>; + interrupts = <1F 2 20 2 21 2>; interrupt-parent = <40000>; phy-handle = <2452002>; }; @@ -169,16 +169,16 @@ compatible = "gianfar"; reg = <27000 1000>; address = [ 00 E0 0C 00 03 FD ]; - interrupts = <25 3 26 3 27 3>; + interrupts = <25 2 26 2 27 2>; interrupt-parent = <40000>; phy-handle = <2452003>; }; serial@4500 { device_type = "serial"; - compatible = "ns16550"; + compatible = "ns16550"; reg = <4500 100>; clock-frequency = <0>; - interrupts = <2a 3>; + interrupts = <2a 2>; interrupt-parent = <40000>; }; @@ -187,7 +187,7 @@ compatible = "ns16550"; reg = <4600 100>; clock-frequency = <0>; - interrupts = <1c 3>; + interrupts = <2a 2>; interrupt-parent = <40000>; }; @@ -204,8 +204,8 @@ 01000000 0 00000000 e2000000 0 00100000>; clock-frequency = <1fca055>; interrupt-parent = <40000>; - interrupts = <8 0>; - interrupt-map-mask = ; + interrupts = <18 2>; + interrupt-map-mask = ; interrupt-map = < /* IDSEL 0x11 */ 8800 0 0 1 40000 3 0 @@ -220,16 +220,16 @@ 9000 0 0 4 40000 3 0 /* IDSEL 0x13 */ - 9800 0 0 1 40000 5 0 - 9800 0 0 2 40000 6 0 - 9800 0 0 3 40000 3 0 - 9800 0 0 4 40000 4 0 + 9800 0 0 1 40000 0 0 + 9800 0 0 2 40000 0 0 + 9800 0 0 3 40000 0 0 + 9800 0 0 4 40000 0 0 /* IDSEL 0x14 */ - a000 0 0 1 40000 6 0 - a000 0 0 2 40000 3 0 - a000 0 0 3 40000 4 0 - a000 0 0 4 40000 5 0 + a000 0 0 1 40000 0 0 + a000 0 0 2 40000 0 0 + a000 0 0 3 40000 0 0 + a000 0 0 4 40000 0 0 /* IDSEL 0x15 */ a800 0 0 1 40000 0 0 @@ -262,41 +262,41 @@ c800 0 0 4 40000 0 0 /* IDSEL 0x1a */ - d000 0 0 1 40000 0 0 - d000 0 0 2 40000 0 0 - d000 0 0 3 40000 0 0 - d000 0 0 4 40000 0 0 + d000 0 0 1 40000 6 0 + d000 0 0 2 40000 3 0 + d000 0 0 3 40000 4 0 + d000 0 0 4 40000 5 0 /* IDSEL 0x1b */ - d800 0 0 1 40000 0 0 + d800 0 0 1 40000 5 0 d800 0 0 2 40000 0 0 d800 0 0 3 40000 0 0 d800 0 0 4 40000 0 0 /* IDSEL 0x1c */ - e000 0 0 1 40000 0 0 - e000 0 0 2 40000 0 0 - e000 0 0 3 40000 0 0 - e000 0 0 4 40000 0 0 + e000 0 0 1 40000 9 0 + e000 0 0 2 40000 a 0 + e000 0 0 3 40000 c 0 + e000 0 0 4 40000 7 0 /* IDSEL 0x1d */ - e800 0 0 1 40000 0 0 - e800 0 0 2 40000 0 0 - e800 0 0 3 40000 0 0 + e800 0 0 1 40000 9 0 + e800 0 0 2 40000 a 0 + e800 0 0 3 40000 b 0 e800 0 0 4 40000 0 0 /* IDSEL 0x1e */ - f000 0 0 1 40000 0 0 + f000 0 0 1 40000 c 0 f000 0 0 2 40000 0 0 f000 0 0 3 40000 0 0 f000 0 0 4 40000 0 0 /* IDSEL 0x1f */ f800 0 0 1 40000 6 0 - f800 0 0 2 40000 6 0 - f800 0 0 3 40000 6 0 - f800 0 0 4 40000 6 0 + f800 0 0 2 40000 0 0 + f800 0 0 3 40000 0 0 + f800 0 0 4 40000 0 0 >; }; pic@40000 { @@ -310,6 +310,22 @@ compatible = "chrp,open-pic"; device_type = "open-pic"; big-endian; + interrupts = < + 10 2 11 2 12 2 13 2 + 14 2 15 2 16 2 17 2 + 18 2 19 2 1a 2 1b 2 + 1c 2 1d 2 1e 2 1f 2 + 20 2 21 2 22 2 23 2 + 24 2 25 2 26 2 27 2 + 28 2 29 2 2a 2 2b 2 + 2c 2 2d 2 2e 2 2f 2 + 30 2 31 2 32 2 33 2 + 34 2 35 2 36 2 37 2 + 38 2 39 2 2a 2 3b 2 + 3c 2 3d 2 3e 2 3f 2 + 48 1 49 2 4a 1 + >; + interrupt-parent = <40000>; }; }; }; From 684623ce92c5fd32e7db2d6e016945a67c5ffaba Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 22 Jun 2006 08:51:46 -0500 Subject: [PATCH 029/101] Fix bug in 8641hpcn reset command with no args. Signed-off-by: Haiying Wang Acked-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index c6b2a5b3b..2626cccb9 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -269,7 +269,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * No args is a simple reset request. */ - if (argv <= 0) { + if (argc <= 1) { out8(PIXIS_BASE + PIXIS_RST, 0); /* not reached */ } From fa7db9c377bc2353a17bf1d381d65a6c418728f0 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:11:54 +0800 Subject: [PATCH 030/101] Enable PCIE1 for MPC8641HPCN board Signed-off-by: Jason Jin --- cpu/mpc86xx/Makefile | 4 +- cpu/mpc86xx/pci.c | 186 ++++++++++++++------------------ cpu/mpc86xx/pcie_indirect.c | 198 ++++++++++++++++++++++++++++++++++ include/asm-ppc/immap_86xx.h | 62 +++++------ include/configs/MPC8641HPCN.h | 20 ++-- 5 files changed, 327 insertions(+), 143 deletions(-) create mode 100644 cpu/mpc86xx/pcie_indirect.c diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index ab6255a7d..799594516 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -28,9 +28,9 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o #resetvec.o -ASOBJS = cache.o +ASOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o i2c.o spd_sdram.o + pci.o pcie_indirect.o i2c.o spd_sdram.o OBJS = $(COBJS) all: .depend $(START) $(ASOBJS) $(LIB) diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c index 05976bdd4..deb66aa64 100644 --- a/cpu/mpc86xx/pci.c +++ b/cpu/mpc86xx/pci.c @@ -1,6 +1,9 @@ /* - * Copyright 2005 Freescale Semiconductor. + * Copyright (C) Freescale Semiconductor,Inc. + * 2005, 2006. All rights reserved. + * * Ed Swarthout (ed.swarthout@freescale.com) + * Jason Jin (Jason.jin@freescale.com) * * See file CREDITS for list of people who contributed to this * project. @@ -22,142 +25,115 @@ */ /* - * PEX Configuration space access support for PEX Bridge + * PCIE Configuration space access support for PCIE Bridge */ #include #include - #if defined(CONFIG_PCI) - void pci_mpc86xx_init(struct pci_controller *hose) { volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; + volatile ccsr_pex_t *pcie1 = &immap->im_pex1; + u16 temp16; + u32 temp32; + volatile ccsr_gur_t *gur = &immap->im_gur; uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_host = (host1_agent == 2) || (host1_agent == 3); + uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); + uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - u16 reg16, reg16_1, reg16_2, reg16_3; - u32 reg32, i; + if ((io_sel ==2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || + io_sel == 7 || io_sel == 0xf) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + printf ("PCI-EXPRESS 1: Configured as %s \n", + pcie1_agent ? "Agent" : "Host"); + if(pcie1_agent) return; /*Don't scan bus when configured as agent*/ + printf (" Scanning PCIE bus"); + debug("0x%08x=0x%08x ", &pcie1->pme_msg_det,pcie1->pme_msg_det); + if (pcie1->pme_msg_det) { + pcie1->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x", + pcie1->pme_msg_det); + } + debug ("\n"); + } + else{ + printf("PCI-EXPRESS 1 disabled!\n"); + return; + } - ulong addr, data; + /*set first_bus=0 only skipped B0:D0:F0 which is + * a reserved device in M1575, but make it easy for + * most of the scan process. + */ + hose->first_busno = 0x00; + hose->last_busno = 0xfe; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + pcie_setup_indirect(hose, + (CFG_IMMR+0x8000), + (CFG_IMMR+0x8004)); - if ((io_sel==2 || io_sel==3 || io_sel==5 - || io_sel==6 || io_sel==7 || io_sel==0xF ) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - printf ("PCI-EXPRESS 1: Configured as %s \n", - pex1_agent ? "Agent" : "Host"); - printf (" Scanning PCI bus"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug ("\n"); - } + pci_hose_read_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, &temp16); + temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, temp16); - hose->first_busno = 0; - hose->last_busno = 0x7f; + pci_hose_write_config_word(hose,PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 0x80); + + pci_hose_read_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, &temp32); + temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); + pci_hose_write_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, temp32); + + pcie1->powar1 = 0; + pcie1->powar2 = 0; + pcie1->piwar1 = 0; + pcie1->piwar1 = 0; + + pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->powar1 = 0x8004401c; /* 512M MEM space */ + pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->potear1 = 0x00000000; + + pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcie1->powar2 = 0x80088017; /* 16M IO space */ + pcie1->potar2 = 0x00000000; + pcie1->potear2 = 0x00000000; + + pcie1->pitar1 = 0x00000000; + pcie1->piwbar1 = 0x00000000; + /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ + pcie1->piwar1 = 0xa0f5501e; pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + pci_set_region(hose->regions + 1, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); - pci_set_region(hose->regions + 1, + pci_set_region(hose->regions + 2, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 2; + hose->region_count = 3; - pci_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); - - /* - * Hose scan. - */ pci_register_hose(hose); - pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16); - debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16); - pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16); - debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16); - - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY \ - | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - /* - * pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - * pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); - */ - - pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pex1->powar1 = 0x8004401c; /* 512M MEM space */ - pex1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pex1->potear1 = 0x00000000; - - pex1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pex1->powar2 = 0x80088017; /* 16M IO space */ - pex1->potar2 = 0x00000000; - pex1->potear2 = 0x00000000; - - if (!pex1->piwar1) { - pex1->pitar1 = 0x00000000; - pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff; - pex1->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - * Snoop R/W, 2G */ - } - - pex1->pitar2 = 0x00000000; - pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff; - pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - * Snoop R/W, 2G */ - - *(u32 *)(0xf8008000)= 0x80000000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", - *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", - *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", - *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", - *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - hose->last_busno = pci_hose_scan(hose); - hose->last_busno = 0x21; - debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); - debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); + debug("pcie_mpc86xx_init: last_busno %x\n",hose->last_busno); + debug("pcie_mpc86xx init: current_busno %x\n ",hose->current_busno); - printf("....PCI scan & enumeration done\n"); + printf("....PCIE1 scan & enumeration done\n"); } - #endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c new file mode 100644 index 000000000..e3cb4beed --- /dev/null +++ b/cpu/mpc86xx/pcie_indirect.c @@ -0,0 +1,198 @@ +/* + * Support for indirect PCI bridges. + * + * Copyright (c) Freescale Semiconductor, Inc. + * 2006. All rights reserved. + * + * Jason Jin + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * partly derived from + * arch/powerpc/platforms/86xx/mpc86xx_pcie.c + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include + +#define PCI_CFG_OUT out_be32 +#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff) + +static int +indirect_read_config_pcie(struct pci_controller *hose, + pci_dev_t dev, int offset, + int len,u32 *val) +{ + int bus = PCI_BUS(dev); + char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ; + + unsigned char *cfg_data; + u32 temp; + + PEX_FIX; + if( bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); + }else { + PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); + } + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ + cfg_data = hose->cfg_data; + PEX_FIX; + temp = in_le32(cfg_data); + switch (len) { + case 1: + *val = (temp >> (((offset & 3))*8)) & 0xff; + break; + case 2: + *val = (temp >> (((offset & 3))*8)) & 0xffff; + break; + default: + *val = temp; + break; + } + + return 0; +} + +static int +indirect_write_config_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + int len, + u32 val) +{ + int bus = PCI_BUS(dev); + char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ; + + unsigned char *cfg_data; + u32 temp; + + PEX_FIX; + if( bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); + }else { + PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); + } + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ + cfg_data = hose->cfg_data; + switch (len) { + case 1: + PEX_FIX; + temp = in_le32(cfg_data); + temp = (temp & ~(0xff << ((offset & 3) * 8))) | + (val << ((offset & 3) * 8)); + PEX_FIX; + out_le32(cfg_data, temp); + break; + case 2: + PEX_FIX; + temp = in_le32(cfg_data); + temp = (temp & ~(0xffff << ((offset & 3) * 8))); + temp |= (val << ((offset & 3) * 8)) ; + PEX_FIX; + out_le32(cfg_data, temp); + break; + default: + PEX_FIX; + out_le32(cfg_data, val); + break; + } + PEX_FIX; + return 0; +} + +static int +indirect_read_config_byte_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u8 *val) +{ + u32 val32; + indirect_read_config_pcie(hose,dev,offset,1,&val32); + *val = (u8)val32; + return 0; +} + +static int +indirect_read_config_word_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u16 *val) +{ + u32 val32; + indirect_read_config_pcie(hose,dev,offset,2,&val32); + *val = (u16)val32; + return 0; +} + +static int +indirect_read_config_dword_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + u32 *val) +{ + return indirect_read_config_pcie(hose,dev, offset,4,val); +} + +static int +indirect_write_config_byte_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + char val) +{ + return indirect_write_config_pcie(hose,dev, offset,1,(u32)val); +} + +static int +indirect_write_config_word_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + unsigned short val) +{ + return indirect_write_config_pcie(hose,dev, offset,2,(u32)val); +} + +static int +indirect_write_config_dword_pcie(struct pci_controller *hose, + pci_dev_t dev, + int offset, + unsigned short val) +{ + return indirect_write_config_pcie(hose,dev, offset,4,val); +} + +void +pcie_setup_indirect(struct pci_controller* hose, + u32 cfg_addr, + u32 cfg_data) +{ + pci_set_ops(hose, + indirect_read_config_byte_pcie, + indirect_read_config_word_pcie, + indirect_read_config_dword_pcie, + indirect_write_config_byte_pcie, + indirect_write_config_word_pcie, + indirect_write_config_dword_pcie); + + hose->cfg_addr = (unsigned int *) cfg_addr; + hose->cfg_data = (unsigned char *) cfg_data; +} + +#endif /* CONFIG_PCI */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 9e81b4707..5b1f0f4ea 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -284,41 +284,41 @@ typedef struct ccsr_pex { char res2[16]; uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ - uint pme_msg_dis; /* 0x802C - PEX PME & message disable register */ - char res3[4]; - uint pm_command; /* 0x8030 - PEX PM Command register */ - char res4[3016]; - uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ - uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ + uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */ + uint pm_command; /* 0x802c - PEX PM Command register */ + char res3[3016]; + uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ + uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ - char res5[8]; + char res4[8]; uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ - char res6[12]; + char res5[12]; uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ - char res7[4]; + char res6[4]; uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ - char res8[12]; + char res7[12]; uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ - char res9[4]; + char res8[4]; uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ - char res10[12]; + char res9[12]; uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ - char res11[4]; + char res10[4]; uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ - char res12[12]; + char res11[12]; uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ - char res13[4]; + char res12[4]; uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ - char res14[268]; + char res13[12]; + char res14[256]; uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ char res15[4]; uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ @@ -332,23 +332,25 @@ typedef struct ccsr_pex { uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ char res18[12]; uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ - char res19[4]; + char res19[4]; uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ - char res20[4]; + uint piwbear1; uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ - char res21[12]; + char res20[12]; uint pedr; /* 0x8e00 - PEX Error Detect Register */ - uint pecdr; /* 0x8e04 - PEX Error Capture Disable Register */ - uint peer; /* 0x8e08 - PEX Error Enable Register */ - uint perr_cap0; /* 0x8e0c - PEX Error Capture Register 0 */ - uint perr_cap1; /* 0x8e10 - PEX Error Capture Register 1 */ - uint perr_cap2; /* 0x8e14 - PEX Error Capture Register 2 */ - uint perr_cap3; /* 0x8e18 - PEX Error Capture Register 3 */ - char res22[100]; - uint perr_stat; /* 0x8e80 - PEX Error Status Register */ - char res23[124]; - uint pdebug; /* 0x8f00 - PEX Debug Register */ - char res24[248]; //Sri: changed this because of adding 4 bytes before 0x?8020. + char res21[4]; + uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */ + char res22[4]; + uint pecdr; /* 0x8e10 - PEX Error Disable Register */ + char res23[12]; + uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */ + char res24[4]; + uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */ + uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */ + uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */ + uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */ + char res25[452]; + char res26[4]; } ccsr_pex_t; /* Hyper Transport Register Block (0xA000-0xB000) */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 2a197be29..4453171d4 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,7 +46,8 @@ #define CFG_RESET_ADDRESS 0xfff00100 -#undef CONFIG_PCI +/*#undef CONFIG_PCI*/ +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -209,8 +210,10 @@ #undef CFG_RAMBOOT #endif -#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT) -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#if defined(CFG_RAMBOOT) +#undef CFG_FLASH_CFI_DRIVER +#undef CONFIG_SPD_EEPROM +#define CFG_SDRAM_SIZE 256 #endif #undef CONFIG_CLOCKS_IN_MHZ @@ -295,6 +298,11 @@ #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + /* For RTL8139 */ #define _IO_BASE 0x00000000 @@ -429,10 +437,10 @@ * BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U CFG_DBAT6U #define CFG_DBAT7L 0x00000000 From bd22c2b97514fbfb0e03bd9c72b3445e4dbd57e2 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:12:02 +0800 Subject: [PATCH 031/101] Fix bug for io_bar size during pci scan During the pci scan process, Some devices return bar_reponse with the highest bytes 0, such as the pci bridge in uli1575 return bar_response with 0xffffff, So the bar_size should be manually set under 64K. Signed-off-by: Jason Jin --- drivers/pci_auto.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 15f74328f..9e921b214 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -102,7 +102,8 @@ void pciauto_setup_device(struct pci_controller *hose, /* Check the BAR type and set our address mask */ if (bar_response & PCI_BASE_ADDRESS_SPACE) { - bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) + & 0xffff) + 1; bar_res = io; DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size); From fcfb9a57947fc203b99fe81ab0578f7286261f9f Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:12:23 +0800 Subject: [PATCH 032/101] Fix Tsec bug when no link When tftp a non-exist file from the tftp server, u-boot will check the link of all eth port. The original file will return wrong link state on the no link ports. signed-off-by: Jason Jin --- drivers/tsec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index 18778c270..a8a2ba2f5 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -372,7 +372,7 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts (" TIMEOUT !\n"); priv->link = 0; - break; + return 0; } if ((i++ % 1000) == 0) { From bc09cf3c2bfb8d54c659cbb332f79d0950982fd0 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong-R64188 Date: Tue, 27 Jun 2006 18:12:10 +0800 Subject: [PATCH 033/101] Fix RTL8139 in big endian signed-off-by: Jason Jin signed-off-by: Wei Zhang --- drivers/rtl8139.c | 1 + include/configs/MPC8641HPCN.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index a95f84e62..848d1d177 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -196,6 +196,7 @@ static void rtl_disable(struct eth_device *dev); static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, + {0x1186, 0x1300}, {} }; diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 4453171d4..b0897695a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -304,6 +304,7 @@ #define CFG_PCI_MEMORY_SIZE 0x80000000 /* For RTL8139 */ +#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000 #define CFG_PCI2_MEM_BASE 0xa0000000 From da012ab661fd4ab169dd7b9b32201a4df62cf34a Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 28 Jun 2006 08:43:56 -0500 Subject: [PATCH 034/101] Change Id to symbolic name for RTL8139 Signed-off-by: Jason Jin --- drivers/rtl8139.c | 2 +- include/pci_ids.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c index 848d1d177..afe1a4fda 100644 --- a/drivers/rtl8139.c +++ b/drivers/rtl8139.c @@ -196,7 +196,7 @@ static void rtl_disable(struct eth_device *dev); static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, - {0x1186, 0x1300}, + {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139}, {} }; diff --git a/include/pci_ids.h b/include/pci_ids.h index 8cc3ec0a2..3b1045241 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1045,6 +1045,9 @@ #define PCI_DEVICE_ID_REALTEK_8139 0x8139 #define PCI_DEVICE_ID_REALTEK_8169 0x8169 +#define PCI_VENDOR_ID_DLINK 0x1186 +#define PCI_DEVICE_ID_DLINK_8139 0x1300 + #define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_TURBOPAM 0x4020 From e6cd2a1785d74ec3d30a86f1cb360be8de478151 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 7 Jul 2006 10:01:45 -0500 Subject: [PATCH 035/101] We made a u-boot patch to fix the hang up issue when booting filesystem from ramdisk. Signed-off-by:Jason Jin --- common/cmd_bootm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index e5d70fa20..a78a16df9 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -538,6 +538,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_copy_to_ram = 0; } else { /* not set, no restrictions to load high */ initrd_high = ~0; + initrd_copy_to_ram = 0; } #ifdef CONFIG_LOGBUFFER From fcb28e763415e0e4e66b0f45842d1557ae198e5e Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Thu, 13 Jul 2006 10:35:10 -0500 Subject: [PATCH 036/101] Fixed initrd issue by define big RAM Signed-off-by:Jason Jin --- common/cmd_bootm.c | 1 - include/configs/MPC8641HPCN.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index a78a16df9..e5d70fa20 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -538,7 +538,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_copy_to_ram = 0; } else { /* not set, no restrictions to load high */ initrd_high = ~0; - initrd_copy_to_ram = 0; } #ifdef CONFIG_LOGBUFFER diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b0897695a..aca2ecc23 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -100,6 +100,7 @@ */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM #define MPC86xx_DDR_SDRAM_CLK_CNTL From bea3f28d285942bf3f7ab339ce85178ded544225 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 12 Jul 2006 10:48:05 -0400 Subject: [PATCH 037/101] Add support for reading and writing mac addresses to or from ID EEPROM. Added code for reading and writing Mac addresses to/from ID EEPROM(0x57). With attached patch, we can use command "mac/mac read/mac save/" to read and write EEPROM under u-boot prompt. U-boot will calculate the checksum of EEPROM while bootup, if it is right, then u-boot will check whether the mac address of eTSEC0/1/2/3 is availalbe (non-zero). If there is mac address availabe in EEPROM, u-boot will use it, otherewise, u-boot will use the mac address defined in MPC8641HPCN.h. This matches the requirement to set unique mac address for each TSEC port. Signed-off-by: Haiying Wang Signed-off-by: York Sun --- board/mpc8641hpcn/Makefile | 2 +- board/mpc8641hpcn/sys_eeprom.c | 244 +++++++++++++++++++++++++++++++++ common/Makefile | 2 +- common/cmd_mac.c | 66 +++++++++ include/common.h | 3 + include/configs/MPC8641HPCN.h | 2 + lib_ppc/board.c | 4 + 7 files changed, 321 insertions(+), 2 deletions(-) create mode 100644 board/mpc8641hpcn/sys_eeprom.c create mode 100644 common/cmd_mac.c diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 060db84ef..0ebed87bc 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o pixis.o oftree.o +OBJS := $(BOARD).o pixis.o sys_eeprom.o oftree.o SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c new file mode 100644 index 000000000..733a57f93 --- /dev/null +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -0,0 +1,244 @@ +/* + * Copyright 2006 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CFG_ID_EEPROM +typedef struct { + unsigned char id[4]; /* 0x0000 - 0x0003 */ + unsigned char sn[12]; /* 0x0004 - 0x000F */ + unsigned char errata[5];/* 0x0010 - 0x0014 */ + unsigned char date[7]; /* 0x0015 - 0x001a */ + unsigned char res_1[37];/* 0x001b - 0x003f */ + unsigned char tab_size; /* 0x0040 */ + unsigned char tab_flag; /* 0x0041 */ + unsigned char mac[8][6];/* 0x0042 - 0x0071 */ + unsigned char res_2[126];/* 0x0072 - 0x00ef */ + unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ +} EEPROM_data; + +static EEPROM_data mac_data; + +int mac_show(void) +{ + int i; + unsigned char ethaddr[8][18]; + + printf("ID %c%c%c%c\n", mac_data.id[0],\ + mac_data.id[1],\ + mac_data.id[2],\ + mac_data.id[3]); + printf("Errata %c%c%c%c%c\n", mac_data.errata[0],\ + mac_data.errata[1],\ + mac_data.errata[2],\ + mac_data.errata[3],\ + mac_data.errata[4]); + printf("Date %c%c%c%c%c%c%c\n", mac_data.date[0],\ + mac_data.date[1],\ + mac_data.date[2],\ + mac_data.date[3],\ + mac_data.date[4],\ + mac_data.date[5],\ + mac_data.date[6]); + for (i = 0; i < 8; i++) { + sprintf(ethaddr[i],"%02x:%02x:%02x:%02x:%02x:%02x",\ + mac_data.mac[i][0],\ + mac_data.mac[i][1],\ + mac_data.mac[i][2],\ + mac_data.mac[i][3],\ + mac_data.mac[i][4],\ + mac_data.mac[i][5]); + printf("MAC %d %s\n", i, ethaddr[i]); + } + + setenv("ethaddr", ethaddr[0]); + setenv("eth1addr", ethaddr[1]); + setenv("eth2addr", ethaddr[2]); + setenv("eth3addr", ethaddr[3]); + + return 0; +} + +int mac_read(void) +{ + int ret,length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR, *data; + + length = sizeof(EEPROM_data); + ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length); + if (ret) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + printf("Check CRC on reading ..."); + crc = crc32(crc, data, length-4); + if (crc != mac_data.crc) { + printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",mac_data.crc,crc); + return -1; + } + else { + printf("CRC OK\n"); + mac_show(); + } + return 0; +} + +int mac_prog(void) +{ + int ret, i, length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR,*ptr; + unsigned char * eeprom_data = (unsigned char *)(&mac_data); + + for (i = 0; i < sizeof(mac_data.res_1); i++) + mac_data.res_1[i] = 0; + for (i = 0;i < sizeof(mac_data.res_2); i++) + mac_data.res_2[i] = 0; + length = sizeof(EEPROM_data); + crc = crc32 (crc, eeprom_data, length-4); + mac_data.crc = crc; + for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { + ret = i2c_write(dev, i, 1, ptr, (length-i) <8 ? (length-i) : 8); + udelay(5000); /* 5ms write cycle timing */ + if (ret) + break; + } + if (ret) { + printf("Programming failed.\n"); + return -1; + } + else { + printf("Programming %d bytes. Reading back ...\n",length); + mac_read(); + } + return 0; +} + +int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + char cmd = 's'; + unsigned long long mac_val; + + if(i2c_probe(ID_EEPROM_ADDR) != 0) + return -1; + + if(argc>1) { + cmd = argv[1][0]; + switch (cmd) { + case 'r': /* display */ + mac_read(); + break; + case 's': /* save */ + mac_prog(); + break; + case 'i': /* id */ + for (i=0; i<4; i++) { + mac_data.id[i] = argv[2][i]; + } + break; + case 'n': /* serial number */ + for (i=0; i<12; i++) { + mac_data.sn[i] = argv[2][i]; + } + break; + case 'e': /* errata */ + for (i=0; i<5; i++) { + mac_data.errata[i] = argv[2][i]; + } + break; + case 'd': /* date */ + for (i=0; i<7; i++) { + mac_data.date[i] = argv[2][i]; + } + break; + case 'p': /* number of ports */ + mac_data.tab_size = (unsigned char)simple_strtoul(argv[2],NULL,16); + break; + case '0': /* mac 0 */ + case '1': /* mac 1 */ + case '2': /* mac 2 */ + case '3': /* mac 3 */ + case '4': /* mac 4 */ + case '5': /* mac 5 */ + case '6': /* mac 6 */ + case '7': /* mac 7 */ + mac_val = simple_strtoull(argv[2],NULL,16); + for (i=0; i<6; i++) { + mac_data.mac[cmd-'0'][i] = *((unsigned char *)(((unsigned int)(&mac_val))+i+2)); + } + break; + case 'h': /* help */ + default: + printf ("Usage:\n%s\n", cmdtp->usage); + break; + } + } + else { + mac_show(); + } + return 0; +} + +int mac_read_from_eeprom(void) +{ + int length,i; + unsigned char dev = ID_EEPROM_ADDR, *data, ethaddr[4][18], enetvar[32]; + unsigned int crc = 0; + + length = sizeof(EEPROM_data); + if(i2c_read (dev, 0, 1, (unsigned char *)(&mac_data), length)) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + crc = crc32(crc, data, length-4); + if (crc != mac_data.crc) { + return -1; + } + else { + for(i=0; i<4; i++) { + if(memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { + sprintf(ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", \ + mac_data.mac[i][0], \ + mac_data.mac[i][1], \ + mac_data.mac[i][2], \ + mac_data.mac[i][3], \ + mac_data.mac[i][4], \ + mac_data.mac[i][5]); + sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + setenv(enetvar, ethaddr[i]); + } + } + } + return 0; +} +#endif /* CFG_ID_EEPROM */ diff --git a/common/Makefile b/common/Makefile index eb0b5dadf..a62bc16e8 100644 --- a/common/Makefile +++ b/common/Makefile @@ -51,7 +51,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ memsize.o miiphybb.o miiphyutil.o \ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ usb.o usb_kbd.o usb_storage.o \ - virtex2.o xilinx.o crc16.o xyzModem.o + virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o OBJS = $(AOBJS) $(COBJS) diff --git a/common/cmd_mac.c b/common/cmd_mac.c new file mode 100644 index 000000000..0add43285 --- /dev/null +++ b/common/cmd_mac.c @@ -0,0 +1,66 @@ +/* + * Copyright 2006 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CFG_ID_EEPROM + +extern int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +U_BOOT_CMD( + mac, 3, 1, do_mac, + "mac - display and program the system ID and MAC addresses in EEPROM\n", + "[read|save|id|num|errata|date|ports|0|1|2|3|4|5|6|7]\n" + "read\n" + " - show content of mac\n" + "mac save\n" + " - save to the EEPROM\n" + "mac id\n" + " - program system id\n" + "mac num\n" + " - program system serial number\n" + "mac errata\n" + " - program errata data\n" + "mac date\n" + " - program data date\n" + "mac ports\n" + " - program the number of ports\n" + "mac 0\n" + " - program the MAC address for port 0\n" + "mac 1\n" + " - program the MAC address for port 1\n" + "mac 2\n" + " - program the MAC address for port 2\n" + "mac 3\n" + " - program the MAC address for port 3\n" + "mac 4\n" + " - program the MAC address for port 4\n" + "mac 5\n" + " - program the MAC address for port 5\n" + "mac 6\n" + " - program the MAC address for port 6\n" + "mac 7\n" + " - program the MAC address for port 7\n" +); +#endif /* CFG_ID_EEPROM */ diff --git a/include/common.h b/include/common.h index 83ccf7c98..7e54da93b 100644 --- a/include/common.h +++ b/include/common.h @@ -197,6 +197,9 @@ int checkdram (void); char * strmhz(char *buf, long hz); int last_stage_init(void); extern ulong monitor_flash_len; +#ifdef CFG_ID_EEPROM +int mac_read_from_eeprom(void); +#endif /* common/flash.c */ void flash_perror (int); diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aca2ecc23..7e91e644b 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -146,6 +146,8 @@ #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ #endif +#define CFG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 /* * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. diff --git a/lib_ppc/board.c b/lib_ppc/board.c index c367b3ef9..2c29f467e 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -862,6 +862,10 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif +#ifdef CFG_ID_EEPROM + mac_read_from_eeprom(); +#endif + #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \ defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) load_sernum_ethaddr (); From c86360b830f1eecd7a72208575dde4f57879faea Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Fri, 28 Jul 2006 00:01:34 +0800 Subject: [PATCH 038/101] Fixed OF device tree of mpc86xxhpcn board. The changes works in with kernel irq mapping rework. Signed-off-by: Zhang Wei --- board/mpc8641hpcn/oftree.dts | 136 +++++++++++++++++++---------------- 1 file changed, 75 insertions(+), 61 deletions(-) diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 32ba36747..e3f5efab4 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -205,99 +205,113 @@ clock-frequency = <1fca055>; interrupt-parent = <40000>; interrupts = <18 2>; - interrupt-map-mask = ; + interrupt-map-mask = ; interrupt-map = < /* IDSEL 0x11 */ - 8800 0 0 1 40000 3 0 - 8800 0 0 2 40000 4 0 - 8800 0 0 3 40000 5 0 - 8800 0 0 4 40000 6 0 + 8800 0 0 1 4d0 3 2 + 8800 0 0 2 4d0 4 2 + 8800 0 0 3 4d0 5 2 + 8800 0 0 4 4d0 6 2 /* IDSEL 0x12 */ - 9000 0 0 1 40000 4 0 - 9000 0 0 2 40000 5 0 - 9000 0 0 3 40000 6 0 - 9000 0 0 4 40000 3 0 + 9000 0 0 1 4d0 4 2 + 9000 0 0 2 4d0 5 2 + 9000 0 0 3 4d0 6 2 + 9000 0 0 4 4d0 3 2 /* IDSEL 0x13 */ - 9800 0 0 1 40000 0 0 - 9800 0 0 2 40000 0 0 - 9800 0 0 3 40000 0 0 - 9800 0 0 4 40000 0 0 + 9800 0 0 1 4d0 0 0 + 9800 0 0 2 4d0 0 0 + 9800 0 0 3 4d0 0 0 + 9800 0 0 4 4d0 0 0 /* IDSEL 0x14 */ - a000 0 0 1 40000 0 0 - a000 0 0 2 40000 0 0 - a000 0 0 3 40000 0 0 - a000 0 0 4 40000 0 0 + a000 0 0 1 4d0 0 0 + a000 0 0 2 4d0 0 0 + a000 0 0 3 4d0 0 0 + a000 0 0 4 4d0 0 0 /* IDSEL 0x15 */ - a800 0 0 1 40000 0 0 - a800 0 0 2 40000 0 0 - a800 0 0 3 40000 0 0 - a800 0 0 4 40000 0 0 + a800 0 0 1 4d0 0 0 + a800 0 0 2 4d0 0 0 + a800 0 0 3 4d0 0 0 + a800 0 0 4 4d0 0 0 /* IDSEL 0x16 */ - b000 0 0 1 40000 0 0 - b000 0 0 2 40000 0 0 - b000 0 0 3 40000 0 0 - b000 0 0 4 40000 0 0 + b000 0 0 1 4d0 0 0 + b000 0 0 2 4d0 0 0 + b000 0 0 3 4d0 0 0 + b000 0 0 4 4d0 0 0 /* IDSEL 0x17 */ - b800 0 0 1 40000 0 0 - b800 0 0 2 40000 0 0 - b800 0 0 3 40000 0 0 - b800 0 0 4 40000 0 0 + b800 0 0 1 4d0 0 0 + b800 0 0 2 4d0 0 0 + b800 0 0 3 4d0 0 0 + b800 0 0 4 4d0 0 0 /* IDSEL 0x18 */ - c000 0 0 1 40000 0 0 - c000 0 0 2 40000 0 0 - c000 0 0 3 40000 0 0 - c000 0 0 4 40000 0 0 + c000 0 0 1 4d0 0 0 + c000 0 0 2 4d0 0 0 + c000 0 0 3 4d0 0 0 + c000 0 0 4 4d0 0 0 /* IDSEL 0x19 */ - c800 0 0 1 40000 0 0 - c800 0 0 2 40000 0 0 - c800 0 0 3 40000 0 0 - c800 0 0 4 40000 0 0 + c800 0 0 1 4d0 0 0 + c800 0 0 2 4d0 0 0 + c800 0 0 3 4d0 0 0 + c800 0 0 4 4d0 0 0 /* IDSEL 0x1a */ - d000 0 0 1 40000 6 0 - d000 0 0 2 40000 3 0 - d000 0 0 3 40000 4 0 - d000 0 0 4 40000 5 0 + d000 0 0 1 4d0 6 2 + d000 0 0 2 4d0 3 2 + d000 0 0 3 4d0 4 2 + d000 0 0 4 4d0 5 2 /* IDSEL 0x1b */ - d800 0 0 1 40000 5 0 - d800 0 0 2 40000 0 0 - d800 0 0 3 40000 0 0 - d800 0 0 4 40000 0 0 + d800 0 0 1 4d0 5 2 + d800 0 0 2 4d0 0 0 + d800 0 0 3 4d0 0 0 + d800 0 0 4 4d0 0 0 /* IDSEL 0x1c */ - e000 0 0 1 40000 9 0 - e000 0 0 2 40000 a 0 - e000 0 0 3 40000 c 0 - e000 0 0 4 40000 7 0 + e000 0 0 1 4d0 9 2 + e000 0 0 2 4d0 a 2 + e000 0 0 3 4d0 c 2 + e000 0 0 4 4d0 7 2 /* IDSEL 0x1d */ - e800 0 0 1 40000 9 0 - e800 0 0 2 40000 a 0 - e800 0 0 3 40000 b 0 - e800 0 0 4 40000 0 0 + e800 0 0 1 4d0 9 2 + e800 0 0 2 4d0 a 2 + e800 0 0 3 4d0 b 2 + e800 0 0 4 4d0 0 0 /* IDSEL 0x1e */ - f000 0 0 1 40000 c 0 - f000 0 0 2 40000 0 0 - f000 0 0 3 40000 0 0 - f000 0 0 4 40000 0 0 + f000 0 0 1 4d0 c 2 + f000 0 0 2 4d0 0 0 + f000 0 0 3 4d0 0 0 + f000 0 0 4 4d0 0 0 /* IDSEL 0x1f */ - f800 0 0 1 40000 6 0 - f800 0 0 2 40000 0 0 - f800 0 0 3 40000 0 0 - f800 0 0 4 40000 0 0 + f800 0 0 1 4d0 6 2 + f800 0 0 2 4d0 0 0 + f800 0 0 3 4d0 0 0 + f800 0 0 4 4d0 0 0 >; + i8259@4d0 { + linux,phandle = <4d0>; + clock-frequency = <0>; + interrupt-controller; + device_type = "interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <2>; + built-in; + compatible = "chrp,iic"; + big-endian; + interrupts = <49 2>; + interrupt-parent = <40000>; + }; + }; pic@40000 { linux,phandle = <40000>; From 515ab8a62e8574e2babc6e8dcc43544ad221c5b2 Mon Sep 17 00:00:00 2001 From: John Traill Date: Fri, 28 Jul 2006 08:16:06 +0100 Subject: [PATCH 039/101] Fix 8641HPCN timebase --- include/configs/MPC8641HPCN.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7e91e644b..15e987139 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -268,7 +268,7 @@ #define OF_CPU "PowerPC,8641@0" #define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" #define CFG_64BIT_VSPRINTF 1 From 492900b985439fbce1a118afde1e35def870db03 Mon Sep 17 00:00:00 2001 From: John Traill Date: Fri, 28 Jul 2006 09:03:54 +0100 Subject: [PATCH 040/101] Fix 8641HPCN pollution --- cpu/mpc86xx/speed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 6775a1143..8088b870a 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -30,6 +30,7 @@ #include +#ifdef MPC8641HPCN /* * get_board_sys_clk * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ @@ -93,6 +94,7 @@ unsigned long get_board_sys_clk(ulong dummy) return val; } +#endif void get_sys_info (sys_info_t *sysInfo) { From 239db37c94f7a92941c4465feceb867c609241c5 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 28 Jul 2006 12:41:18 -0400 Subject: [PATCH 041/101] Move get_board_sys_clk to board directory --- board/mpc8641hpcn/mpc8641hpcn.c | 64 ++++++++++++++++++++++++++++++++ cpu/mpc86xx/speed.c | 66 --------------------------------- 2 files changed, 64 insertions(+), 66 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 2626cccb9..5023c1c97 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -359,3 +359,67 @@ my_usage: puts("For example: reset cf 40 2.5 10\n"); puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } + +/* + * get_board_sys_clk + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ + +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i, go_bit, rd_clks; + ulong val = 0; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} + diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 8088b870a..e13070537 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -30,72 +30,6 @@ #include -#ifdef MPC8641HPCN -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val = 0; - - go_bit = in8(PIXIS_BASE + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in8(PIXIS_BASE + PIXIS_AUX); - else - i = in8(PIXIS_BASE + PIXIS_SPD); - } else { - i = in8(PIXIS_BASE + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; -} - -#endif - void get_sys_info (sys_info_t *sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; From 9cb3e8816ae4d854e7dc22128c3eea3d70bb982c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 28 Jul 2006 12:41:41 -0400 Subject: [PATCH 042/101] Change the space size of PEX IO in README --- doc/README.mpc8641hpcn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn index 907a911ed..8ea0b1e9e 100644 --- a/doc/README.mpc8641hpcn +++ b/doc/README.mpc8641hpcn @@ -117,7 +117,7 @@ To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): 0xf800_0000 0xf80f_ffff CCSR 1M 0xf810_0000 0xf81f_ffff PIXIS 1M 0xf840_0000 0xf840_3fff Stack space 32K - 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 512M - 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 512M + 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M + 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M 0xfe00_0000 0xfeff_ffff Flash(alternate)16M 0xff00_0000 0xffff_ffff Flash(boot bank)16M From 71748af833ca1017edf1415be376366ff2937d17 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 28 Jul 2006 12:41:35 -0400 Subject: [PATCH 043/101] Correct the irq value of DUART2 --- board/mpc8641hpcn/oftree.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index e3f5efab4..742a1404f 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -187,7 +187,7 @@ compatible = "ns16550"; reg = <4600 100>; clock-frequency = <0>; - interrupts = <2a 2>; + interrupts = <1c 2>; interrupt-parent = <40000>; }; From 709d3073e74153278e7904a70819bbef7df50e1a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 3 Aug 2006 16:17:56 -0500 Subject: [PATCH 044/101] Convert to mac-address in ethernet nodes. --- cpu/mpc86xx/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index fc77d9949..0e82e74fa 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -276,22 +276,22 @@ void ft_cpu_setup(void *blob, bd_t *bd) *p = cpu_to_be32(clock); #if defined(CONFIG_MPC86XX_TSEC1) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); memcpy(p, bd->bi_enetaddr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC2) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); memcpy(p, bd->bi_enet1addr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC3) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); memcpy(p, bd->bi_enet2addr, 6); #endif #if defined(CONFIG_MPC86XX_TSEC4) - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); memcpy(p, bd->bi_enet3addr, 6); #endif From 91a414c7d1fb0eac912592cd995b30c9f23045c9 Mon Sep 17 00:00:00 2001 From: John Traill Date: Tue, 8 Aug 2006 11:32:43 +0100 Subject: [PATCH 045/101] Fix caslat calculation Signed-off-by: John Traill --- cpu/mpc86xx/spd_sdram.c | 135 ++++++++++++---------------------------- 1 file changed, 39 insertions(+), 96 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index f30bbbd7e..a4b9d54c7 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -44,7 +44,7 @@ extern int dma_xfer(void *dest, uint count, void *src); /* * Only one of the following three should be 1; others should be 0 * By default the cache line interleaving is selected if - * the CONFIG_DDR_INTERLEAVE flag is defined in MPC8641HPCN.h + * the CONFIG_DDR_INTERLEAVE flag is defined */ #define CFG_PAGE_INTERLEAVING 0 #define CFG_BANK_INTERLEAVING 0 @@ -137,8 +137,8 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) 800, 900, 250, - 330, /* FIXME: Is 333 better/valid? */ - 660, /* FIXME: Is 667 better/valid? */ + 330, + 660, 750, 0, /* undefined */ 0 /* undefined */ @@ -167,7 +167,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, unsigned int dqs_cfg; unsigned char twr_clk, twtr_clk, twr_auto_clk; unsigned int tCKmin_ps, tCKmax_ps; - unsigned int max_data_rate, effective_data_rate; + unsigned int max_data_rate; unsigned int busfreq; unsigned sdram_cfg_1; unsigned int memsize; @@ -187,6 +187,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, unsigned char d_init; unsigned int law_size; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + unsigned int tCycle_ps, modfreq; if (ddr_num == 1) ddr = &immap->im_ddr1; @@ -288,7 +289,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, } #ifdef CONFIG_DDR_INTERLEAVE -#ifdef CONFIG_MPC8641HPCN + if (dimm_num != 1) { printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num); return 0; @@ -340,8 +341,6 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, rank_density /= 2; } } -#endif /* CONFIG_MPC8641HPCN */ - #else /* CONFIG_DDR_INTERLEAVE */ if (dimm_num == 1) { @@ -468,81 +467,42 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, */ busfreq = get_bus_freq(0) / 1000000; /* MHz */ - effective_data_rate = max_data_rate; - if (busfreq < 90) { - /* DDR rate out-of-range */ - puts("DDR: platform frequency is not fit for DDR rate\n"); + if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) { + printf("DDR: platform frequency too low for correct DDR2 controller operation\n"); return 0; - - } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) { - /* - * busfreq 90~230 range, treated as DDR 200. - */ - effective_data_rate = 200; - if (spd.clk_cycle3 == 0xa0) /* 10 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0xa0) - caslat--; - - } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) { - /* - * busfreq 230~280 range, treated as DDR 266. - */ - effective_data_rate = 266; - if (spd.clk_cycle3 == 0x75) /* 7.5 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x75) - caslat--; - - } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) { - /* - * busfreq 280~350 range, treated as DDR 333. - */ - effective_data_rate = 333; - if (spd.clk_cycle3 == 0x60) /* 6.0 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x60) - caslat--; - - } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) { - /* - * busfreq 350~460 range, treated as DDR 400. - */ - effective_data_rate = 400; - if (spd.clk_cycle3 == 0x50) /* 5.0 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x50) - caslat--; - - } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) { - /* - * busfreq 460~560 range, treated as DDR 533. - */ - effective_data_rate = 533; - if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x3D) - caslat--; - - } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) { - /* - * busfreq 560~700 range, treated as DDR 667. - */ - effective_data_rate = 667; - if (spd.clk_cycle3 == 0x30) /* 3.0 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x30) - caslat--; - - } else if (700 <= busfreq) { - /* - * DDR rate out-of-range - */ - printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", - busfreq, max_data_rate); + } else if (busfreq < 90) { + printf("DDR: platform frequency too low for correct DDR1 operation\n"); return 0; } + if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) { + caslat -= 2; + } else { + tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2); + modfreq = 2 * 1000 * 1000 / tCycle_ps; + if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1)))) + caslat -= 1; + else if (busfreq > max_data_rate) { + printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", + busfreq, max_data_rate); + return 0; + } + } + + /* + * Empirically set ~MCAS-to-preamble override for DDR 2. + * Your milage will vary. + */ + cpo = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (busfreq <= 333) { + cpo = 0x7; + } else if (busfreq <= 400) { + cpo = 0x9; + } else { + cpo = 0xa; + } + } /* * Convert caslat clocks to DDR controller value. @@ -554,7 +514,6 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, caslat_ctrl = (2 * caslat - 1) & 0x0f; } - debug("DDR: effective data rate is %d MHz\n", effective_data_rate); debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", caslat, caslat_ctrl); @@ -676,7 +635,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, && (odt_wr_cfg || odt_rd_cfg) && (caslat < 4)) { add_lat = 4 - caslat; - if (add_lat > trcd_clk) { + if (add_lat >= trcd_clk) { add_lat = trcd_clk - 1; } } @@ -717,22 +676,6 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, four_act = picos_to_clk(37500); /* By the book. 1k pages? */ } - /* - * Empirically set ~MCAS-to-preamble override for DDR 2. - * Your milage will vary. - */ - cpo = 0; - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - if (effective_data_rate == 266 || effective_data_rate == 333) { - cpo = 0x7; /* READ_LAT + 5/4 */ - } else if (effective_data_rate == 400) { - cpo = 0x9; /* READ_LAT + 7/4 */ - } else { - /* Pure speculation */ - cpo = 0xb; - } - } - ddr->timing_cfg_2 = (0 | ((add_lat & 0x7) << 28) /* ADD_LAT */ | ((cpo & 0x1f) << 23) /* CPO */ From 8fc8bd2cc479b6cd188fdede4010e0e052970b8a Mon Sep 17 00:00:00 2001 From: John Traill Date: Wed, 9 Aug 2006 14:33:50 +0100 Subject: [PATCH 046/101] Add Rapidio support for the MPC8641HPCN Signed-off-by: John Traill --- board/mpc8641hpcn/init.S | 12 +++++++++++ board/mpc8641hpcn/oftree.dts | 42 ++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 69954a81a..c6ea55ea7 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -84,6 +84,9 @@ #define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) #endif +#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + .section .bootpg, "ax" .globl law_entry law_entry: @@ -164,5 +167,14 @@ law_entry: ori r6,r6,LAWAR8@l stwu r6, 0x20(r5) + /* LAWBAR9, LAWAR9 */ + lis r6,LAWBAR9@h + ori r6,r6,LAWBAR9@l + stwu r6, 0x20(r4) + + lis r6,LAWAR9@h + ori r6,r6,LAWAR9@l + stwu r6, 0x20(r5) + blr diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 742a1404f..99d75ca62 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -341,6 +341,48 @@ >; interrupt-parent = <40000>; }; + rio@c0000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "rio"; + model = "pq38"; + compatible = "85xx"; + ranges = <0 c0000000 20000000>; + reg = ; + linux,phandle = ; + }; + rio_message@d3000 { + device_type = "network"; + compatible = "85xx"; + linux,phandle = ; + reg = ; + interrupts = <35 2 36 2>; + interrupt-parent = <40000>; + }; + rio_message@d3100 { + device_type = "network"; + compatible = "85xx"; + linux,phandle = ; + reg = ; + interrupts = <37 2 38 2>; + interrupt-parent = <40000>; + }; + rio_doorbell@d3400 { + device_type = "doorbell"; + compatible = "85xx"; + linux,phandle = ; + reg = ; + interrupts = <31 2 32 2>; + interrupt-parent = <40000>; + }; + rio_portwrite@d34e0 { + device_type = "portwrite"; + compatible = "85xx"; + linux,phandle = ; + reg = ; + interrupts = <30 2>; + interrupt-parent = <40000>; + }; }; }; From 0267768eddc5ca7bc1865bc40c866829ac5efbfe Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:41:37 -0500 Subject: [PATCH 047/101] * Modify bootm command to support booting with flat device trees Patch by Matthew McClintock 26-June-2006 --- README | 54 ++++++++++++++++++++++++++++++++++++++++++++++ common/cmd_bootm.c | 40 ++++++++++++++++++++++------------ 2 files changed, 80 insertions(+), 14 deletions(-) diff --git a/README b/README index 5ed30f27c..0fda03f3c 100644 --- a/README +++ b/README @@ -447,6 +447,11 @@ The following options need to be configured: Board code has addition modification that it wants to make to the flat device tree before handing it off to the kernel + CONFIG_OF_BOOT_CPU + + This define fills in the correct boot cpu in the boot + param header, the default value is zero if undefined. + - Serial Ports: CFG_PL010_SERIAL @@ -3013,6 +3018,55 @@ format!) to the "bootm" command: bash# +Boot Linux and pass a flat device tree: +----------- + +First, U-Boot must be compiled with the appropriate defines. See the section +titled "Linux Kernel Interface" above for a more in depth explanation. The +following is an example of how to start a kernel and pass an updated +flat device tree: + +=> print oftaddr +oftaddr=0x300000 +=> print oft +oft=oftrees/mpc8540ads.dtb +=> tftp $oftaddr $oft +Speed: 1000, full duplex +Using TSEC0 device +TFTP from server 192.168.1.1; our IP address is 192.168.1.101 +Filename 'oftrees/mpc8540ads.dtb'. +Load address: 0x300000 +Loading: # +done +Bytes transferred = 4106 (100a hex) +=> tftp $loadaddr $bootfile +Speed: 1000, full duplex +Using TSEC0 device +TFTP from server 192.168.1.1; our IP address is 192.168.1.2 +Filename 'uImage'. +Load address: 0x200000 +Loading:############ +done +Bytes transferred = 1029407 (fb51f hex) +=> print loadaddr +loadaddr=200000 +=> print oftaddr +oftaddr=0x300000 +=> bootm $loadaddr - $oftaddr +## Booting image at 00200000 ... + Image Name: Linux-2.6.17-dirty + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 1029343 Bytes = 1005.2 kB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Booting using flat device tree at 0x300000 +Using MPC85xx ADS machine description +Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb +[snip] + + More About U-Boot Image Types: ------------------------------ diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index fdf7180a1..a472a1d7b 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -465,6 +465,13 @@ U_BOOT_CMD( "[addr [arg ...]]\n - boot application image stored in memory\n" "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n" "\t'arg' can be the address of an initrd image\n" +#ifdef CONFIG_OF_FLAT_TREE + "\tWhen booting a Linux kernel which requires a flat device-tree\n" + "\ta third argument is required which is the address of the of the\n" + "\tdevice-tree blob. To boot that kernel without an initrd image,\n" + "\tuse a '-' for the second argument. If you do not pass a third\n" + "\ta bd_info struct will be passed instead\n" +#endif ); #ifdef CONFIG_SILENT_CONSOLE @@ -500,11 +507,6 @@ fixup_silent_linux () } #endif /* CONFIG_SILENT_CONSOLE */ -#ifdef CONFIG_OF_FLAT_TREE -extern const unsigned char oftree_dtb[]; -extern const unsigned int oftree_dtb_len; -#endif - #ifdef CONFIG_PPC static void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, @@ -616,7 +618,17 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, /* * Check if there is an initrd image */ + +#ifdef CONFIG_OF_FLAT_TREE + /* Look for a '-' which indicates to ignore the ramdisk argument */ + if (argc >= 3 && strcmp(argv[2], "-") == 0) { + debug ("Skipping initrd\n"); + data = 0; + } + else +#endif if (argc >= 3) { + debug ("Not skipping initrd\n"); SHOW_BOOT_PROGRESS (9); addr = simple_strtoul(argv[2], NULL, 16); @@ -724,6 +736,15 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, len = data = 0; } +#ifdef CONFIG_OF_FLAT_TREE + if (argc >= 3) + { + of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16); + printf ("Booting using flat device tree at 0x%x\n", + of_flat_tree); + } +#endif + if (!data) { debug ("No initrd\n"); } @@ -793,15 +814,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_end = 0; } -#ifdef CONFIG_OF_FLAT_TREE - if (initrd_start == 0) - of_flat_tree = (char *)(((ulong)kbd - OF_FLAT_TREE_MAX_SIZE - - sizeof(bd_t)) & ~0xF); - else - of_flat_tree = (char *)((initrd_start - OF_FLAT_TREE_MAX_SIZE - - sizeof(bd_t)) & ~0xF); -#endif - debug ("## Transferring control to Linux (at address %08lx) ...\n", (ulong)kernel); From 5498d90312aad9f6bdbf047986027c35b03cd163 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:42:24 -0500 Subject: [PATCH 048/101] * Patch to modify ft_build.c to update flat device trees in place Patch by Matthew McClintock 26-June-2006 --- common/cmd_bootm.c | 2 +- common/ft_build.c | 343 ++++++++++++++------------------------------- include/ft_build.h | 19 +-- 3 files changed, 116 insertions(+), 248 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index a472a1d7b..f1c0eb4d1 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -836,7 +836,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); #else - ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end); + ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) diff --git a/common/ft_build.c b/common/ft_build.c index 9e9c906fc..b5a997c1b 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -1,5 +1,22 @@ /* * OF flat tree builder + * Written by: Pantelis Antoniou + * Updated by: Matthew McClintock + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #include @@ -13,44 +30,39 @@ #include +#undef DEBUG + /* align addr on a size boundary - adjust address up if needed -- Cort */ #define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1))) +#ifndef CONFIG_OF_BOOT_CPU +#define CONFIG_OF_BOOT_CPU 0 +#endif +#define SIZE_OF_RSVMAP_ENTRY (2*sizeof(u64)) static void ft_put_word(struct ft_cxt *cxt, u32 v) { - if (cxt->overflow) /* do nothing */ - return; - - /* check for overflow */ - if (cxt->p + 4 > cxt->pstr) { - cxt->overflow = 1; - return; - } + memmove(cxt->p + sizeof(u32), cxt->p, cxt->p_end - cxt->p); *(u32 *) cxt->p = cpu_to_be32(v); - cxt->p += 4; + cxt->p += sizeof(u32); + cxt->p_end += sizeof(u32); } static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz) { - u8 *p; + int aligned_size = ((u8 *)_ALIGN((unsigned long)cxt->p + sz, + sizeof(u32))) - cxt->p; - if (cxt->overflow) /* do nothing */ - return; + memmove(cxt->p + aligned_size, cxt->p, cxt->p_end - cxt->p); - /* next pointer pos */ - p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4); - - /* check for overflow */ - if (p > cxt->pstr) { - cxt->overflow = 1; - return; - } + /* make sure the last bytes are zeroed */ + memset(cxt->p + aligned_size - (aligned_size % sizeof(u32)), 0, + (aligned_size % sizeof(u32))); memcpy(cxt->p, data, sz); - if ((sz & 3) != 0) - memset(cxt->p + sz, 0, 4 - (sz & 3)); - cxt->p = p; + + cxt->p += aligned_size; + cxt->p_end += aligned_size; } void ft_begin_node(struct ft_cxt *cxt, const char *name) @@ -73,10 +85,10 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) { u8 *p; - p = cxt->pstr; - while (p < cxt->pstr_begin) { + p = cxt->p; + while (p < cxt->p_end) { if (strcmp(p, name) == 0) - return p - cxt->p_begin; + return p - cxt->p; p += strlen(p) + 1; } @@ -85,24 +97,13 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz) { - int len, off; - - if (cxt->overflow) - return; - - len = strlen(name) + 1; + int off = 0; off = lookup_string(cxt, name); if (off == -1) { - /* check if we have space */ - if (cxt->p + 12 + sz + len > cxt->pstr) { - cxt->overflow = 1; - return; - } - - cxt->pstr -= len; - memcpy(cxt->pstr, name, len); - off = cxt->pstr - cxt->p_begin; + memcpy(cxt->p_end, name, strlen(name) + 1); + off = cxt->p_end - cxt->p; + cxt->p_end += strlen(name) + 2; } /* now put offset from beginning of *STRUCTURE* */ @@ -122,137 +123,62 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val) { u32 v = cpu_to_be32((u32) val); - ft_prop(cxt, name, &v, 4); + ft_prop(cxt, name, &v, sizeof(u32)); } -/* start construction of the flat OF tree */ -void ft_begin(struct ft_cxt *cxt, void *blob, int max_size) +/* pick up and start working on a tree in place */ +void ft_init_cxt(struct ft_cxt *cxt, void *blob) { struct boot_param_header *bph = blob; - u32 off; - /* clear the cxt */ memset(cxt, 0, sizeof(*cxt)); cxt->bph = bph; - cxt->max_size = max_size; + bph->boot_cpuid_phys = CONFIG_OF_BOOT_CPU; - /* zero everything in the header area */ - memset(bph, 0, sizeof(*bph)); + /* find beginning and end of reserve map table (zeros in last entry) */ + cxt->p_rsvmap = (u8 *)bph + bph->off_mem_rsvmap; + while ( ((uint64_t *)cxt->p_rsvmap)[0] != 0 && + ((uint64_t *)cxt->p_rsvmap)[1] != 0 ) { + cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; + } - bph->magic = cpu_to_be32(OF_DT_HEADER); - bph->version = cpu_to_be32(0x10); - bph->last_comp_version = cpu_to_be32(0x10); - - /* start pointers */ - cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8); - cxt->pres = cxt->pres_begin; - - off = (unsigned long)cxt->pres_begin - (unsigned long)bph; - bph->off_mem_rsvmap = cpu_to_be32(off); - - ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = 0; - - cxt->p_anchor = cxt->pres + 16; /* over the terminator */ + cxt->p_start = (char*)bph + bph->off_dt_struct; + cxt->p_end = (char *)bph + bph->totalsize; + cxt->p = (char *)bph + bph->off_dt_strings; } /* add a reserver physical area to the rsvmap */ -void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size) +void ft_add_rsvmap(struct ft_cxt *cxt, u64 physstart, u64 physend) { - ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = cpu_to_be64(size); + memmove(cxt->p_rsvmap + SIZE_OF_RSVMAP_ENTRY, cxt->p_rsvmap, + cxt->p_end - cxt->p_rsvmap); - cxt->pres += 16; /* advance */ + ((u64 *)cxt->p_rsvmap)[0] = cpu_to_be64(physstart); + ((u64 *)cxt->p_rsvmap)[1] = cpu_to_be64(physend); + ((u64 *)cxt->p_rsvmap)[2] = 0; + ((u64 *)cxt->p_rsvmap)[3] = 0; - ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ - ((u64 *) cxt->pres)[1] = 0; - - /* keep track of size */ - cxt->res_size = cxt->pres + 16 - cxt->pres_begin; - - cxt->p_anchor = cxt->pres + 16; /* over the terminator */ + cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; + cxt->p_start += SIZE_OF_RSVMAP_ENTRY; + cxt->p += SIZE_OF_RSVMAP_ENTRY; + cxt->p_end += SIZE_OF_RSVMAP_ENTRY; } -void ft_begin_tree(struct ft_cxt *cxt) +void ft_end_tree(struct ft_cxt *cxt) { - cxt->p_begin = cxt->p_anchor; - cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */ - - cxt->p = cxt->p_begin; - cxt->pstr = cxt->pstr_begin; -} - -int ft_end_tree(struct ft_cxt *cxt) -{ - struct boot_param_header *bph = cxt->bph; - int off, sz, sz1; - u32 tag, v; - u8 *p; - ft_put_word(cxt, OF_DT_END); - - if (cxt->overflow) - return -ENOMEM; - - /* size of the areas */ - cxt->struct_size = cxt->p - cxt->p_begin; - cxt->strings_size = cxt->pstr_begin - cxt->pstr; - - /* the offset we must move */ - off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size; - - /* the new strings start */ - cxt->pstr_begin = cxt->p_begin + cxt->struct_size; - - /* move the whole string area */ - memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size); - - /* now perform the fixup of the strings */ - p = cxt->p_begin; - while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) { - p += 4; - - if (tag == OF_DT_BEGIN_NODE) { - p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4); - continue; - } - - if (tag == OF_DT_END_NODE || tag == OF_DT_NOP) - continue; - - if (tag != OF_DT_PROP) - return -EINVAL; - - sz = be32_to_cpu(*(u32 *) p); - p += 4; - - v = be32_to_cpu(*(u32 *) p); - v -= off; - *(u32 *) p = cpu_to_be32(v); /* move down */ - p += 4; - - p = (u8 *) _ALIGN((unsigned long)p + sz, 4); - } - - /* fix sizes */ - p = (char *)cxt->bph; - sz = (cxt->pstr_begin + cxt->strings_size) - p; - sz1 = _ALIGN(sz, 16); /* align at 16 bytes */ - if (sz != sz1) - memset(p + sz, 0, sz1 - sz); - bph->totalsize = cpu_to_be32(sz1); - bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p); - bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p); - - /* the new strings start */ - cxt->pstr_begin = cxt->p_begin + cxt->struct_size; - cxt->pstr = cxt->pstr_begin + cxt->strings_size; - - return 0; } -/**********************************************************************/ +/* update the boot param header with correct values */ +void ft_finalize_tree(struct ft_cxt *cxt) { + struct boot_param_header *bph = cxt->bph; + + bph->totalsize = cxt->p_end - (u8 *)bph; + bph->off_dt_struct = cxt->p_start - (u8 *)bph; + bph->off_dt_strings = cxt->p - (u8 *)bph; + bph->dt_strings_size = cxt->p_end - cxt->p; +} static inline int isprint(int c) { @@ -299,16 +225,16 @@ static void print_data(const void *data, int len) switch (len) { case 1: /* byte */ - printf(" = <0x%02x>", (*(u8 *) data) & 0xff); + printf(" = <%02x>", (*(u8 *) data) & 0xff); break; case 2: /* half-word */ - printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); + printf(" = <%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); break; case 4: /* word */ - printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); + printf(" = <%x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); break; case 8: /* double-word */ - printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data)); + printf(" = <%qx>", be64_to_cpu(*(uint64_t *) data)); break; default: /* anything else... hexdump */ printf(" = ["); @@ -350,7 +276,7 @@ void ft_dump_blob(const void *bphp) if (addr == 0 && size == 0) break; - printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size); + printf("/memreserve/ %qx %qx;\n", addr, size); } p = p_struct; @@ -381,8 +307,8 @@ void ft_dump_blob(const void *bphp) } if (tag != OF_DT_PROP) { - fprintf(stderr, "%*s ** Unknown tag 0x%08x\n", - depth * shift, "", tag); + fprintf(stderr, "%*s ** Unknown tag 0x%08x at 0x%x\n", + depth * shift, "", tag, --p); break; } sz = be32_to_cpu(*p++); @@ -397,64 +323,15 @@ void ft_dump_blob(const void *bphp) void ft_backtrack_node(struct ft_cxt *cxt) { - if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) - return; /* XXX only for node */ + int i = 4; - cxt->p -= 4; -} + while (be32_to_cpu(*(u32 *) (cxt->p - i)) != OF_DT_END_NODE) + i += 4; -/* note that the root node of the blob is "peeled" off */ -void ft_merge_blob(struct ft_cxt *cxt, void *blob) -{ - struct boot_param_header *bph = (struct boot_param_header *)blob; - u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct)); - u32 *p_strings = - (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings)); - u32 tag, *p; - char *s, *t; - int depth, sz; + memmove (cxt->p - i, cxt->p, cxt->p_end - cxt->p); - if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) - return; /* XXX only for node */ - - cxt->p -= 4; - - depth = 0; - p = p_struct; - while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { - - /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */ - - if (tag == OF_DT_BEGIN_NODE) { - s = (char *)p; - p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4); - - if (depth++ > 0) - ft_begin_node(cxt, s); - - continue; - } - - if (tag == OF_DT_END_NODE) { - ft_end_node(cxt); - if (--depth == 0) - break; - continue; - } - - if (tag == OF_DT_NOP) - continue; - - if (tag != OF_DT_PROP) - break; - - sz = be32_to_cpu(*p++); - s = (char *)p_strings + be32_to_cpu(*p++); - t = (char *)p; - p = (u32 *) _ALIGN((unsigned long)p + sz, 4); - - ft_prop(cxt, s, t, sz); - } + cxt->p_end -= i; + cxt->p -= i; } void *ft_get_prop(void *bphp, const char *propname, int *szp) @@ -521,9 +398,6 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp) /********************************************************************/ -extern unsigned char oftree_dtb[]; -extern unsigned int oftree_dtb_len; - /* Function that returns a character from the environment */ extern uchar(*env_get_char) (int); @@ -577,7 +451,7 @@ static const struct { }; #endif -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end) +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end) { u32 *p; int len; @@ -600,20 +474,16 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ return; } - ft_begin(&cxt, blob, size); +#ifdef DEBUG + printf ("recieved oftree\n"); + ft_dump_blob(blob); +#endif + + ft_init_cxt(&cxt, blob); if (initrd_start && initrd_end) ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1); - ft_begin_tree(&cxt); - - ft_begin_node(&cxt, ""); - - ft_end_node(&cxt); - - /* copy RO tree */ - ft_merge_blob(&cxt, oftree_dtb); - /* back into root */ ft_backtrack_node(&cxt); @@ -642,8 +512,8 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ #endif ft_begin_node(&cxt, "chosen"); - ft_prop_str(&cxt, "name", "chosen"); + ft_prop_str(&cxt, "bootargs", getenv("bootargs")); ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */ if (initrd_start && initrd_end) { @@ -659,11 +529,7 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ ft_end_node(&cxt); /* end root */ ft_end_tree(&cxt); - - /* - printf("merged OF-tree\n"); - ft_dump_blob(blob); - */ + ft_finalize_tree(&cxt); #ifdef CONFIG_OF_HAS_BD_T /* paste the bd_t at the end of the flat tree */ @@ -712,11 +578,12 @@ void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_ ft_board_setup(blob, bd); #endif - /* - printf("final OF-tree\n"); - ft_dump_blob(blob); - */ - -} + /* in case the size changed in the platform code */ + ft_finalize_tree(&cxt); +#ifdef DEBUG + printf("final OF-tree\n"); + ft_dump_blob(blob); +#endif +} #endif diff --git a/include/ft_build.h b/include/ft_build.h index 47ca575d9..f5156879d 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -36,19 +36,18 @@ struct boot_param_header { struct ft_cxt { struct boot_param_header *bph; - int max_size; /* maximum size of tree */ - int overflow; /* set when this happens */ - u8 *p, *pstr, *pres; /* running pointers */ - u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */ - u8 *p_anchor; /* start of constructed area */ - int struct_size, strings_size, res_size; + u8 *p_rsvmap; + u8 *p_start; /* pointer to beginning of dt_struct */ + u8 *p_end; /* pointer to end of dt_strings */ + u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */ }; void ft_begin_node(struct ft_cxt *cxt, const char *name); +void ft_init_cxt(struct ft_cxt *cxt, void *blob); void ft_end_node(struct ft_cxt *cxt); -void ft_begin_tree(struct ft_cxt *cxt); -int ft_end_tree(struct ft_cxt *cxt); +void ft_end_tree(struct ft_cxt *cxt); +void ft_finalize_tree(struct ft_cxt *cxt); void ft_nop(struct ft_cxt *cxt); void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz); @@ -57,12 +56,14 @@ void ft_prop_int(struct ft_cxt *cxt, const char *name, int val); void ft_begin(struct ft_cxt *cxt, void *blob, int max_size); void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size); -void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end); +void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end); void ft_dump_blob(const void *bphp); void ft_merge_blob(struct ft_cxt *cxt, void *blob); void *ft_get_prop(void *bphp, const char *propname, int *szp); +#ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +#endif #endif From 855e6fb073f9d04fe4a7f06c107ecbac6344ddd4 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:43:00 -0500 Subject: [PATCH 049/101] * Removed the oftree.dts for stxxtx in light of the changes to the flat device tree handling code Patch by Matthew McClintock 26-June-2006 --- board/stxxtc/Makefile | 10 +------- board/stxxtc/oftree.dts | 52 ----------------------------------------- 2 files changed, 1 insertion(+), 61 deletions(-) delete mode 100644 board/stxxtc/oftree.dts diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile index 11065cfd2..8c529a061 100644 --- a/board/stxxtc/Makefile +++ b/board/stxxtc/Makefile @@ -25,19 +25,11 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o oftree.o +OBJS = $(BOARD).o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) -%.dtb: %.dts - dtc -f -V 0x10 -I dts -O dtb $< >$@ - -%.c: %.dtb - xxd -i $< \ - | sed -e "s/^unsigned char/const unsigned char/g" \ - | sed -e "s/^unsigned int/const unsigned int/g" > $@ - ######################################################################### .depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) diff --git a/board/stxxtc/oftree.dts b/board/stxxtc/oftree.dts deleted file mode 100644 index e3f301794..000000000 --- a/board/stxxtc/oftree.dts +++ /dev/null @@ -1,52 +0,0 @@ -/ { - model = "STXXTC V1"; - compatible = "STXXTC"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - linux,phandle = <1>; - #address-cells = <1>; - #size-cells = <0>; - PowerPC,MPC870@0 { - linux,phandle = <3>; - name = "PowerPC,MPC870"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <0>; /* place-holder for runtime fillup */ - timebase-frequency = <0>; /* dido */ - linux,boot-cpu; - i-cache-size = <2000>; - d-cache-size = <2000>; - 32-bit; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <00000000 00000000 00000000 20000000>; - }; - - /* copy of the bd_t information (place-holders) */ - bd_t { - memstart = <0>; - memsize = <0>; - flashstart = <0>; - flashsize = <0>; - flashoffset = <0>; - sramstart = <0>; - sramsize = <0>; - - immr_base = <0>; - - bootflags = <0>; - ip_addr = <0>; - enetaddr = [ 00 00 00 00 00 00 ]; - ethspeed = <0>; - intfreq = <0>; - busfreq = <0>; - - baudrate = <0>; - }; - -}; From 0e16387db1d4aacd5bf35cb6d7c1942765c0347b Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:43:36 -0500 Subject: [PATCH 050/101] * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger --- board/cds/common/ft_board.c | 46 ++++++++++++++++++++++++++++++++ board/cds/mpc8541cds/Makefile | 3 ++- board/cds/mpc8548cds/Makefile | 3 ++- board/cds/mpc8555cds/Makefile | 3 ++- board/mpc8540ads/mpc8540ads.c | 24 +++++++++++++++++ board/mpc8560ads/mpc8560ads.c | 9 +++++++ cpu/mpc85xx/cpu.c | 50 ++++++++++++++++++++++++++++++++++- cpu/mpc85xx/cpu_init.c | 1 + include/configs/MPC8540ADS.h | 15 +++++++++++ include/configs/MPC8541CDS.h | 12 +++++++++ include/configs/MPC8548CDS.h | 12 +++++++++ include/configs/MPC8555CDS.h | 12 +++++++++ include/configs/MPC8560ADS.h | 12 +++++++++ 13 files changed, 198 insertions(+), 4 deletions(-) create mode 100644 board/cds/common/ft_board.c diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c new file mode 100644 index 000000000..73eca5e69 --- /dev/null +++ b/board/cds/common/ft_board.c @@ -0,0 +1,46 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile index 0d4abbd71..aea61360a 100644 --- a/board/cds/mpc8541cds/Makefile +++ b/board/cds/mpc8541cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile index 0d4abbd71..aea61360a 100644 --- a/board/cds/mpc8548cds/Makefile +++ b/board/cds/mpc8548cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile index 0d4abbd71..aea61360a 100644 --- a/board/cds/mpc8555cds/Makefile +++ b/board/cds/mpc8555cds/Makefile @@ -28,7 +28,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ - ../common/eeprom.o + ../common/eeprom.o \ + ../common/ft_board.o SOBJS := init.o diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index d0eb6904a..855888d27 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -31,6 +31,12 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -342,3 +348,21 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 25f69a0bf..f9d75e805 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -544,3 +544,12 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index f7fe22e3e..0507c47e6 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -30,7 +30,10 @@ #include #include -/* ------------------------------------------------------------------------- */ +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + int checkcpu (void) { @@ -227,3 +230,48 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif + + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_cpu_setup(void *blob, bd_t *bd) +{ + u32 *p; + ulong clock; + int len; + + clock = bd->bi_busfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#if defined(CONFIG_MPC85XX_TSEC1) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); + memcpy(p, bd->bi_enetaddr, 6); +#endif + +#if defined(CONFIG_HAS_ETH1) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); + memcpy(p, bd->bi_enet1addr, 6); +#endif + +#if defined(CONFIG_HAS_ETH2) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); + memcpy(p, bd->bi_enet2addr, 6); +#endif + +#if defined(CONFIG_HAS_ETH3) + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); + memcpy(p, bd->bi_enet3addr, 6); +#endif + +} +#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c12b47b58..9f4d36c1a 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_CPM2 static void config_8560_ioports (volatile immap_t * immr) { diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 131c83224..d31a18b79 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -293,6 +293,21 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8540@0" +#define OF_SOC "soc8540@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c96b98b54..86bcfe324 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8541@0" +#define OF_SOC "soc8541@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4ca8bc35d..b1f8a192d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -314,6 +314,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8548@0" +#define OF_SOC "soc8548@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a44e3ec84..b725dac52 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -308,6 +308,18 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8555@0" +#define OF_SOC "soc8555@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 2d5031b77..1c684f2fd 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -290,6 +290,18 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8560@0" +#define OF_SOC "soc8560@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ From a4e11558b810ef2cddffdf7b9d86bc1130441960 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:44:23 -0500 Subject: [PATCH 051/101] * Made sure the code which disables prefetch for PCI devices sets the size of the prefetch region to 0 Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming --- drivers/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 15f74328f..8fde3301e 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -186,7 +186,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose, } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); } if (pci_io) { From f0e6f57f71b3c4fdd13028eb03c3f3e91926dda2 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:44:49 -0500 Subject: [PATCH 052/101] * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming --- include/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/pci.h b/include/pci.h index 0fc00e427..e0e8783a7 100644 --- a/include/pci.h +++ b/include/pci.h @@ -270,6 +270,15 @@ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ #define PCI_AGP_SIZEOF 12 +/* PCI-X registers */ + +#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ +#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ +#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ +#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ + + /* Slot Identification */ #define PCI_SID_ESR 2 /* Expansion Slot Register */ From 97074ed9655309b64231bc2cee69fe85399f8055 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:17 -0500 Subject: [PATCH 053/101] * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- cpu/mpc85xx/pci.c | 184 ++++++++++++++++++++++++++++------- include/asm-ppc/immap_85xx.h | 25 ++++- 2 files changed, 171 insertions(+), 38 deletions(-) diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index a94493e08..ca11bce22 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -32,17 +32,75 @@ #if defined(CONFIG_PCI) +static struct pci_controller *pci_hose; + void -pci_mpc85xx_init(struct pci_controller *hose) +pci_mpc85xx_init(struct pci_controller *board_hose) { + u16 reg16; + u32 dev; + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; volatile ccsr_pcix_t *pcix = &immap->im_pcix; + volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; + volatile ccsr_gur_t *gur = &immap->im_gur; + struct pci_controller * hose; - u16 reg16; + pci_hose = board_hose; + + hose = &pci_hose[0]; hose->first_busno = 0; hose->last_busno = 0xff; + pci_setup_indirect(hose, + (CFG_IMMR+0x8000), + (CFG_IMMR+0x8004)); + + /* + * Hose scan. + */ + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); + } + + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potear1 = 0x00000000; + pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff; + pcix->powbear1 = 0x00000000; + pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | POWAR_MEM_512M); + + pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->potear2 = 0x00000000; + pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff; + pcix->powbear2 = 0x00000000; + pcix->powar2 = (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | POWAR_IO_1M); + + pcix->pitar1 = 0x00000000; + pcix->piwbar1 = 0x00000000; + pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); + + pcix->powar3 = 0; + pcix->powar4 = 0; + pcix->piwar2 = 0; + pcix->piwar3 = 0; + pci_set_region(hose->regions + 0, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, @@ -57,42 +115,8 @@ pci_mpc85xx_init(struct pci_controller *hose) hose->region_count = 2; - pci_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); - - pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcix->powbear1 = 0x00000000; - pcix->powar1 = 0x8004401c; /* 512M MEM space */ - - pcix->potar2 = 0x00000000; - pcix->potear2 = 0x00000000; - pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcix->powbear2 = 0x00000000; - pcix->powar2 = 0x80088017; /* 16M IO space */ - - pcix->pitar1 = 0x00000000; - pcix->piwbar1 = 0x00000000; - pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - * Snoop R/W, 2G */ - - /* - * Hose scan. - */ pci_register_hose(hose); - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); - #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) /* * This is a SW workaround for an apparent HW problem @@ -117,6 +141,94 @@ pci_mpc85xx_init(struct pci_controller *hose) #endif hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC85XX_PCI2 + hose = &pci_hose[1]; + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + pci_setup_indirect(hose, + (CFG_IMMR+0x9000), + (CFG_IMMR+0x9004)); + + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + + pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff; + pcix2->potear1 = 0x00000000; + pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff; + pcix2->powbear1 = 0x00000000; + pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | POWAR_MEM_512M); + + pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff; + pcix2->potear2 = 0x00000000; + pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff; + pcix2->powbear2 = 0x00000000; + pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | POWAR_IO_1M); + + pcix2->pitar1 = 0x00000000; + pcix2->piwbar1 = 0x00000000; + pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); + + pcix2->powar3 = 0; + pcix2->powar4 = 0; + pcix2->piwar2 = 0; + pcix2->piwar3 = 0; + + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + /* + * Hose scan. + */ + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +#endif } +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + +#ifdef CONFIG_MPC85XX_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +#endif +} +#endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 2f10e9591..7a4345a74 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -246,7 +246,6 @@ typedef struct ccsr_lbc { /* * PCI Registers(0x8000-0x9000) - * Omitting Reserved(0x9000-0x2_0000) */ typedef struct ccsr_pcix { uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ @@ -309,9 +308,27 @@ typedef struct ccsr_pcix { uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - char res11[94688]; + uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ + char res11[476]; } ccsr_pcix_t; +#define PCIX_COMMAND 0x62 +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 +#define POWAR_MEM_512M 0x0000001c +#define POWAR_IO_1M 0x00000013 + +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_MEM_2G 0x0000001e + + /* * L2 Cache Registers(0x2_0000-0x2_1000) */ @@ -1572,6 +1589,8 @@ typedef struct ccsr_gur { char res15[61651]; } ccsr_gur_t; +#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ + typedef struct immap { ccsr_local_ecm_t im_local_ecm; ccsr_ddr_t im_ddr; @@ -1579,6 +1598,8 @@ typedef struct immap { ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; ccsr_pcix_t im_pcix; + ccsr_pcix_t im_pcix2; + char reserved[90112]; ccsr_l2cache_t im_l2cache; ccsr_dma_t im_dma; ccsr_tsec_t im_tsec1; From c88f9fe66b64247e5b6a38410ba315ca25596d16 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:45:41 -0500 Subject: [PATCH 054/101] * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- board/mpc8540ads/mpc8540ads.c | 21 ++++----------------- include/configs/MPC8540ADS.h | 9 +++++---- 2 files changed, 9 insertions(+), 21 deletions(-) diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index 855888d27..fbcb39729 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -317,24 +317,8 @@ long int fixed_sdram (void) * Initialize PCI Devices, report devices found. */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; +static struct pci_controller hose; #endif /* CONFIG_PCI */ @@ -357,6 +341,9 @@ ft_board_setup(void *blob, bd_t *bd) u32 *p; int len; +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif ft_cpu_setup(blob, bd); p = ft_get_prop(blob, "/memory/reg", &len); diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index d31a18b79..81ee945d4 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -71,7 +71,7 @@ */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 +#define CONFIG_SYS_CLK_FREQ 66000000 #endif @@ -327,9 +327,10 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) From bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:46:13 -0500 Subject: [PATCH 055/101] * Added VIA configuration table * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- board/cds/common/ft_board.c | 3 + board/cds/common/via.c | 99 +++++++++++++++++++++++++++++++ board/cds/common/via.h | 18 ++++++ board/cds/mpc8541cds/Makefile | 3 +- board/cds/mpc8541cds/init.S | 12 ++-- board/cds/mpc8541cds/mpc8541cds.c | 32 +++++----- board/cds/mpc8548cds/Makefile | 3 +- board/cds/mpc8548cds/init.S | 12 ++-- board/cds/mpc8548cds/mpc8548cds.c | 32 +++++----- board/cds/mpc8555cds/Makefile | 3 +- board/cds/mpc8555cds/init.S | 12 ++-- board/cds/mpc8555cds/mpc8555cds.c | 39 ++++++------ include/configs/MPC8541CDS.h | 21 +++---- include/configs/MPC8548CDS.h | 23 +++---- include/configs/MPC8555CDS.h | 23 +++---- 15 files changed, 223 insertions(+), 112 deletions(-) create mode 100644 board/cds/common/via.c create mode 100644 board/cds/common/via.h diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c index 73eca5e69..77d1d851d 100644 --- a/board/cds/common/ft_board.c +++ b/board/cds/common/ft_board.c @@ -35,6 +35,9 @@ ft_board_setup(void *blob, bd_t *bd) u32 *p; int len; +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif ft_cpu_setup(blob, bd); p = ft_get_prop(blob, "/memory/reg", &len); diff --git a/board/cds/common/via.c b/board/cds/common/via.c new file mode 100644 index 000000000..68c8d212f --- /dev/null +++ b/board/cds/common/via.c @@ -0,0 +1,99 @@ +/* + * Copyright 2006 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* Config the VIA chip */ +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pci_dev_t bridge; + + /* Enable USB and IDE functions */ + pci_hose_write_config_byte(hose, dev, 0x48, 0x08); + + pciauto_config_device(hose, dev); + + /* + * Force the backplane P2P bridge to have a window + * open from 0x00000000-0x00001fff in PCI I/O space. + * This allows legacy I/O (i8259, etc) on the VIA + * southbridge to be accessed. + */ + bridge = PCI_BDF(0,17,0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); + pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); + pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); +} + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + /* + * Since the P2P window was forced to cover the fixed + * legacy I/O addresses, it is necessary to manually + * place the base addresses for the IDE and USB functions + * within this window. + */ + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); +} + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); +} + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); +} + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); +} + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); +} + diff --git a/board/cds/common/via.h b/board/cds/common/via.h new file mode 100644 index 000000000..77cfacc52 --- /dev/null +++ b/board/cds/common/via.h @@ -0,0 +1,18 @@ +#ifndef _MPC85xx_VIA_H +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); +#endif /* _MPC85xx_VIA_H */ diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile index aea61360a..d202281d4 100644 --- a/board/cds/mpc8541cds/Makefile +++ b/board/cds/mpc8541cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8541cds/init.S b/board/cds/mpc8541cds/init.S index 53dcd0d76..978bda5e4 100644 --- a/board/cds/mpc8541cds/init.S +++ b/board/cds/mpc8541cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 6b8aa68f5..c2b3009fd 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -31,6 +31,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -468,26 +469,25 @@ testdram(void) #endif #if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif }; @@ -497,7 +497,7 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); pci_mpc85xx_init(&hose); #endif diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile index aea61360a..d202281d4 100644 --- a/board/cds/mpc8548cds/Makefile +++ b/board/cds/mpc8548cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 53dcd0d76..978bda5e4 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 5bc08900a..6eedb4a20 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -30,6 +30,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -293,26 +294,25 @@ testdram(void) #endif #if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif }; @@ -322,7 +322,7 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); pci_mpc85xx_init(&hose); #endif diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile index aea61360a..d202281d4 100644 --- a/board/cds/mpc8555cds/Makefile +++ b/board/cds/mpc8555cds/Makefile @@ -29,7 +29,8 @@ LIB = lib$(BOARD).a OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ - ../common/ft_board.o + ../common/ft_board.o \ + ../common/via.o SOBJS := init.o diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S index 53dcd0d76..978bda5e4 100644 --- a/board/cds/mpc8555cds/init.S +++ b/board/cds/mpc8555cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 18adf5b9e..e15bf8f2c 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -29,6 +29,7 @@ #include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -464,38 +465,40 @@ testdram(void) } #endif -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +#ifdef CONFIG_PCI +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } -#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP + +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table, + }, +#ifdef CONFIG_MPC85XX_PCI2 + { } #endif }; -#endif /* CONFIG_PCI */ +#endif void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(*pci_hose); #endif } diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 86bcfe324..f73caf031 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,32 +335,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) +#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b1f8a192d..37b518cca 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 +#undef CONFIG_MPC85XX_TSEC4 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b725dac52..b94e38ae3 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void); #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,33 +335,28 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_MPC85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ From b6c5e1373b6ea0bb37a18e4aeecec00613d1cd39 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:46:35 -0500 Subject: [PATCH 056/101] * Fixed a bug where 8555 PCI code used the old variable and function names Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- board/cds/mpc8555cds/mpc8555cds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index e15bf8f2c..012181c31 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -497,8 +497,8 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller **hose); + extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(*pci_hose); + pci_mpc85xx_init(hose); #endif } From 34c3c0e01dbf1f8cc2bd08de92f2b89ba84921eb Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Wed, 28 Jun 2006 10:47:03 -0500 Subject: [PATCH 057/101] * Switched default PCI speed for 8540 ADS back to 33MHz * Added comments and a printf to warn that PCI-X won't work at 33MHz Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming --- cpu/mpc85xx/pci.c | 3 +++ doc/README.mpc85xxads | 3 +++ include/configs/MPC8540ADS.h | 6 +++++- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index ca11bce22..cfb7dcdc8 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -72,6 +72,9 @@ pci_mpc85xx_init(struct pci_controller *board_hose) if (!(gur->pordevsr & PORDEVSR_PCI)) { /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index f0cf782a8..ae8202bdd 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -100,6 +100,9 @@ Updated 13-July-2004 Jon Loeliger SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock + In order to use PCI-X (only in the first PCI slot. The one with + the RIO connector), you need to set SW1[4] (config) to 1 (off). + Also, configure the board to run PCI at 66 MHz. 2. MEMORY MAP TO WORK WITH LINUX KERNEL diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 81ee945d4..8e4d2c95a 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -68,10 +68,14 @@ * The board, however, can run at 66MHz. In any event, this value * must match the settings of some switches. Details can be found * in the README.mpc85xxads. + * + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to + * 33MHz to accommodate, based on a PCI pin. + * Note that PCI-X won't work at 33MHz. */ #ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_SYS_CLK_FREQ 33000000 #endif From 40bc83559db5745681909fd7382ae509567e116d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 9 Aug 2006 15:32:16 -0500 Subject: [PATCH 058/101] Removed MPC8641HPCN DTS source file from build. It is no longer linked into U-Boot; its sources are now located in the kernel tree. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/Makefile | 18 +- board/mpc8641hpcn/oftree.dts | 388 ----------------------------------- 2 files changed, 3 insertions(+), 403 deletions(-) delete mode 100644 board/mpc8641hpcn/oftree.dts diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 0ebed87bc..f70f44ba2 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,27 +25,15 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o pixis.o sys_eeprom.o oftree.o +OBJS := $(BOARD).o pixis.o sys_eeprom.o SOBJS := init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) -ifndef DTC -DTC := dtc -endif - -%.dtb: %.dts - $(DTC) -f -V 0x10 -I dts -O dtb $< >$@ - -%.c: %.dtb - xxd -i $< \ - | sed -e "s/^unsigned char/const unsigned char/g" \ - | sed -e "s/^unsigned int/const unsigned int/g" > $@ - - clean: - rm -f $(OBJS) $(SOBJS) *.dtb oftree.c + rm -f $(OBJS) $(SOBJS) + .PHONY: distclean distclean: clean rm -f $(LIB) core *.bak .depend diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts deleted file mode 100644 index 99d75ca62..000000000 --- a/board/mpc8641hpcn/oftree.dts +++ /dev/null @@ -1,388 +0,0 @@ -/* - * MPC8641 HPCN Device Tree Source - * - * Copyright 2006 Freescale Semiconductor Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - - -/ { - model = "MPC8641HPCN"; - compatible = "mpc86xx"; - #address-cells = <1>; - #size-cells = <1>; - linux,phandle = <100>; - - cpus { - #cpus = <2>; - #address-cells = <1>; - #size-cells = <0>; - linux,phandle = <200>; - - PowerPC,8641@0 { - device_type = "cpu"; - reg = <0>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot - bus-frequency = <0>; // From uboot - clock-frequency = <0>; // From uboot - 32-bit; - linux,phandle = <201>; - linux,boot-cpu; - }; - PowerPC,8641@1 { - device_type = "cpu"; - reg = <1>; - d-cache-line-size = <20>; // 32 bytes - i-cache-line-size = <20>; // 32 bytes - d-cache-size = <8000>; // L1, 32K - i-cache-size = <8000>; // L1, 32K - timebase-frequency = <0>; // 33 MHz, from uboot - bus-frequency = <0>; // From uboot - clock-frequency = <0>; // From uboot - 32-bit; - linux,phandle = <202>; - }; - }; - - memory { - device_type = "memory"; - linux,phandle = <300>; - reg = <00000000 40000000>; // 1G at 0x0 - }; - - soc8641@f8000000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - device_type = "soc"; - ranges = <0 f8000000 00100000>; - reg = ; // CCSRBAR 1M - bus-frequency = <0>; - - i2c@3000 { - device_type = "i2c"; - compatible = "fsl-i2c"; - reg = <3000 100>; - interrupts = <2b 2>; - interrupt-parent = <40000>; - dfsrr; - }; - - i2c@3100 { - device_type = "i2c"; - compatible = "fsl-i2c"; - reg = <3100 100>; - interrupts = <2b 2>; - interrupt-parent = <40000>; - dfsrr; - }; - - mdio@24520 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "mdio"; - compatible = "gianfar"; - reg = <24520 20>; - linux,phandle = <24520>; - ethernet-phy@0 { - linux,phandle = <2452000>; - interrupt-parent = <40000>; - interrupts = <4a 1>; - reg = <0>; - device_type = "ethernet-phy"; - }; - ethernet-phy@1 { - linux,phandle = <2452001>; - interrupt-parent = <40000>; - interrupts = <4a 1>; - reg = <1>; - device_type = "ethernet-phy"; - }; - ethernet-phy@2 { - linux,phandle = <2452002>; - interrupt-parent = <40000>; - interrupts = <4a 1>; - reg = <2>; - device_type = "ethernet-phy"; - }; - ethernet-phy@3 { - linux,phandle = <2452003>; - interrupt-parent = <40000>; - interrupts = <4a 1>; - reg = <3>; - device_type = "ethernet-phy"; - }; - }; - - ethernet@24000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <24000 1000>; - address = [ 00 E0 0C 00 73 00 ]; - interrupts = <1d 2 1e 2 22 2>; - interrupt-parent = <40000>; - phy-handle = <2452000>; - }; - - ethernet@25000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <25000 1000>; - address = [ 00 E0 0C 00 73 01 ]; - interrupts = <23 2 24 2 28 2>; - interrupt-parent = <40000>; - phy-handle = <2452001>; - }; - - ethernet@26000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <26000 1000>; - address = [ 00 E0 0C 00 02 FD ]; - interrupts = <1F 2 20 2 21 2>; - interrupt-parent = <40000>; - phy-handle = <2452002>; - }; - - ethernet@27000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <27000 1000>; - address = [ 00 E0 0C 00 03 FD ]; - interrupts = <25 2 26 2 27 2>; - interrupt-parent = <40000>; - phy-handle = <2452003>; - }; - serial@4500 { - device_type = "serial"; - compatible = "ns16550"; - reg = <4500 100>; - clock-frequency = <0>; - interrupts = <2a 2>; - interrupt-parent = <40000>; - }; - - serial@4600 { - device_type = "serial"; - compatible = "ns16550"; - reg = <4600 100>; - clock-frequency = <0>; - interrupts = <1c 2>; - interrupt-parent = <40000>; - }; - - pci@8000 { - compatible = "86xx"; - device_type = "pci"; - linux,phandle = <8000>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8000 1000>; - bus-range = <0 fe>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <1fca055>; - interrupt-parent = <40000>; - interrupts = <18 2>; - interrupt-map-mask = ; - interrupt-map = < - /* IDSEL 0x11 */ - 8800 0 0 1 4d0 3 2 - 8800 0 0 2 4d0 4 2 - 8800 0 0 3 4d0 5 2 - 8800 0 0 4 4d0 6 2 - - /* IDSEL 0x12 */ - 9000 0 0 1 4d0 4 2 - 9000 0 0 2 4d0 5 2 - 9000 0 0 3 4d0 6 2 - 9000 0 0 4 4d0 3 2 - - /* IDSEL 0x13 */ - 9800 0 0 1 4d0 0 0 - 9800 0 0 2 4d0 0 0 - 9800 0 0 3 4d0 0 0 - 9800 0 0 4 4d0 0 0 - - /* IDSEL 0x14 */ - a000 0 0 1 4d0 0 0 - a000 0 0 2 4d0 0 0 - a000 0 0 3 4d0 0 0 - a000 0 0 4 4d0 0 0 - - /* IDSEL 0x15 */ - a800 0 0 1 4d0 0 0 - a800 0 0 2 4d0 0 0 - a800 0 0 3 4d0 0 0 - a800 0 0 4 4d0 0 0 - - /* IDSEL 0x16 */ - b000 0 0 1 4d0 0 0 - b000 0 0 2 4d0 0 0 - b000 0 0 3 4d0 0 0 - b000 0 0 4 4d0 0 0 - - /* IDSEL 0x17 */ - b800 0 0 1 4d0 0 0 - b800 0 0 2 4d0 0 0 - b800 0 0 3 4d0 0 0 - b800 0 0 4 4d0 0 0 - - /* IDSEL 0x18 */ - c000 0 0 1 4d0 0 0 - c000 0 0 2 4d0 0 0 - c000 0 0 3 4d0 0 0 - c000 0 0 4 4d0 0 0 - - /* IDSEL 0x19 */ - c800 0 0 1 4d0 0 0 - c800 0 0 2 4d0 0 0 - c800 0 0 3 4d0 0 0 - c800 0 0 4 4d0 0 0 - - /* IDSEL 0x1a */ - d000 0 0 1 4d0 6 2 - d000 0 0 2 4d0 3 2 - d000 0 0 3 4d0 4 2 - d000 0 0 4 4d0 5 2 - - - /* IDSEL 0x1b */ - d800 0 0 1 4d0 5 2 - d800 0 0 2 4d0 0 0 - d800 0 0 3 4d0 0 0 - d800 0 0 4 4d0 0 0 - - /* IDSEL 0x1c */ - e000 0 0 1 4d0 9 2 - e000 0 0 2 4d0 a 2 - e000 0 0 3 4d0 c 2 - e000 0 0 4 4d0 7 2 - - /* IDSEL 0x1d */ - e800 0 0 1 4d0 9 2 - e800 0 0 2 4d0 a 2 - e800 0 0 3 4d0 b 2 - e800 0 0 4 4d0 0 0 - - /* IDSEL 0x1e */ - f000 0 0 1 4d0 c 2 - f000 0 0 2 4d0 0 0 - f000 0 0 3 4d0 0 0 - f000 0 0 4 4d0 0 0 - - /* IDSEL 0x1f */ - f800 0 0 1 4d0 6 2 - f800 0 0 2 4d0 0 0 - f800 0 0 3 4d0 0 0 - f800 0 0 4 4d0 0 0 - >; - i8259@4d0 { - linux,phandle = <4d0>; - clock-frequency = <0>; - interrupt-controller; - device_type = "interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - big-endian; - interrupts = <49 2>; - interrupt-parent = <40000>; - }; - - }; - pic@40000 { - linux,phandle = <40000>; - clock-frequency = <0>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <40000 40000>; - built-in; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - big-endian; - interrupts = < - 10 2 11 2 12 2 13 2 - 14 2 15 2 16 2 17 2 - 18 2 19 2 1a 2 1b 2 - 1c 2 1d 2 1e 2 1f 2 - 20 2 21 2 22 2 23 2 - 24 2 25 2 26 2 27 2 - 28 2 29 2 2a 2 2b 2 - 2c 2 2d 2 2e 2 2f 2 - 30 2 31 2 32 2 33 2 - 34 2 35 2 36 2 37 2 - 38 2 39 2 2a 2 3b 2 - 3c 2 3d 2 3e 2 3f 2 - 48 1 49 2 4a 1 - >; - interrupt-parent = <40000>; - }; - rio@c0000 { - #address-cells = <1>; - #size-cells = <0>; - device_type = "rio"; - model = "pq38"; - compatible = "85xx"; - ranges = <0 c0000000 20000000>; - reg = ; - linux,phandle = ; - }; - rio_message@d3000 { - device_type = "network"; - compatible = "85xx"; - linux,phandle = ; - reg = ; - interrupts = <35 2 36 2>; - interrupt-parent = <40000>; - }; - rio_message@d3100 { - device_type = "network"; - compatible = "85xx"; - linux,phandle = ; - reg = ; - interrupts = <37 2 38 2>; - interrupt-parent = <40000>; - }; - rio_doorbell@d3400 { - device_type = "doorbell"; - compatible = "85xx"; - linux,phandle = ; - reg = ; - interrupts = <31 2 32 2>; - interrupt-parent = <40000>; - }; - rio_portwrite@d34e0 { - device_type = "portwrite"; - compatible = "85xx"; - linux,phandle = ; - reg = ; - interrupts = <30 2>; - interrupt-parent = <40000>; - }; - }; -}; - From fecf1c7e4de1b2779edc18742b91c22bdc32b68b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 14 Aug 2006 15:33:38 -0500 Subject: [PATCH 059/101] Fix BAT0 to actually be cacheable, non-guarded as documented. Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 15e987139..200a38f3e 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -378,10 +378,9 @@ * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) -#define CFG_DBAT0U ( BATU_BL_2G | BATU_VS | BATU_VP ) -#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) #define CFG_IBAT0U CFG_DBAT0U /* From 0d9ccc55edf9a7f3c5b2b6263580a6ea8d702a04 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 15 Aug 2006 15:13:15 -0400 Subject: [PATCH 060/101] Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR --- cpu/mpc86xx/start.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 12bf75b2e..25687f8bb 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -814,8 +814,9 @@ relocate_code: mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Global Data pointer */ + mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */ mr r10, r5 /* Save copy of Destination Address */ - + mr r3, r5 /* Destination Address */ lis r4, CFG_MONITOR_BASE@h /* Source Address */ ori r4, r4, CFG_MONITOR_BASE@l From 1c8f6d8fb028f156094d05f2d14298e6479364ac Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 15 Aug 2006 15:12:55 -0400 Subject: [PATCH 061/101] Unlock cache before kernel starts up for MPC86xx --- common/cmd_bootm.c | 4 ++-- lib_ppc/board.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 0225cb7f2..f1c0eb4d1 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -821,7 +821,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, #ifndef CONFIG_OF_FLAT_TREE -#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500) || !defined(CONFIG_MPC86xx)) +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); #endif @@ -839,7 +839,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ -#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500)||!defined(CONFIG_MPC86xx)) +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); #endif /* diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 039053aab..71dae07d3 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -676,7 +676,7 @@ void board_init_r (gd_t *id, ulong dest_addr) icache_enable (); /* it's time to enable the instruction cache */ #endif -#if defined(CFG_INIT_RAM_LOCK) && (defined(CONFIG_E500) || defined(CONFIG_MPC86xx)) +#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ #endif From 67256678f00c09b0a7f19e862e5c1847553d31bc Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 15 Aug 2006 15:13:15 -0400 Subject: [PATCH 062/101] Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR --- cpu/mpc86xx/start.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 12bf75b2e..25687f8bb 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -814,8 +814,9 @@ relocate_code: mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Global Data pointer */ + mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */ mr r10, r5 /* Save copy of Destination Address */ - + mr r3, r5 /* Destination Address */ lis r4, CFG_MONITOR_BASE@h /* Source Address */ ori r4, r4, CFG_MONITOR_BASE@l From 75c299c38369d01addd5e054b8a16217b70f4a86 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 15 Aug 2006 15:12:55 -0400 Subject: [PATCH 063/101] Unlock cache before kernel starts up for MPC86xx --- common/cmd_bootm.c | 4 ++-- lib_ppc/board.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index e5d70fa20..fdf7180a1 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -809,7 +809,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, #ifndef CONFIG_OF_FLAT_TREE -#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500) || !defined(CONFIG_MPC86xx)) +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); #endif @@ -827,7 +827,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ -#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500)||!defined(CONFIG_MPC86xx)) +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); #endif /* diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 2c29f467e..26f5b2fbb 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -676,7 +676,7 @@ void board_init_r (gd_t *id, ulong dest_addr) icache_enable (); /* it's time to enable the instruction cache */ #endif -#if defined(CFG_INIT_RAM_LOCK) && (defined(CONFIG_E500) || defined(CONFIG_MPC86xx)) +#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ #endif From 87a449c8ac396420cb24260f717ea9e6faa82047 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Tue, 22 Aug 2006 09:23:55 -0500 Subject: [PATCH 064/101] Support for FDT in uImage format, error when using FDT from flash Signed-off-by: Matthew McClintock --- common/cmd_bootm.c | 70 ++++++++++++++++++++++++++++++++++++++++++---- include/image.h | 1 + tools/mkimage.c | 1 + 3 files changed, 67 insertions(+), 5 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index f1c0eb4d1..f980659f7 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -528,7 +528,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); image_header_t *hdr = &header; #ifdef CONFIG_OF_FLAT_TREE - char *of_flat_tree; + char *of_flat_tree = NULL; #endif if ((s = getenv ("initrd_high")) != NULL) { @@ -737,14 +737,73 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #ifdef CONFIG_OF_FLAT_TREE - if (argc >= 3) - { + if(argc >= 3) { of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16); - printf ("Booting using flat device tree at 0x%x\n", + hdr = (image_header_t *)of_flat_tree; + + if (*(ulong *)of_flat_tree == OF_DT_HEADER) { +#ifndef CFG_NO_FLASH + if (addr2info((ulong)of_flat_tree) != NULL) { + printf ("Cannot modify flat device tree stored in flash\n" \ + "Copy to memory before using the bootm command\n"); + return; + } +#endif + } else if (ntohl(hdr->ih_magic) == IH_MAGIC) { + printf("## Flat Device Tree Image at %08lX\n", hdr); + print_image_hdr(hdr); + + if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) && + ((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) { + printf ("ERROR: Load address overwrites Flat Device Tree uImage\n"); + return; + } + + printf(" Verifying Checksum ... "); + memmove (&header, (char *)hdr, sizeof(image_header_t)); + checksum = ntohl(header.ih_hcrc); + header.ih_hcrc = 0; + + if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) { + printf("ERROR: Flat Device Tree header checksum is invalid\n"); + return; + } + + checksum = ntohl(hdr->ih_dcrc); + addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t)); + len = ntohl(hdr->ih_size); + + if(checksum != crc32(0, (uchar *)addr, len)) { + printf("ERROR: Flat Device Tree checksum is invalid\n"); + return; + } + printf("OK\n"); + + if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) { + printf ("ERROR: uImage not Flat Device Tree type\n"); + return; + } + if (ntohl(hdr->ih_comp) != IH_COMP_NONE) { + printf("ERROR: uImage is not uncompressed\n"); + return; + } + if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { + printf ("ERROR: uImage data is not a flat device tree\n"); + return; + } + + memmove((void *)ntohl(hdr->ih_load), + (void *)(of_flat_tree + sizeof(image_header_t)), + ntohl(hdr->ih_size)); + of_flat_tree = (char *)ntohl(hdr->ih_load); + } else { + printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree); + return; + } + printf (" Booting using flat device tree at 0x%x\n", of_flat_tree); } #endif - if (!data) { debug ("No initrd\n"); } @@ -1272,6 +1331,7 @@ print_type (image_header_t *hdr) case IH_TYPE_MULTI: type = "Multi-File Image"; break; case IH_TYPE_FIRMWARE: type = "Firmware"; break; case IH_TYPE_SCRIPT: type = "Script"; break; + case IH_TYPE_FLATDT: type = "Flat Device Tree"; break; default: type = "Unknown Image"; break; } diff --git a/include/image.h b/include/image.h index 139df0b2d..ea7e9531d 100644 --- a/include/image.h +++ b/include/image.h @@ -124,6 +124,7 @@ #define IH_TYPE_FIRMWARE 5 /* Firmware Image */ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ +#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ /* * Compression Types diff --git a/tools/mkimage.c b/tools/mkimage.c index fea3e5bc6..d6000e04b 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -130,6 +130,7 @@ table_entry_t type_name[] = { { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, + { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { -1, "", "", }, }; From 5de62c47a8628b3da4d73f7c07027f32a3342d40 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Tue, 22 Aug 2006 09:31:59 -0500 Subject: [PATCH 065/101] Fix disable_of booting Signed-off-by: Matthew McClintock --- common/cmd_bootm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index f980659f7..652d8431d 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -737,7 +737,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #ifdef CONFIG_OF_FLAT_TREE - if(argc >= 3) { + if(argc > 3) { of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16); hdr = (image_header_t *)of_flat_tree; @@ -802,6 +802,9 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } printf (" Booting using flat device tree at 0x%x\n", of_flat_tree); + } else if(getenv("disable_of") == NULL) { + printf ("ERROR: bootm needs flat device tree as third argument\n"); + return; } #endif if (!data) { From 41a0e8b304d3ff55fe27a230507aac79684016ac Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 10:42:21 -0500 Subject: [PATCH 066/101] Cleanup compiler warnings. --- cpu/mpc86xx/pcie_indirect.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c index e3cb4beed..6c63b3815 100644 --- a/cpu/mpc86xx/pcie_indirect.c +++ b/cpu/mpc86xx/pcie_indirect.c @@ -32,9 +32,8 @@ indirect_read_config_pcie(struct pci_controller *hose, int len,u32 *val) { int bus = PCI_BUS(dev); - char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ; - unsigned char *cfg_data; + volatile unsigned char *cfg_data; u32 temp; PEX_FIX; @@ -50,7 +49,7 @@ indirect_read_config_pcie(struct pci_controller *hose, /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ cfg_data = hose->cfg_data; PEX_FIX; - temp = in_le32(cfg_data); + temp = in_le32((u32 *)cfg_data); switch (len) { case 1: *val = (temp >> (((offset & 3))*8)) & 0xff; @@ -74,9 +73,7 @@ indirect_write_config_pcie(struct pci_controller *hose, u32 val) { int bus = PCI_BUS(dev); - char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ; - - unsigned char *cfg_data; + volatile unsigned char *cfg_data; u32 temp; PEX_FIX; @@ -95,23 +92,23 @@ indirect_write_config_pcie(struct pci_controller *hose, switch (len) { case 1: PEX_FIX; - temp = in_le32(cfg_data); + temp = in_le32((u32 *)cfg_data); temp = (temp & ~(0xff << ((offset & 3) * 8))) | (val << ((offset & 3) * 8)); PEX_FIX; - out_le32(cfg_data, temp); + out_le32((u32 *)cfg_data, temp); break; case 2: PEX_FIX; - temp = in_le32(cfg_data); + temp = in_le32((u32 *)cfg_data); temp = (temp & ~(0xffff << ((offset & 3) * 8))); temp |= (val << ((offset & 3) * 8)) ; PEX_FIX; - out_le32(cfg_data, temp); + out_le32((u32 *)cfg_data, temp); break; default: PEX_FIX; - out_le32(cfg_data, val); + out_le32((u32 *)cfg_data, val); break; } PEX_FIX; @@ -155,7 +152,7 @@ static int indirect_write_config_byte_pcie(struct pci_controller *hose, pci_dev_t dev, int offset, - char val) + u8 val) { return indirect_write_config_pcie(hose,dev, offset,1,(u32)val); } @@ -173,7 +170,7 @@ static int indirect_write_config_dword_pcie(struct pci_controller *hose, pci_dev_t dev, int offset, - unsigned short val) + u32 val) { return indirect_write_config_pcie(hose,dev, offset,4,val); } From ffff3ae56f5842ca3679e4ce7922b819a87aad9f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 12:06:18 -0500 Subject: [PATCH 067/101] General indent and whitespace cleanups. --- cpu/mpc86xx/cpu.c | 60 ++++++----- cpu/mpc86xx/cpu_init.c | 8 +- cpu/mpc86xx/i2c.c | 34 ++++--- cpu/mpc86xx/interrupts.c | 88 +++++++--------- cpu/mpc86xx/pci.c | 77 +++++++------- cpu/mpc86xx/pcie_indirect.c | 116 +++++++++++---------- cpu/mpc86xx/speed.c | 14 +-- cpu/mpc86xx/start.S | 197 ++++++++++++++++++------------------ cpu/mpc86xx/traps.c | 89 ++++++---------- 9 files changed, 331 insertions(+), 352 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 0e82e74fa..ddd0ad3b3 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -38,7 +38,8 @@ extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, #endif -int checkcpu (void) +int +checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; @@ -59,11 +60,11 @@ int checkcpu (void) switch (ver) { case PVR_VER(PVR_86xx): - puts("E600"); - break; + puts("E600"); + break; default: - puts("Unknown"); - break; + puts("Unknown"); + break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); @@ -75,8 +76,8 @@ int checkcpu (void) puts(" System: "); switch (ver) { case SVR_8641: - puts("8641"); - break; + puts("8641"); + break; case SVR_8641D: puts("8641D"); break; @@ -97,10 +98,10 @@ int checkcpu (void) lcrr = CFG_LBC_LCRR; #else { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; - lcrr = lbc->lcrr; + lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; @@ -126,8 +127,10 @@ soft_restart(unsigned long addr) { #ifndef CONFIG_MPC8641HPCN - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ + /* + * SRR0 has system reset vector, SRR1 has default MSR value + * rfi restores MSR from SRR1 and sets the PC to the SRR0 value + */ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); @@ -140,7 +143,7 @@ soft_restart(unsigned long addr) #endif /* !CONFIG_MPC8641HPCN */ - while(1); /* not reached */ + while (1) ; /* not reached */ } @@ -185,16 +188,17 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif /* !CONFIG_MPC8641HPCN */ - while(1); /* not reached */ + while (1) ; /* not reached */ } /* * Get timebase clock frequency */ -unsigned long get_tbclk(void) +unsigned long +get_tbclk(void) { - sys_info_t sys_info; + sys_info_t sys_info; get_sys_info(&sys_info); return (sys_info.freqSystemBus + 3L) / 4L; @@ -210,9 +214,10 @@ watchdog_reset(void) #if defined(CONFIG_DDR_ECC) -void dma_init(void) +void +dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; dma->satr0 = 0x00040000; @@ -220,26 +225,28 @@ void dma_init(void) asm("sync; isync"); } -uint dma_check(void) +uint +dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; volatile uint status = dma->sr0; /* While the channel is busy, spin */ - while((status & 4) == 4) { + while ((status & 4) == 4) { status = dma->sr0; } if (status != 0) { - printf ("DMA Error: status = %x\n", status); + printf("DMA Error: status = %x\n", status); } return status; } -int dma_xfer(void *dest, uint count, void *src) +int +dma_xfer(void *dest, uint count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; dma->dar0 = (uint) dest; @@ -256,7 +263,8 @@ int dma_xfer(void *dest, uint count, void *src) #ifdef CONFIG_OF_FLAT_TREE -void ft_cpu_setup(void *blob, bd_t *bd) +void +ft_cpu_setup(void *blob, bd_t *bd) { u32 *p; ulong clock; @@ -292,7 +300,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_MPC86XX_TSEC4) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); - memcpy(p, bd->bi_enet3addr, 6); + memcpy(p, bd->bi_enet3addr, 6); #endif } diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 93b73381f..6ed7c3720 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -38,11 +38,11 @@ void cpu_init_f(void) { - DECLARE_GLOBAL_DATA_PTR; + DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; - /* Pointer is writable since we allocated a register for it */ + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); /* Clear initial global data */ @@ -104,8 +104,8 @@ void cpu_init_f(void) /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); - /* enable SYNCBE | ABE bits in HID1 */ - set_hid1(get_hid1() | 0x00000C00); + /* enable SYNCBE | ABE bits in HID1 */ + set_hid1(get_hid1() | 0x00000C00); } /* diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c index b3ac848a4..d99ecb92d 100644 --- a/cpu/mpc86xx/i2c.c +++ b/cpu/mpc86xx/i2c.c @@ -61,7 +61,7 @@ i2c_init(int speed, int slaveadd) writeb(0x3f, I2CFDR); /* set default filter */ - writeb(0x10,I2CDFSRR); + writeb(0x10, I2CDFSRR); /* write slave address */ writeb(slaveadd, I2CADR); @@ -76,7 +76,7 @@ i2c_init(int speed, int slaveadd) static __inline__ int i2c_wait4bus(void) { - ulong timeval = get_timer (0); + ulong timeval = get_timer(0); while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { if (get_timer(timeval) > TIMEOUT) { @@ -91,7 +91,7 @@ static __inline__ int i2c_wait(int write) { u32 csr; - ulong timeval = get_timer (0); + ulong timeval = get_timer(0); do { csr = readb(I2CCSR); @@ -105,7 +105,7 @@ i2c_wait(int write) return -1; } - if (!(csr & MPC86xx_I2CSR_MCF)) { + if (!(csr & MPC86xx_I2CSR_MCF)) { debug("i2c_wait: unfinished\n"); return -1; } @@ -123,7 +123,7 @@ i2c_wait(int write) } static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) +i2c_write_addr(u8 dev, u8 dir, int rsta) { writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX | (rsta ? MPC86xx_I2CCR_RSTA : 0), @@ -138,7 +138,7 @@ i2c_write_addr (u8 dev, u8 dir, int rsta) } static __inline__ int -__i2c_write (u8 *data, int length) +__i2c_write(u8 *data, int length) { int i; @@ -156,7 +156,7 @@ __i2c_write (u8 *data, int length) } static __inline__ int -__i2c_read (u8 *data, int length) +__i2c_read(u8 *data, int length) { int i; @@ -174,8 +174,7 @@ __i2c_read (u8 *data, int length) /* Generate ack on last next to last byte */ if (i == length - 2) writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA - | MPC86xx_I2CCR_TXAK, - I2CCCR); + | MPC86xx_I2CCR_TXAK, I2CCCR); /* Generate stop on last byte */ if (i == length - 1) @@ -188,10 +187,10 @@ __i2c_read (u8 *data, int length) } int -i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) +i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) { int i = 0; - u8 *a = (u8*)&addr; + u8 *a = (u8 *) &addr; if (i2c_wait4bus() < 0) goto exit; @@ -214,10 +213,10 @@ exit: } int -i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) +i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) { int i = 0; - u8 *a = (u8*)&addr; + u8 *a = (u8 *) &addr; if (i2c_wait4bus() < 0) goto exit; @@ -236,7 +235,8 @@ exit: return !(i == length); } -int i2c_probe (uchar chip) +int +i2c_probe(uchar chip) { int tmp; @@ -250,7 +250,8 @@ int i2c_probe (uchar chip) return i2c_read(chip, 0, 1, (char *)&tmp, 1); } -uchar i2c_reg_read (uchar i2c_addr, uchar reg) +uchar +i2c_reg_read(uchar i2c_addr, uchar reg) { char buf[1]; @@ -259,7 +260,8 @@ uchar i2c_reg_read (uchar i2c_addr, uchar reg) return buf[0]; } -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +void +i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) { i2c_write(i2c_addr, reg, 1, &val, 1); } diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index a8bcb98b8..1df6cdc5b 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -41,7 +41,7 @@ unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ unsigned long timestamp; -static __inline__ unsigned long get_msr (void) +static __inline__ unsigned long get_msr(void) { unsigned long msr; @@ -50,12 +50,12 @@ static __inline__ unsigned long get_msr (void) return msr; } -static __inline__ void set_msr (unsigned long msr) +static __inline__ void set_msr(unsigned long msr) { asm volatile ("mtmsr %0"::"r" (msr)); } -static __inline__ unsigned long get_dec (void) +static __inline__ unsigned long get_dec(void) { unsigned long val; @@ -64,58 +64,58 @@ static __inline__ unsigned long get_dec (void) return val; } - -static __inline__ void set_dec (unsigned long val) +static __inline__ void set_dec(unsigned long val) { if (val) asm volatile ("mtdec %0"::"r" (val)); } /* interrupt is not supported yet */ -int interrupt_init_cpu (unsigned *decrementer_count) +int interrupt_init_cpu(unsigned *decrementer_count) { return 0; } - -int interrupt_init (void) +int interrupt_init(void) { int ret; /* call cpu specific function from $(CPU)/interrupts.c */ - ret = interrupt_init_cpu (&decrementer_count); + ret = interrupt_init_cpu(&decrementer_count); if (ret) return ret; - decrementer_count = get_tbclk()/CFG_HZ; - debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); + decrementer_count = get_tbclk() / CFG_HZ; + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", + (get_tbclk() / 1000000), + decrementer_count); - set_dec (decrementer_count); + set_dec(decrementer_count); - set_msr (get_msr () | MSR_EE); + set_msr(get_msr() | MSR_EE); - debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); + debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", + get_msr(), + get_dec()); return 0; } - -void enable_interrupts (void) +void enable_interrupts(void) { - set_msr (get_msr () | MSR_EE); + set_msr(get_msr() | MSR_EE); } /* returns flag if MSR_EE was set before */ -int disable_interrupts (void) +int disable_interrupts(void) { - ulong msr = get_msr (); + ulong msr = get_msr(); - set_msr (msr & ~MSR_EE); + set_msr(msr & ~MSR_EE); return (msr & MSR_EE) != 0; } - void increment_timestamp(void) { timestamp++; @@ -126,52 +126,49 @@ void increment_timestamp(void) * with interrupts disabled. * Trivial implementation - no need to be really accurate. */ -void -timer_interrupt_cpu (struct pt_regs *regs) +void timer_interrupt_cpu(struct pt_regs *regs) { /* nothing to do here */ } - -void timer_interrupt (struct pt_regs *regs) +void timer_interrupt(struct pt_regs *regs) { /* call cpu specific function from $(CPU)/interrupts.c */ - timer_interrupt_cpu (regs); + timer_interrupt_cpu(regs); timestamp++; ppcDcbf(×tamp); /* Restore Decrementer Count */ - set_dec (decrementer_count); + set_dec(decrementer_count); #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) - WATCHDOG_RESET (); -#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ + WATCHDOG_RESET(); +#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ #ifdef CONFIG_STATUS_LED - status_led_tick (timestamp); + status_led_tick(timestamp); #endif /* CONFIG_STATUS_LED */ #ifdef CONFIG_SHOW_ACTIVITY - board_show_activity (timestamp); + board_show_activity(timestamp); #endif /* CONFIG_SHOW_ACTIVITY */ - } -void reset_timer (void) +void reset_timer(void) { timestamp = 0; } -ulong get_timer (ulong base) +ulong get_timer(ulong base) { return timestamp - base; } -void set_timer (ulong t) +void set_timer(ulong t) { timestamp = t; } @@ -180,24 +177,20 @@ void set_timer (ulong t) * Install and free a interrupt handler. Not implemented yet. */ -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) { } -void -irq_free_handler(int vec) +void irq_free_handler(int vec) { } - /* * irqinfo - print information about PCI devices,not implemented. */ -int -do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - printf ("\nInterrupt-unsupported:\n"); + printf("\nInterrupt-unsupported:\n"); return 0; } @@ -205,14 +198,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Handle external interrupts */ -void -external_interrupt(struct pt_regs *regs) +void external_interrupt(struct pt_regs *regs) { puts("external_interrupt (oops!)\n"); } - - - - - - diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c index deb66aa64..b86548db4 100644 --- a/cpu/mpc86xx/pci.c +++ b/cpu/mpc86xx/pci.c @@ -34,7 +34,7 @@ void pci_mpc86xx_init(struct pci_controller *hose) { - volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_pex_t *pcie1 = &immap->im_pex1; u16 temp16; u32 temp32; @@ -46,62 +46,69 @@ pci_mpc86xx_init(struct pci_controller *hose) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - if ((io_sel ==2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || - io_sel == 7 || io_sel == 0xf) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - printf ("PCI-EXPRESS 1: Configured as %s \n", - pcie1_agent ? "Agent" : "Host"); - if(pcie1_agent) return; /*Don't scan bus when configured as agent*/ - printf (" Scanning PCIE bus"); - debug("0x%08x=0x%08x ", &pcie1->pme_msg_det,pcie1->pme_msg_det); + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || + io_sel == 7 || io_sel == 0xf) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + printf("PCI-EXPRESS 1: Configured as %s \n", + pcie1_agent ? "Agent" : "Host"); + if (pcie1_agent) + return; /*Don't scan bus when configured as agent */ + printf(" Scanning PCIE bus"); + debug("0x%08x=0x%08x ", + &pcie1->pme_msg_det, + pcie1->pme_msg_det); if (pcie1->pme_msg_det) { pcie1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pcie1->pme_msg_det); + debug(" with errors. Clearing. Now 0x%08x", + pcie1->pme_msg_det); } - debug ("\n"); - } - else{ + debug("\n"); + } else { printf("PCI-EXPRESS 1 disabled!\n"); return; } - /*set first_bus=0 only skipped B0:D0:F0 which is + /* + * Set first_bus=0 only skipped B0:D0:F0 which is * a reserved device in M1575, but make it easy for * most of the scan process. */ hose->first_busno = 0x00; hose->last_busno = 0xfe; - pcie_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); + pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); - pci_hose_read_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, &temp16); + pci_hose_read_config_word(hose, + PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16); temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, temp16); + PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_hose_write_config_word(hose, + PCI_BDF(0, 0, 0), PCI_COMMAND, temp16); - pci_hose_write_config_word(hose,PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, + PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); - pci_hose_read_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, &temp32); + pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, + &temp32); temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); - pci_hose_write_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, temp32); + pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, + temp32); pcie1->powar1 = 0; pcie1->powar2 = 0; pcie1->piwar1 = 0; pcie1->piwar1 = 0; - pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->powar1 = 0x8004401c; /* 512M MEM space */ - pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->potear1 = 0x00000000; + pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->powar1 = 0x8004401c; /* 512M MEM space */ + pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcie1->potear1 = 0x00000000; - pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcie1->powar2 = 0x80088017; /* 16M IO space */ - pcie1->potar2 = 0x00000000; - pcie1->potear2 = 0x00000000; + pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcie1->powar2 = 0x80088017; /* 16M IO space */ + pcie1->potar2 = 0x00000000; + pcie1->potear2 = 0x00000000; pcie1->pitar1 = 0x00000000; pcie1->piwbar1 = 0x00000000; @@ -131,9 +138,9 @@ pci_mpc86xx_init(struct pci_controller *hose) pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); - debug("pcie_mpc86xx_init: last_busno %x\n",hose->last_busno); - debug("pcie_mpc86xx init: current_busno %x\n ",hose->current_busno); + debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno); + debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno); printf("....PCIE1 scan & enumeration done\n"); } -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c index 6c63b3815..b00ad76ab 100644 --- a/cpu/mpc86xx/pcie_indirect.c +++ b/cpu/mpc86xx/pcie_indirect.c @@ -28,8 +28,10 @@ static int indirect_read_config_pcie(struct pci_controller *hose, - pci_dev_t dev, int offset, - int len,u32 *val) + pci_dev_t dev, + int offset, + int len, + u32 *val) { int bus = PCI_BUS(dev); @@ -37,10 +39,12 @@ indirect_read_config_pcie(struct pci_controller *hose, u32 temp; PEX_FIX; - if( bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); - }else { - PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); + if (bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000001); + } else { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000000); } /* * Note: the caller has already checked that offset is @@ -49,13 +53,13 @@ indirect_read_config_pcie(struct pci_controller *hose, /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ cfg_data = hose->cfg_data; PEX_FIX; - temp = in_le32((u32 *)cfg_data); + temp = in_le32((u32 *) cfg_data); switch (len) { case 1: - *val = (temp >> (((offset & 3))*8)) & 0xff; + *val = (temp >> (((offset & 3)) * 8)) & 0xff; break; case 2: - *val = (temp >> (((offset & 3))*8)) & 0xffff; + *val = (temp >> (((offset & 3)) * 8)) & 0xffff; break; default: *val = temp; @@ -67,20 +71,22 @@ indirect_read_config_pcie(struct pci_controller *hose, static int indirect_write_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 val) + pci_dev_t dev, + int offset, + int len, + u32 val) { int bus = PCI_BUS(dev); volatile unsigned char *cfg_data; u32 temp; PEX_FIX; - if( bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); - }else { - PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); + if (bus == 0xff) { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000001); + } else { + PCI_CFG_OUT(hose->cfg_addr, + dev | (offset & 0xfc) | 0x80000000); } /* @@ -92,23 +98,23 @@ indirect_write_config_pcie(struct pci_controller *hose, switch (len) { case 1: PEX_FIX; - temp = in_le32((u32 *)cfg_data); + temp = in_le32((u32 *) cfg_data); temp = (temp & ~(0xff << ((offset & 3) * 8))) | - (val << ((offset & 3) * 8)); + (val << ((offset & 3) * 8)); PEX_FIX; - out_le32((u32 *)cfg_data, temp); + out_le32((u32 *) cfg_data, temp); break; case 2: PEX_FIX; - temp = in_le32((u32 *)cfg_data); + temp = in_le32((u32 *) cfg_data); temp = (temp & ~(0xffff << ((offset & 3) * 8))); - temp |= (val << ((offset & 3) * 8)) ; + temp |= (val << ((offset & 3) * 8)); PEX_FIX; - out_le32((u32 *)cfg_data, temp); + out_le32((u32 *) cfg_data, temp); break; default: PEX_FIX; - out_le32((u32 *)cfg_data, val); + out_le32((u32 *) cfg_data, val); break; } PEX_FIX; @@ -117,68 +123,66 @@ indirect_write_config_pcie(struct pci_controller *hose, static int indirect_read_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 *val) + pci_dev_t dev, + int offset, + u8 *val) { u32 val32; - indirect_read_config_pcie(hose,dev,offset,1,&val32); - *val = (u8)val32; + indirect_read_config_pcie(hose, dev, offset, 1, &val32); + *val = (u8) val32; return 0; } static int indirect_read_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u16 *val) + pci_dev_t dev, + int offset, + u16 *val) { u32 val32; - indirect_read_config_pcie(hose,dev,offset,2,&val32); - *val = (u16)val32; + indirect_read_config_pcie(hose, dev, offset, 2, &val32); + *val = (u16) val32; return 0; } static int indirect_read_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 *val) + pci_dev_t dev, + int offset, + u32 *val) { - return indirect_read_config_pcie(hose,dev, offset,4,val); + return indirect_read_config_pcie(hose, dev, offset, 4, val); } static int indirect_write_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 val) + pci_dev_t dev, + int offset, + u8 val) { - return indirect_write_config_pcie(hose,dev, offset,1,(u32)val); + return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val); } static int indirect_write_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - unsigned short val) + pci_dev_t dev, + int offset, + unsigned short val) { - return indirect_write_config_pcie(hose,dev, offset,2,(u32)val); + return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val); } static int indirect_write_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 val) + pci_dev_t dev, + int offset, + u32 val) { - return indirect_write_config_pcie(hose,dev, offset,4,val); + return indirect_write_config_pcie(hose, dev, offset, 4, val); } void -pcie_setup_indirect(struct pci_controller* hose, - u32 cfg_addr, - u32 cfg_data) +pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) { pci_set_ops(hose, indirect_read_config_byte_pcie, @@ -188,8 +192,8 @@ pcie_setup_indirect(struct pci_controller* hose, indirect_write_config_word_pcie, indirect_write_config_dword_pcie); - hose->cfg_addr = (unsigned int *) cfg_addr; - hose->cfg_data = (unsigned char *) cfg_data; + hose->cfg_addr = (unsigned int *)cfg_addr; + hose->cfg_data = (unsigned char *)cfg_data; } -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index e13070537..312ca1282 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -30,16 +30,16 @@ #include -void get_sys_info (sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sysInfo) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio, e600_ratio; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - switch(plat_ratio) { + switch (plat_ratio) { case 0x0: sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; break; @@ -56,7 +56,7 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; break; default: - sysInfo->freqSystemBus = 0; + sysInfo->freqSystemBus = 0; break; } @@ -68,19 +68,19 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; break; case 0x19: - sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2; break; case 0x20: sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; break; case 0x39: - sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2; break; case 0x28: sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus; break; case 0x1d: - sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2; break; default: sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 25687f8bb..e537dcb32 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -74,7 +74,7 @@ * r4 - 2nd arg to board_init(): boot flag */ .text - .long 0x27051956 /* U-Boot Magic Number */ + .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: .ascii U_BOOT_VERSION @@ -92,7 +92,7 @@ _start: .globl _start_warm _start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ + li r21, BOOTFLAG_WARM /* Software reboot */ b boot_warm sync @@ -183,7 +183,7 @@ boot_cold: boot_warm: /* if this is a multi-core system we need to check which cpu - * this is, if it is not cpu 0 send the cpu to the linux reset + * this is, if it is not cpu 0 send the cpu to the linux reset * vector */ #if (CONFIG_NUM_CPUS > 1) mfspr r0, MSSCR0 @@ -194,7 +194,7 @@ boot_warm: bl secondary_cpu_setup #endif - + /* disable everything */ 1: li r0, 0 mtspr HID0, r0 @@ -202,17 +202,17 @@ boot_warm: mtmsr 0 bl invalidate_bats sync - + #ifdef CFG_L2 /* init the L2 cache */ addis r3, r0, L2_INIT@h ori r3, r3, L2_INIT@l - mtspr l2cr, r3 + mtspr l2cr, r3 /* invalidate the L2 cache */ bl l2cache_invalidate sync #endif - + /* * Calculate absolute address in FLASH and jump there *------------------------------------------------------*/ @@ -231,7 +231,7 @@ in_flash: /* enable extended addressing */ bl enable_ext_addr - + /* setup the bats */ bl setup_bats sync @@ -240,7 +240,7 @@ in_flash: /* setup ccsrbar */ bl setup_ccsrbar #endif - + /* Fix for SMP linux - Changing arbitration to round-robin */ lis r3, CFG_CCSRBAR@h ori r3, r3, 0x1000 @@ -279,7 +279,7 @@ in_flash: stw r4, 0(r3) sync #endif -#if 1 +#if 1 /* make sure timer enabled in guts register too */ lis r3, CFG_CCSRBAR@h oris r3,r3, 0xE @@ -289,7 +289,7 @@ in_flash: ori r5,r5,0x5FFF and r4,r4,r5 stw r4,0(r3) -#endif +#endif /* * Cache must be enabled here for stack-in-cache trick. * This means we need to enable the BATS. @@ -303,13 +303,13 @@ in_flash: /* enable and invalidate the data cache */ /* bl l1dcache_enable */ - bl dcache_enable + bl dcache_enable sync #if 1 bl icache_enable #endif - + #ifdef CFG_INIT_RAM_LOCK bl lock_ram_in_cache sync @@ -330,7 +330,7 @@ in_flash: bl cpu_init_f sync -#ifdef RUN_DIAG +#ifdef RUN_DIAG /* Sri: Code to run the diagnostic automatically */ @@ -361,9 +361,9 @@ in_flash: /* Branch to diagnostic */ blr - -diag_done: -#endif + +diag_done: +#endif /* bl l2cache_enable*/ mr r3, r21 @@ -377,7 +377,7 @@ diag_done: .globl invalidate_bats invalidate_bats: - + /* invalidate BATs */ mtspr IBAT0U, r0 mtspr IBAT1U, r0 @@ -401,12 +401,12 @@ invalidate_bats: isync sync blr - - + + /* setup_bats - set them up to some initial state */ .globl setup_bats setup_bats: - + addis r0, r0, 0x0000 /* IBAT 0 */ @@ -553,7 +553,7 @@ setup_bats: mtspr DBAT7U, r3 isync -1: +1: addis r3, 0, 0x0000 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ isync @@ -662,142 +662,140 @@ get_svr: blr -/*------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in8 + * Description: Input 8 bits + */ .globl in8 in8: lbz r3,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out8 + * Description: Output 8 bits + */ .globl out8 out8: stb r4,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out16 + * Description: Output 16 bits + */ .globl out16 out16: sth r4,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out16r + * Description: Byte reverse and output 16 bits + */ .globl out16r out16r: sthbrx r4,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out32 + * Description: Output 32 bits + */ .globl out32 out32: stw r4,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: out32r + * Description: Byte reverse and output 32 bits + */ .globl out32r out32r: stwbrx r4,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in16 + * Description: Input 16 bits + */ .globl in16 in16: lhz r3,0x0000(r3) blr -/*------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in16r + * Description: Input 16 bits and byte reverse + */ .globl in16r in16r: lhbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in32 + * Description: Input 32 bits + */ .globl in32 in32: lwz 3,0x0000(3) blr -/*------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ +/* + * Function: in32r + * Description: Input 32 bits and byte reverse + */ .globl in32r in32r: lwbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ +/* + * Function: ppcDcbf + * Description: Data Cache block flush + * Input: r3 = effective address + * Output: none. + */ .globl ppcDcbf ppcDcbf: dcbf r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ +/* + * Function: ppcDcbi + * Description: Data Cache block Invalidate + * Input: r3 = effective address + * Output: none. + */ .globl ppcDcbi ppcDcbi: dcbi r0,r3 blr -/*-------------------------------------------------------------------------- +/* * Function: ppcDcbz * Description: Data Cache block zero. * Input: r3 = effective address * Output: none. - *-------------------------------------------------------------------------- */ - + */ .globl ppcDcbz ppcDcbz: dcbz r0,r3 blr -/*-------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*-------------------------------------------------------------------------- */ +/* + * Function: ppcSync + * Description: Processor Synchronize + * Input: none. + * Output: none. + */ .globl ppcSync ppcSync: sync blr - -/*-----------------------------------------------------------------------*/ + /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -1062,7 +1060,7 @@ enable_ext_addr: #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) .globl setup_ccsrbar -setup_ccsrbar: +setup_ccsrbar: /* Special sequence needed to update CCSRBAR itself */ lis r4, CFG_CCSRBAR_DEFAULT@h ori r4, r4, CFG_CCSRBAR_DEFAULT@l @@ -1081,10 +1079,10 @@ setup_ccsrbar: lis r3, CFG_CCSRBAR@h lwz r5, CFG_CCSRBAR@l(r3) isync - + blr #endif - + #ifdef CFG_INIT_RAM_LOCK lock_ram_in_cache: /* Allocate Initial RAM in data cache. @@ -1120,7 +1118,7 @@ lock_ram_in_cache: isync blr #endif - + .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1146,7 +1144,7 @@ unlock_ram_in_cache: sync blr #endif -#if 0 +#if 0 /* Unlock the first way of the data cache */ mfspr r0, LDSTCR li r3,0x0080 @@ -1173,16 +1171,16 @@ unlock_ram_in_cache: * from Linux. We'll do some basic cpu init and then pass * it to the Linux Reset Vector. * Sri: Much of this initialization is not required. Linux - * rewrites the bats, and the sprs and also enables the L1 cache. + * rewrites the bats, and the sprs and also enables the L1 cache. */ #if (CONFIG_NUM_CPUS > 1) .globl secondary_cpu_setup -secondary_cpu_setup: +secondary_cpu_setup: /* Do only core setup on all cores except cpu0 */ bl invalidate_bats sync bl enable_ext_addr - + #ifdef CFG_L2 /* init the L2 cache */ addis r3, r0, L2_INIT@h @@ -1204,27 +1202,26 @@ secondary_cpu_setup: /* enable and invalidate the instruction cache*/ bl icache_enable sync - /* TBEN in HID0 */ mfspr r4, HID0 - oris r4, r4, 0x0400 + oris r4, r4, 0x0400 mtspr HID0, r4 sync isync - + /*SYNCBE|ABE in HID1*/ mfspr r4, HID1 - ori r4, r4, 0x0C00 + ori r4, r4, 0x0C00 mtspr HID1, r4 sync isync - + lis r3, CONFIG_LINUX_RESET_VEC@h ori r3, r3, CONFIG_LINUX_RESET_VEC@l mtlr r3 blr - - /* Never Returns, Running in Linux Now */ + + /* Never Returns, Running in Linux Now */ #endif diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 8113dfbcc..8ea14e575 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -57,21 +57,22 @@ print_backtrace(unsigned long *sp) printf("Call backtrace: "); while (sp) { - if ((uint)sp > END_OF_MEM) + if ((uint) sp > END_OF_MEM) break; i = sp[1]; if (cnt++ % 7 == 0) printf("\n"); printf("%08lX ", i); - if (cnt > 32) break; + if (cnt > 32) + break; sp = (unsigned long *)*sp; } printf("\n"); } void -show_regs(struct pt_regs * regs) +show_regs(struct pt_regs *regs) { int i; @@ -80,21 +81,19 @@ show_regs(struct pt_regs * regs) regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); printf("MSR: %08lx EE: %01x PR: %01x FP:" " %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); + regs->msr, regs->msr & MSR_EE ? 1 : 0, + regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, + regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, + regs->msr & MSR_DR ? 1 : 0); printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { printf("GPR%02d: ", i); } printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { + if ((i % 8) == 7) { printf("\n"); } } @@ -106,7 +105,7 @@ _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); + panic("Exception in kernel pc %lx signal %d", regs->nip, signr); } void @@ -124,25 +123,25 @@ MachineCheckException(struct pt_regs *regs) } #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif printf("Machine check in kernel mode.\n"); printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): + printf("regs %p ", regs); + switch (regs->msr & 0x000F0000) { + case (0x80000000 >> 12): printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); + "with mmu off\n"); break; - case (0x80000000>>13): + case (0x80000000 >> 13): printf("Transfer error ack signal\n"); break; - case (0x80000000>>14): + case (0x80000000 >> 14): printf("Data parity signal\n"); break; - case (0x80000000>>15): + case (0x80000000 >> 15): printf("Address parity signal\n"); break; default: @@ -157,7 +156,7 @@ void AlignmentException(struct pt_regs *regs) { #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif show_regs(regs); @@ -172,17 +171,17 @@ ProgramCheckException(struct pt_regs *regs) int i, j; #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif show_regs(regs); - p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0); + p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0); p -= 32; - for (i = 0; i < 256; i+=16) { - printf("%08x: ", (unsigned int)p+i); + for (i = 0; i < 256; i += 16) { + printf("%08x: ", (unsigned int)p + i); for (j = 0; j < 16; j++) { - printf("%02x ", p[i+j]); + printf("%02x ", p[i + j]); } printf("\n"); } @@ -195,7 +194,7 @@ void SoftEmuException(struct pt_regs *regs) { #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif show_regs(regs); @@ -203,12 +202,11 @@ SoftEmuException(struct pt_regs *regs) panic("Software Emulation Exception"); } - void UnknownException(struct pt_regs *regs) { #if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", @@ -216,36 +214,13 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. +/* + * Probe an address by reading. + * If not present, return -1, + * otherwise return 0. */ int addr_probe(uint *addr) { -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif return 0; } - - - - - - From 80e955c7dd98f4b4fd23c2113caf75ed2b77b5b3 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 12:25:27 -0500 Subject: [PATCH 068/101] General indent and whitespace cleanups. --- board/mpc8641hpcn/mpc8641hpcn.c | 69 ++++----- board/mpc8641hpcn/pixis.c | 21 ++- board/mpc8641hpcn/sys_eeprom.c | 240 +++++++++++++++++--------------- 3 files changed, 170 insertions(+), 160 deletions(-) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5023c1c97..b2cf4a956 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -50,12 +50,12 @@ void sdram_init(void); long int fixed_sdram(void); -int board_early_init_f (void) +int board_early_init_f(void) { return 0; } -int checkboard (void) +int checkboard(void) { puts("Board: MPC8641HPCN\n"); @@ -68,7 +68,7 @@ int checkboard (void) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) @@ -80,7 +80,7 @@ int checkboard (void) debug(" with errors. Clearing. Now 0x%08x", pex1->pme_msg_det); } - debug ("\n"); + debug("\n"); } else { puts("PCI-EXPRESS 1: Disabled\n"); } @@ -99,9 +99,9 @@ initdram(int board_type) long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = spd_sdram(); #else - dram_size = fixed_sdram (); + dram_size = fixed_sdram(); #endif #if defined(CFG_RAMBOOT) @@ -122,7 +122,8 @@ initdram(int board_type) #if defined(CFG_DRAM_TEST) -int testdram(void) +int +testdram(void) { uint *pstart = (uint *) CFG_MEMTEST_START; uint *pend = (uint *) CFG_MEMTEST_END; @@ -134,7 +135,7 @@ int testdram(void) for (p = pstart; p < pend; p++) { if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); + printf("SDRAM test fails at: %08x\n", (uint) p); return 1; } } @@ -145,7 +146,7 @@ int testdram(void) for (p = pstart; p < pend; p++) { if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); + printf("SDRAM test fails at: %08x\n", (uint) p); return 1; } } @@ -160,11 +161,12 @@ int testdram(void) /* * Fixed sdram init -- doesn't use serial presence detect. */ -long int fixed_sdram(void) +long int +fixed_sdram(void) { #if !defined(CFG_RAMBOOT) - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr1; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr1; ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; @@ -211,28 +213,25 @@ long int fixed_sdram(void) #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_fsl86xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, + {} }; #endif static struct pci_controller hose = { #ifndef CONFIG_PCI_PNP - config_table: pci_mpc86xxcts_config_table, + config_table:pci_mpc86xxcts_config_table, #endif }; -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI */ - -void -pci_init_board(void) +void pci_init_board(void) { #ifdef CONFIG_PCI extern void pci_mpc86xx_init(struct pci_controller *hose); @@ -260,7 +259,7 @@ ft_board_setup(void *blob, bd_t *bd) void -mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { char cmd; ulong val; @@ -276,7 +275,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cmd = argv[1][1]; switch (cmd) { - case 'f': /* reset with frequency changed */ + case 'f': /* reset with frequency changed */ if (argc < 5) goto my_usage; read_from_px_regs(0); @@ -294,7 +293,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else goto my_usage; - while (1); /* Not reached */ + while (1) ; /* Not reached */ case 'l': if (argv[2][1] == 'f') { @@ -305,7 +304,8 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) corepll = strfractoint(argv[4]); val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); + val = val + set_px_mpxpll(simple_strtoul(argv[5], + NULL, 10)); if (val == 3) { puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); set_altbank(); @@ -316,9 +316,9 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else goto my_usage; - while(1); /* Not reached */ + while (1) ; /* Not reached */ - } else if(argv[2][1] == 'd'){ + } else if (argv[2][1] == 'd') { /* * Reset from alternate bank without changing * frequencies but with watchdog timer enabled. @@ -330,7 +330,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) read_from_px_regs_altbank(1); puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); set_px_go_with_watchdog(); - while(1); /* Not reached */ + while (1) ; /* Not reached */ } else { /* @@ -339,7 +339,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ read_from_px_regs(0); read_from_px_regs_altbank(0); - if(argc > 2) + if (argc > 2) goto my_usage; puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); set_altbank(); @@ -360,12 +360,14 @@ my_usage: puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } + /* * get_board_sys_clk * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ */ -unsigned long get_board_sys_clk(ulong dummy) +unsigned long +get_board_sys_clk(ulong dummy) { u8 i, go_bit, rd_clks; ulong val = 0; @@ -422,4 +424,3 @@ unsigned long get_board_sys_clk(ulong dummy) return val; } - diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c index f226b3e8d..964a17ca0 100644 --- a/board/mpc8641hpcn/pixis.c +++ b/board/mpc8641hpcn/pixis.c @@ -92,13 +92,13 @@ int set_px_sysclk(ulong sysclk) return 0; } - vclkh = (sysclk_s << 5) | sysclk_r ; + vclkh = (sysclk_s << 5) | sysclk_r; vclkl = sysclk_v; out8(PIXIS_BASE + PIXIS_VCLKH, vclkh); out8(PIXIS_BASE + PIXIS_VCLKL, vclkl); - out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux); + out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux); return 1; } @@ -118,7 +118,7 @@ int set_px_mpxpll(ulong mpxpll) case 12: case 14: case 16: - val = (u8)mpxpll; + val = (u8) mpxpll; break; default: printf("Unsupported MPXPLL ratio.\n"); @@ -245,19 +245,16 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* setting VCTL[WDEN] to 0 to disable watch dog */ tmp = in8(PIXIS_BASE + PIXIS_VCTL); - tmp &= ~ 0x08; + tmp &= ~0x08; out8(PIXIS_BASE + PIXIS_VCTL, tmp); return 0; } - U_BOOT_CMD( - diswd, 1, 0, disable_watchdog, - "diswd - Disable watchdog timer \n", - NULL -); - + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL); /* * This function takes the non-integral cpu:mpx pll ratio @@ -295,11 +292,11 @@ ulong strfractoint(uchar *strptr) if (no_dec) { /* Currently needed only for single digit corepll ratios */ - mulconst=10; + mulconst = 10; decval = 0; } else { j = 0; - i++; /* Skipping the decimal point */ + i++; /* Skipping the decimal point */ while ((strptr[i] > 47) && (strptr[i] < 58)) { decarr[j] = strptr[i]; i++; diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c index 733a57f93..74e2a3d46 100644 --- a/board/mpc8641hpcn/sys_eeprom.c +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -29,16 +29,16 @@ #ifdef CFG_ID_EEPROM typedef struct { - unsigned char id[4]; /* 0x0000 - 0x0003 */ - unsigned char sn[12]; /* 0x0004 - 0x000F */ - unsigned char errata[5];/* 0x0010 - 0x0014 */ - unsigned char date[7]; /* 0x0015 - 0x001a */ - unsigned char res_1[37];/* 0x001b - 0x003f */ - unsigned char tab_size; /* 0x0040 */ - unsigned char tab_flag; /* 0x0041 */ - unsigned char mac[8][6];/* 0x0042 - 0x0071 */ - unsigned char res_2[126];/* 0x0072 - 0x00ef */ - unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ + unsigned char id[4]; /* 0x0000 - 0x0003 */ + unsigned char sn[12]; /* 0x0004 - 0x000F */ + unsigned char errata[5]; /* 0x0010 - 0x0014 */ + unsigned char date[7]; /* 0x0015 - 0x001a */ + unsigned char res_1[37]; /* 0x001b - 0x003f */ + unsigned char tab_size; /* 0x0040 */ + unsigned char tab_flag; /* 0x0041 */ + unsigned char mac[8][6]; /* 0x0042 - 0x0071 */ + unsigned char res_2[126]; /* 0x0072 - 0x00ef */ + unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ } EEPROM_data; static EEPROM_data mac_data; @@ -48,30 +48,34 @@ int mac_show(void) int i; unsigned char ethaddr[8][18]; - printf("ID %c%c%c%c\n", mac_data.id[0],\ - mac_data.id[1],\ - mac_data.id[2],\ - mac_data.id[3]); - printf("Errata %c%c%c%c%c\n", mac_data.errata[0],\ - mac_data.errata[1],\ - mac_data.errata[2],\ - mac_data.errata[3],\ - mac_data.errata[4]); - printf("Date %c%c%c%c%c%c%c\n", mac_data.date[0],\ - mac_data.date[1],\ - mac_data.date[2],\ - mac_data.date[3],\ - mac_data.date[4],\ - mac_data.date[5],\ - mac_data.date[6]); + printf("ID %c%c%c%c\n", + mac_data.id[0], + mac_data.id[1], + mac_data.id[2], + mac_data.id[3]); + printf("Errata %c%c%c%c%c\n", + mac_data.errata[0], + mac_data.errata[1], + mac_data.errata[2], + mac_data.errata[3], + mac_data.errata[4]); + printf("Date %c%c%c%c%c%c%c\n", + mac_data.date[0], + mac_data.date[1], + mac_data.date[2], + mac_data.date[3], + mac_data.date[4], + mac_data.date[5], + mac_data.date[6]); for (i = 0; i < 8; i++) { - sprintf(ethaddr[i],"%02x:%02x:%02x:%02x:%02x:%02x",\ - mac_data.mac[i][0],\ - mac_data.mac[i][1],\ - mac_data.mac[i][2],\ - mac_data.mac[i][3],\ - mac_data.mac[i][4],\ - mac_data.mac[i][5]); + sprintf(ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], + mac_data.mac[i][5]); printf("MAC %d %s\n", i, ethaddr[i]); } @@ -85,7 +89,7 @@ int mac_show(void) int mac_read(void) { - int ret,length; + int ret, length; unsigned int crc = 0; unsigned char dev = ID_EEPROM_ADDR, *data; @@ -98,12 +102,12 @@ int mac_read(void) data = (unsigned char *)(&mac_data); printf("Check CRC on reading ..."); - crc = crc32(crc, data, length-4); + crc = crc32(crc, data, length - 4); if (crc != mac_data.crc) { - printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",mac_data.crc,crc); + printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n", + mac_data.crc, crc); return -1; - } - else { + } else { printf("CRC OK\n"); mac_show(); } @@ -114,94 +118,97 @@ int mac_prog(void) { int ret, i, length; unsigned int crc = 0; - unsigned char dev = ID_EEPROM_ADDR,*ptr; - unsigned char * eeprom_data = (unsigned char *)(&mac_data); + unsigned char dev = ID_EEPROM_ADDR, *ptr; + unsigned char *eeprom_data = (unsigned char *)(&mac_data); for (i = 0; i < sizeof(mac_data.res_1); i++) mac_data.res_1[i] = 0; - for (i = 0;i < sizeof(mac_data.res_2); i++) + for (i = 0; i < sizeof(mac_data.res_2); i++) mac_data.res_2[i] = 0; length = sizeof(EEPROM_data); - crc = crc32 (crc, eeprom_data, length-4); + crc = crc32(crc, eeprom_data, length - 4); mac_data.crc = crc; for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { - ret = i2c_write(dev, i, 1, ptr, (length-i) <8 ? (length-i) : 8); - udelay(5000); /* 5ms write cycle timing */ + ret = + i2c_write(dev, i, 1, ptr, + (length - i) < 8 ? (length - i) : 8); + udelay(5000); /* 5ms write cycle timing */ if (ret) break; } if (ret) { printf("Programming failed.\n"); return -1; - } - else { - printf("Programming %d bytes. Reading back ...\n",length); + } else { + printf("Programming %d bytes. Reading back ...\n", length); mac_read(); } return 0; } -int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i; char cmd = 's'; unsigned long long mac_val; - if(i2c_probe(ID_EEPROM_ADDR) != 0) + if (i2c_probe(ID_EEPROM_ADDR) != 0) return -1; - if(argc>1) { + if (argc > 1) { cmd = argv[1][0]; switch (cmd) { - case 'r': /* display */ - mac_read(); - break; - case 's': /* save */ - mac_prog(); - break; - case 'i': /* id */ - for (i=0; i<4; i++) { - mac_data.id[i] = argv[2][i]; - } - break; - case 'n': /* serial number */ - for (i=0; i<12; i++) { - mac_data.sn[i] = argv[2][i]; - } - break; - case 'e': /* errata */ - for (i=0; i<5; i++) { - mac_data.errata[i] = argv[2][i]; - } - break; - case 'd': /* date */ - for (i=0; i<7; i++) { - mac_data.date[i] = argv[2][i]; - } - break; - case 'p': /* number of ports */ - mac_data.tab_size = (unsigned char)simple_strtoul(argv[2],NULL,16); - break; - case '0': /* mac 0 */ - case '1': /* mac 1 */ - case '2': /* mac 2 */ - case '3': /* mac 3 */ - case '4': /* mac 4 */ - case '5': /* mac 5 */ - case '6': /* mac 6 */ - case '7': /* mac 7 */ - mac_val = simple_strtoull(argv[2],NULL,16); - for (i=0; i<6; i++) { - mac_data.mac[cmd-'0'][i] = *((unsigned char *)(((unsigned int)(&mac_val))+i+2)); - } - break; - case 'h': /* help */ - default: - printf ("Usage:\n%s\n", cmdtp->usage); - break; + case 'r': /* display */ + mac_read(); + break; + case 's': /* save */ + mac_prog(); + break; + case 'i': /* id */ + for (i = 0; i < 4; i++) { + mac_data.id[i] = argv[2][i]; + } + break; + case 'n': /* serial number */ + for (i = 0; i < 12; i++) { + mac_data.sn[i] = argv[2][i]; + } + break; + case 'e': /* errata */ + for (i = 0; i < 5; i++) { + mac_data.errata[i] = argv[2][i]; + } + break; + case 'd': /* date */ + for (i = 0; i < 7; i++) { + mac_data.date[i] = argv[2][i]; + } + break; + case 'p': /* number of ports */ + mac_data.tab_size = + (unsigned char)simple_strtoul(argv[2], NULL, 16); + break; + case '0': /* mac 0 */ + case '1': /* mac 1 */ + case '2': /* mac 2 */ + case '3': /* mac 3 */ + case '4': /* mac 4 */ + case '5': /* mac 5 */ + case '6': /* mac 6 */ + case '7': /* mac 7 */ + mac_val = simple_strtoull(argv[2], NULL, 16); + for (i = 0; i < 6; i++) { + mac_data.mac[cmd - '0'][i] = + *((unsigned char *) + (((unsigned int)(&mac_val)) + i + 2)); + } + break; + case 'h': /* help */ + default: + printf("Usage:\n%s\n", cmdtp->usage); + break; } - } - else { + } else { mac_show(); } return 0; @@ -209,36 +216,41 @@ int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int mac_read_from_eeprom(void) { - int length,i; - unsigned char dev = ID_EEPROM_ADDR, *data, ethaddr[4][18], enetvar[32]; + int length, i; + unsigned char dev = ID_EEPROM_ADDR; + unsigned char *data; + unsigned char ethaddr[4][18]; + unsigned char enetvar[32]; unsigned int crc = 0; length = sizeof(EEPROM_data); - if(i2c_read (dev, 0, 1, (unsigned char *)(&mac_data), length)) { + if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) { printf("Read failed.\n"); return -1; } data = (unsigned char *)(&mac_data); - crc = crc32(crc, data, length-4); + crc = crc32(crc, data, length - 4); if (crc != mac_data.crc) { return -1; - } - else { - for(i=0; i<4; i++) { - if(memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { - sprintf(ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", \ - mac_data.mac[i][0], \ - mac_data.mac[i][1], \ - mac_data.mac[i][2], \ - mac_data.mac[i][3], \ - mac_data.mac[i][4], \ + } else { + for (i = 0; i < 4; i++) { + if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { + sprintf(ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], mac_data.mac[i][5]); - sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + sprintf(enetvar, + i ? "eth%daddr" : "ethaddr", + i); setenv(enetvar, ethaddr[i]); } } } return 0; } -#endif /* CFG_ID_EEPROM */ +#endif /* CFG_ID_EEPROM */ From 2c33e8a1c535b3ae91cf0b284480600bf3f57c57 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 17:54:05 -0500 Subject: [PATCH 069/101] Cleanup poorly introduced whitespace. --- include/asm-ppc/mmu.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 612b5df48..4f49789f6 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -435,8 +435,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_4GB 11 #if defined(CONFIG_MPC86xx) -#define LAWBAR_BASE_ADDR 0x00FFFFFF -#define LAWAR_TRGT_IF 0x01F00000 +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 #else #define LAWBAR_BASE_ADDR 0x000FFFFF #define LAWAR_TRGT_IF 0x00F00000 @@ -448,14 +448,14 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_HT 0x00200000 +#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 -#define LAWAR_TRGT_IF_DDR1 0x00f00000 -#define LAWAR_TRGT_IF_DDR2 0x01600000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -478,9 +478,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) -#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) -#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) -#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) -#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) #endif /* _PPC_MMU_H_ */ From ae6241685cbcf0c79a3636530d2ceab1fb291a94 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 18:07:00 -0500 Subject: [PATCH 070/101] Cleanup more poorly introduced whitespace. --- include/asm-ppc/processor.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 1848aaf8c..0060cd030 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -264,7 +264,7 @@ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ -#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ @@ -445,7 +445,7 @@ #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCRO 0x3f6 +#define SPRN_MSSCRO 0x3f6 #endif @@ -507,12 +507,12 @@ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ -#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO +#define MSSCR0 SPRN_MSSCRO #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR @@ -548,7 +548,7 @@ #define CSRR0 SPRN_CSRR0 #define CSRR1 SPRN_CSRR1 #define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG +#define USPRG0 SPRN_USPRG #define SPRG4R SPRN_SPRG4R #define SPRG5R SPRN_SPRG5R #define SPRG6R SPRN_SPRG6R From b93775c2036b99baa390ea425c4771895bbc63c4 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 18:26:08 -0500 Subject: [PATCH 071/101] Cleanup even more poorly introduced whitespace. --- include/mpc86xx.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 4edeae164..bc8ba3f2d 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -1,6 +1,6 @@ /* * Copyright 2006 Freescale Semiconductor. - * Jeffrey Brown (jeffrey@freescale.com) + * Jeffrey Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) */ @@ -70,10 +70,9 @@ #ifndef __ASSEMBLY__ -typedef struct -{ - unsigned long freqProcessor; - unsigned long freqSystemBus; +typedef struct { + unsigned long freqProcessor; + unsigned long freqSystemBus; } MPC86xx_SYS_INFO; #define l1icache_enable icache_enable @@ -115,5 +114,3 @@ static __inline__ unsigned long get_l2cr (void) #endif /* _ASMLANGUAGE */ #endif /* __MPC86xx_H__ */ - - From d8ea2acf5f137cae99417df4f573d036ee384668 Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Wed, 23 Aug 2006 17:54:32 +0800 Subject: [PATCH 072/101] Add dtb boot-up parameter to default boot commands. Signed-off-by: Zhang Wei --- include/configs/MPC8641HPCN.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 200a38f3e..1f5e2dfd9 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -595,6 +595,8 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=400000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ + "dtbaddr=2000000\0" \ + "dtbfile=mpc8641_hpcn.dtb\0" \ "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ @@ -611,14 +613,16 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND From 4782ac80b02f0d01afd309e2200dd3c7037f2ba4 Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 23 Aug 2006 19:10:44 +0800 Subject: [PATCH 073/101] Add AHCI support to u-boot Add AHCI support in u-boot, enable the sata disk controllers which following the AHCI protocol. Signed-off-by:Jason Jin --- common/cmd_scsi.c | 7 +- drivers/Makefile | 2 +- drivers/ahci.c | 706 ++++++++++++++++++++++++++++++++++++++++++++++ include/ahci.h | 190 +++++++++++++ 4 files changed, 903 insertions(+), 2 deletions(-) create mode 100644 drivers/ahci.c create mode 100644 include/ahci.h diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index e8048611f..cc08743d5 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -43,8 +43,13 @@ #else #define SCSI_DEV_ID CONFIG_SCSI_DEV_ID #endif +#elif defined CONFIG_SATA_ULI5288 + +#define SCSI_VEND_ID 0x10b9 +#define SCSI_DEV_ID 0x5288 + #else -#error CONFIG_SCSI_SYM53C8XX must be defined +#error no scsi device defined #endif diff --git a/drivers/Makefile b/drivers/Makefile index e6176ed86..98c4ef95f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -44,7 +44,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ - status_led.o sym53c8xx.o \ + status_led.o sym53c8xx.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ videomodes.o w83c553f.o \ diff --git a/drivers/ahci.c b/drivers/ahci.c new file mode 100644 index 000000000..828498ddc --- /dev/null +++ b/drivers/ahci.c @@ -0,0 +1,706 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference on libata and ahci drvier in kernel + * + */ +#include + +#ifdef CONFIG_SCSI_AHCI + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ahci_probe_ent *probe_ent = NULL; +hd_driveid_t *ataid[AHCI_MAX_PORTS]; + +#define writel_with_flush(a,b) do{writel(a,b);readl(b);}while(0) + +static inline u32 ahci_port_base(u32 base, u32 port) +{ + return base + 0x100 + (port * 0x80); +} + + +static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, + unsigned int port_idx) +{ + base = ahci_port_base(base, port_idx); + + port->cmd_addr = base; + port->scr_addr = base + PORT_SCR; +} + + +#define msleep(a) udelay(a * 1000) +#define ssleep(a) msleep(a * 1000) +static int waiting_for_cmd_completed(volatile u8 *offset, int timeout_msec, u32 sign) +{ + int i; + u32 status; + for(i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) + msleep(1); + + return (i < timeout_msec)? 0 : -1; +} + + +static int ahci_host_init(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 tmp, cap_save; + u16 tmp16; + int i, j; + volatile u8* port_mmio; + unsigned short vendor; + + cap_save = readl(mmio + HOST_CAP); + cap_save &= ( (1<<28) | (1<<17) ); + cap_save |= (1 << 27); + + /* global controller reset */ + tmp = readl(mmio + HOST_CTL); + if ((tmp & HOST_RESET) == 0) + writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); + + /* reset must complete within 1 second, or + * the hardware should be considered fried. + */ + ssleep(1); + + tmp = readl(mmio + HOST_CTL); + if (tmp & HOST_RESET) { + debug("controller reset failed (0x%x)\n", tmp); + return -1; + } + + writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); + writel(cap_save, mmio + HOST_CAP); + writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); + + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + + if (vendor == PCI_VENDOR_ID_INTEL) { + u16 tmp16; + pci_read_config_word(pdev, 0x92, &tmp16); + tmp16 |= 0xf; + pci_write_config_word(pdev, 0x92, tmp16); + } + + probe_ent->cap = readl(mmio + HOST_CAP); + probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; + + debug("cap 0x%x port_map 0x%x n_ports %d\n", + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + + for (i = 0; i < probe_ent->n_ports; i++) { + probe_ent->port[i].port_mmio = ahci_port_base((u32)mmio, i); + port_mmio = (u8 *)probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], + (unsigned long) mmio, i); + + /* make sure port is not active */ + tmp = readl(port_mmio + PORT_CMD); + if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START)) { + tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START); + writel_with_flush(tmp, port_mmio + PORT_CMD); + + /* spec says 500 msecs for each bit, so + * this is slightly incorrect. + */ + msleep(500); + } + + writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); + + j = 0; + while (j < 100) { + msleep(10); + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + break; + j++; + } + + tmp = readl(port_mmio + PORT_SCR_ERR); + debug("PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* ack any pending irq events for this port */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + debug("PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << i, mmio + HOST_IRQ_STAT); + + /* set irq mask (enables interrupts) */ + writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); + + /*register linkup ports*/ + tmp = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: 0x%x\n",i,tmp); + if((tmp & 0xf) == 0x03) + probe_ent->link_port_map |= (0x01<< i); + } + + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + + pci_read_config_word(pdev, PCI_COMMAND, &tmp16); + tmp |= PCI_COMMAND_MASTER; + pci_write_config_word(pdev, PCI_COMMAND, tmp16); + + return 0; +} + + +static void ahci_print_info(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8* mmio = (volatile u8 *)probe_ent->mmio_base; + u32 vers, cap, impl, speed; + const char *speed_s; + u16 cc; + const char *scc_s; + + vers = readl(mmio + HOST_VERSION); + cap = probe_ent->cap; + impl = probe_ent->port_map; + + speed = (cap >> 20) & 0xf; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else + speed_s = "?"; + + pci_read_config_word(pdev, 0x0a, &cc); + if (cc == 0x0101) + scc_s = "IDE"; + else if (cc == 0x0106) + scc_s = "SATA"; + else if (cc == 0x0104) + scc_s = "RAID"; + else + scc_s = "unknown"; + + printf( "AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n" + , + + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + + ((cap >> 8) & 0x1f) + 1, + (cap & 0x1f) + 1, + speed_s, + impl, + scc_s); + + printf("flags: " + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n" + , + + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : "" + ); +} + + +static int ahci_init_one (pci_dev_t pdev) +{ + u32 iobase, vendor; + int rc; + + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); + + probe_ent = malloc(sizeof(probe_ent)); + memset(probe_ent, 0, sizeof(probe_ent)); + probe_ent->dev = pdev; + + pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); + iobase &= ~0xf; + + probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6*/ + + probe_ent->mmio_base = iobase; + + /* Take from kernel: + * JMicron-specific fixup: + * make sure we're in AHCI mode + */ + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + if(vendor == 0x197b) + pci_write_config_byte(pdev, 0x41, 0xa1); + + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + + return 0; + +err_out: + return rc; +} + + +#define MAX_DATA_BYTE_COUNT (4*1024*1024) +static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + u32 sg_count; + int i; + + sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; + if(sg_count > AHCI_MAX_SG){ + printf("Error:Too much sg!\n"); + return -1; + } + + for(i = 0;i < sg_count; i++) + { + ahci_sg->addr = cpu_to_le32((u32)buf + i * MAX_DATA_BYTE_COUNT); + ahci_sg->addr_hi = 0; + ahci_sg->flags_size = cpu_to_le32( 0x3fffff & + (buf_len < MAX_DATA_BYTE_COUNT + ? (buf_len - 1) + : (MAX_DATA_BYTE_COUNT - 1))); + ahci_sg++; + buf_len -= MAX_DATA_BYTE_COUNT; + } + + return sg_count; +} + + +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) +{ + pp->cmd_slot->opts = cpu_to_le32(opts); + pp->cmd_slot->status = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr_hi = 0; +} + + +static void ahci_set_feature(u8 port) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ + u8 fis[20]; + + /*set feature*/ + memset(fis,0,20); + fis[0] = 0x27; + fis[1] = 1 << 7; + fis[2] = ATA_CMD_SETF; + fis[3] = SETFEATURES_XFER; + fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; + + memcpy((unsigned char *)pp->cmd_tbl,fis,20); + ahci_fill_cmd_slot(pp, cmd_fis_len); + writel(1, port_mmio + PORT_CMD_ISSUE); + readl(port_mmio + PORT_CMD_ISSUE); + + if(waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("set feature error!\n"); + } +} + + +static int ahci_port_start(u8 port) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 port_status; + u32 mem; + + debug("Enter start port: %d\n",port); + port_status = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: %x\n",port,port_status); + if((port_status & 0xf) != 0x03){ + printf("No Link on this port!\n"); + return -1; + } + + mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + if (!mem) { + free(pp); + printf("No mem for table!\n"); + return -ENOMEM; + } + + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + + memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + debug("cmd_slot = 0x%x\n",pp->cmd_slot); + + mem += (AHCI_CMD_SLOT_SZ + 224); + /* + * Second item: Received-FIS area + */ + pp->rx_fis = mem; + + mem += AHCI_RX_FIS_SZ; + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ + pp->cmd_tbl = mem; + debug("cmd_tbl_dma = 0x%x\n",pp->cmd_tbl); + + mem += AHCI_CMD_TBL_HDR; + pp->cmd_tbl_sg = (struct ahci_sg *)mem; + + writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); + + writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + + writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, port_mmio + PORT_CMD); + + debug("Exit start port %d\n",port); + + return 0; +} + + +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + u32 opts; + u32 port_status; + int sg_count; + + debug("Enter get_ahci_device_data: for port %d\n",port); + + if(port > probe_ent->n_ports){ + printf("Invaild port number %d\n", port); + return -1; + } + + port_status = readl(port_mmio + PORT_SCR_STAT); + if((port_status & 0xf) != 0x03){ + debug("No Link on port %d!\n",port); + return -1; + } + + memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); + + sg_count = ahci_fill_sg(port,buf,buf_len); + opts = (fis_len >> 2) | (sg_count << 16) ; + ahci_fill_cmd_slot(pp, opts); + + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("timeout exit!\n"); + return -1; + } + debug("get_ahci_device_data: %d byte transferred.\n", + pp->cmd_slot->status); + + return 0; +} + + +static char *ata_id_strcpy(u16 *target, u16 *src, int len) +{ + int i; + for(i = 0; i < len / 2; i++) + target[i] = le16_to_cpu(src[i]); + return (char *)target; +} + + +static void dump_ataid(hd_driveid_t *ataid) +{ + debug("(49)ataid->capability = 0x%x\n", ataid->capability); + debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); + debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); + debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); + debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); + debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); + debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); + debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); + debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); + debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); + debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); + debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); + debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); + debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); + debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); +} + +/* + * SCSI INQUIRY command operation. + */ +static int ata_scsiop_inquiry(ccb *pccb) +{ + u8 hdr[] = { + 0, + 0, + 0x5, /* claim SPC-3 version compatibility */ + 2, + 95 - 4, + }; + u8 fis[20]; + u8 *tmpid; + u8 port; + + /* Clean ccb data buffer */ + memset(pccb->pdata, 0, pccb->datalen); + + memcpy(pccb->pdata, hdr, sizeof(hdr)); + + if(pccb->datalen <= 35) + return 0; + + memset(fis, 0, 20); + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_IDENT; /* Command byte. */ + + /* Read id from sata */ + port = pccb->target; + if(!(tmpid = malloc(sizeof(hd_driveid_t)))) + return -ENOMEM; + + if(get_ahci_device_data(port, (u8 *)&fis, 20, + tmpid, sizeof(hd_driveid_t))){ + debug("scsi_ahci: SCSI inquiry command failure.\n"); + return -EIO; + } + + if(ataid[port]) + free(ataid[port]); + ataid[port] = (hd_driveid_t *)tmpid; + + memcpy(&pccb->pdata[8], "ATA ", 8); + ata_id_strcpy((u16 *)&pccb->pdata[16], (u16 *)ataid[port]->model, 16); + ata_id_strcpy((u16 *)&pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + + dump_ataid(ataid[port]); + return 0; +} + + +/* + * SCSI READ10 command operation. + */ +static int ata_scsiop_read10(ccb *pccb) +{ + u64 lba = 0; + u32 len = 0; + u8 fis[20]; + + lba = (((u64)pccb->cmd[2]) << 24) | (((u64)pccb->cmd[3]) << 16) + | (((u64)pccb->cmd[4]) << 8) | ((u64)pccb->cmd[5]); + len = (((u32)pccb->cmd[7]) << 8) | ((u32)pccb->cmd[8]); + + /* For 10-byte and 16-byte SCSI R/W commands, transfer + * length 0 means transfer 0 block of data. + * However, for ATA R/W commands, sector count 0 means + * 256 or 65536 sectors, not 0 sectors as in SCSI. + * + * WARNING: one or two older ATA drives treat 0 as 0... + */ + if(!len) return 0; + memset(fis, 0, 20); + + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ + + /* LBA address, only support LBA28 in this driver*/ + fis[4] = pccb->cmd[5]; + fis[5] = pccb->cmd[4]; + fis[6] = pccb->cmd[3]; + fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; + + /* Sector Count */ + fis[12] = pccb->cmd[8]; + fis[13] = pccb->cmd[7]; + + /* Read from ahci */ + if(get_ahci_device_data(pccb->target, (u8*)&fis, 20, + pccb->pdata, pccb->datalen)){ + debug("scsi_ahci: SCSI READ10 command failure.\n"); + return -EIO; + } + + return 0; +} + + +/* + * SCSI READ CAPACITY10 command operation. + */ +static int ata_scsiop_read_capacity10(ccb *pccb) +{ + u8 buf[8]; + + if(!ataid[pccb->target]) { + printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); + return -EPERM; + } + + memset(buf, 0, 8); + + *(u32 *)buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); + + buf[6] = 512 >> 8; + buf[7] = 512 & 0xff; + + memcpy(pccb->pdata, buf, 8); + + return 0; +} + + +/* + * SCSI TEST UNIT READY command operation. + */ +static int ata_scsiop_test_unit_ready(ccb *pccb) +{ + return (ataid[pccb->target]) ? 0 : -EPERM; +} + +int scsi_exec(ccb *pccb) +{ + int ret; + + switch(pccb->cmd[0]) { + case SCSI_READ10: + ret = ata_scsiop_read10(pccb); + break; + case SCSI_RD_CAPAC: + ret = ata_scsiop_read_capacity10(pccb); + break; + case SCSI_TST_U_RDY: + ret = ata_scsiop_test_unit_ready(pccb); + break; + case SCSI_INQUIRY: + ret = ata_scsiop_inquiry(pccb); + break; + default: + printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); + return FALSE; + } + + if(ret) { + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0],ret); + return FALSE; + } + return TRUE; + +} + + +void scsi_low_level_init(int busdevfunc) +{ + int i; + u32 linkmap; + + ahci_init_one(busdevfunc); + + linkmap = probe_ent->link_port_map; + + for(i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++){ + if( ((linkmap >> i) & 0x01) ){ + if(ahci_port_start((u8)i)){ + printf("Can not start port %d\n",i); + continue; + } + ahci_set_feature((u8)i); + } + } +} + + +void scsi_bus_reset(void) +{ +/*Not implement*/ +} + + +void scsi_print_error(ccb *pccb) +{ +/*The ahci error info can be read in the ahci driver*/ +} +#endif diff --git a/include/ahci.h b/include/ahci.h new file mode 100644 index 000000000..80701e298 --- /dev/null +++ b/include/ahci.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _AHCI_H_ +#define _AHCI_H_ + +#define AHCI_PCI_BAR 0x24 +#define AHCI_MAX_SG 56 /* hardware max is 64K */ +#define AHCI_CMD_SLOT_SZ 32 +#define AHCI_RX_FIS_SZ 256 +#define AHCI_CMD_TBL_HDR 0x80 +#define AHCI_CMD_TBL_CDB 0x40 +#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) +#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ + + AHCI_RX_FIS_SZ +#define AHCI_CMD_ATAPI (1 << 5) +#define AHCI_CMD_WRITE (1 << 6) +#define AHCI_CMD_PREFETCH (1 << 7) +#define AHCI_CMD_RESET (1 << 8) +#define AHCI_CMD_CLR_BUSY (1 << 10) + +#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ + +/* Global controller registers */ +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ +#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ + +/* HOST_CTL bits */ +#define HOST_RESET (1 << 0) /* reset controller; self-clear */ +#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ +#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ + +/* Registers for each SATA port */ +#define PORT_LST_ADDR 0x00 /* command list DMA addr */ +#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ +#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ +#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ +#define PORT_IRQ_STAT 0x10 /* interrupt status */ +#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ +#define PORT_CMD 0x18 /* port command */ +#define PORT_TFDATA 0x20 /* taskfile data */ +#define PORT_SIG 0x24 /* device TF signature */ +#define PORT_CMD_ISSUE 0x38 /* command issue */ +#define PORT_SCR 0x28 /* SATA phy register block */ +#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ +#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ +#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ +#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ + +/* PORT_IRQ_{STAT,MASK} bits */ +#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ +#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ +#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ +#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ +#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ +#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ +#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ +#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ + +#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ +#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ +#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ +#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ +#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ +#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ +#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ +#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ +#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ + +#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ + | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR + +#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ + | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ + | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ + | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ + | PORT_IRQ_D2H_REG_FIS + +/* PORT_CMD bits */ +#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ +#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ +#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ +#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ +#define PORT_CMD_CLO (1 << 3) /* Command list override */ +#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ +#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ +#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ + +#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ +#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ +#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ + +#define AHCI_MAX_PORTS 32 + +/* SETFEATURES stuff */ +#define SETFEATURES_XFER 0x03 +#define XFER_UDMA_7 0x47 +#define XFER_UDMA_6 0x46 +#define XFER_UDMA_5 0x45 +#define XFER_UDMA_4 0x44 +#define XFER_UDMA_3 0x43 +#define XFER_UDMA_2 0x42 +#define XFER_UDMA_1 0x41 +#define XFER_UDMA_0 0x40 +#define XFER_MW_DMA_2 0x22 +#define XFER_MW_DMA_1 0x21 +#define XFER_MW_DMA_0 0x20 +#define XFER_SW_DMA_2 0x12 +#define XFER_SW_DMA_1 0x11 +#define XFER_SW_DMA_0 0x10 +#define XFER_PIO_4 0x0C +#define XFER_PIO_3 0x0B +#define XFER_PIO_2 0x0A +#define XFER_PIO_1 0x09 +#define XFER_PIO_0 0x08 +#define XFER_PIO_SLOW 0x00 + +#define ATA_FLAG_SATA (1 << 3) +#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ +#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ +#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ +#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ +#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ + +struct ahci_cmd_hdr { + u32 opts; + u32 status; + u32 tbl_addr; + u32 tbl_addr_hi; + u32 reserved[4]; +}; + +struct ahci_sg { + u32 addr; + u32 addr_hi; + u32 reserved; + u32 flags_size; +}; + +struct ahci_ioports { + u32 cmd_addr; + u32 scr_addr; + u32 port_mmio; + struct ahci_cmd_hdr *cmd_slot; + struct ahci_sg *cmd_tbl_sg; + u32 cmd_tbl; + u32 rx_fis; +}; + +struct ahci_probe_ent { + pci_dev_t dev; + struct ahci_ioports port[AHCI_MAX_PORTS]; + u32 n_ports; + u32 hard_port_no; + u32 host_flags; + u32 host_set_flags; + u32 mmio_base; + u32 pio_mask; + u32 udma_mask; + u32 flags; + u32 cap; /* cache of HOST_CAP register */ + u32 port_map; /* cache of HOST_PORTS_IMPL reg */ + u32 link_port_map; /*linkup port map*/ +}; + +#endif From dabf9ef8c10b4dead5ef2106ef742b1c06b542de Mon Sep 17 00:00:00 2001 From: Jin Zhengxiong Date: Wed, 23 Aug 2006 19:15:12 +0800 Subject: [PATCH 074/101] Add AHCI define and sata support for MPC8641HPCN board. Signed-off-by:Jason Jin --- include/configs/MPC8641HPCN.h | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 1f5e2dfd9..7097b3eee 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -340,6 +340,17 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + #endif /* CONFIG_PCI */ @@ -477,7 +488,9 @@ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) \ & \ ~(CFG_CMD_ENV \ | CFG_CMD_IMLS \ @@ -486,7 +499,9 @@ #else #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | CFG_CMD_PING \ - | CFG_CMD_I2C) \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CGF_CMD_EXT2) \ & \ ~(CFG_CMD_ENV \ | CFG_CMD_IMLS \ @@ -498,7 +513,9 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PCI \ | CFG_CMD_PING \ - | CFG_CMD_I2C) + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) #else #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PING \ From 4a7cc0f21918e6ecf07ed57075d67df2c4a1299c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 23 Aug 2006 11:04:43 -0500 Subject: [PATCH 075/101] Cleanup and lindent new AHCI driver. --- drivers/ahci.c | 280 ++++++++++++++++++++++++------------------------- 1 file changed, 138 insertions(+), 142 deletions(-) diff --git a/drivers/ahci.c b/drivers/ahci.c index 828498ddc..8ceff0092 100644 --- a/drivers/ahci.c +++ b/drivers/ahci.c @@ -42,7 +42,8 @@ struct ahci_probe_ent *probe_ent = NULL; hd_driveid_t *ataid[AHCI_MAX_PORTS]; -#define writel_with_flush(a,b) do{writel(a,b);readl(b);}while(0) +#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) + static inline u32 ahci_port_base(u32 base, u32 port) { @@ -55,21 +56,25 @@ static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, { base = ahci_port_base(base, port_idx); - port->cmd_addr = base; - port->scr_addr = base + PORT_SCR; + port->cmd_addr = base; + port->scr_addr = base + PORT_SCR; } #define msleep(a) udelay(a * 1000) #define ssleep(a) msleep(a * 1000) -static int waiting_for_cmd_completed(volatile u8 *offset, int timeout_msec, u32 sign) + +static int waiting_for_cmd_completed(volatile u8 *offset, + int timeout_msec, + u32 sign) { int i; u32 status; - for(i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) + + for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) msleep(1); - return (i < timeout_msec)? 0 : -1; + return (i < timeout_msec) ? 0 : -1; } @@ -80,11 +85,11 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) u32 tmp, cap_save; u16 tmp16; int i, j; - volatile u8* port_mmio; + volatile u8 *port_mmio; unsigned short vendor; cap_save = readl(mmio + HOST_CAP); - cap_save &= ( (1<<28) | (1<<17) ); + cap_save &= ((1 << 28) | (1 << 17)); cap_save |= (1 << 27); /* global controller reset */ @@ -121,13 +126,12 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; debug("cap 0x%x port_map 0x%x n_ports %d\n", - probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); for (i = 0; i < probe_ent->n_ports; i++) { - probe_ent->port[i].port_mmio = ahci_port_base((u32)mmio, i); - port_mmio = (u8 *)probe_ent->port[i].port_mmio; - ahci_setup_port(&probe_ent->port[i], - (unsigned long) mmio, i); + probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); + port_mmio = (u8 *) probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); /* make sure port is not active */ tmp = readl(port_mmio + PORT_CMD); @@ -169,11 +173,11 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) /* set irq mask (enables interrupts) */ writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); - /*register linkup ports*/ + /*register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); - debug("Port %d status: 0x%x\n",i,tmp); - if((tmp & 0xf) == 0x03) - probe_ent->link_port_map |= (0x01<< i); + debug("Port %d status: 0x%x\n", i, tmp); + if ((tmp & 0xf) == 0x03) + probe_ent->link_port_map |= (0x01 << i); } tmp = readl(mmio + HOST_CTL); @@ -193,7 +197,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) static void ahci_print_info(struct ahci_probe_ent *probe_ent) { pci_dev_t pdev = probe_ent->dev; - volatile u8* mmio = (volatile u8 *)probe_ent->mmio_base; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; u32 vers, cap, impl, speed; const char *speed_s; u16 cc; @@ -221,50 +225,38 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) else scc_s = "unknown"; - printf( "AHCI %02x%02x.%02x%02x " - "%u slots %u ports %s Gbps 0x%x impl %s mode\n" - , - - (vers >> 24) & 0xff, - (vers >> 16) & 0xff, - (vers >> 8) & 0xff, - vers & 0xff, - - ((cap >> 8) & 0x1f) + 1, - (cap & 0x1f) + 1, - speed_s, - impl, - scc_s); + printf("AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n", + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); printf("flags: " - "%s%s%s%s%s%s" - "%s%s%s%s%s%s%s\n" - , - - cap & (1 << 31) ? "64bit " : "", - cap & (1 << 30) ? "ncq " : "", - cap & (1 << 28) ? "ilck " : "", - cap & (1 << 27) ? "stag " : "", - cap & (1 << 26) ? "pm " : "", - cap & (1 << 25) ? "led " : "", - - cap & (1 << 24) ? "clo " : "", - cap & (1 << 19) ? "nz " : "", - cap & (1 << 18) ? "only " : "", - cap & (1 << 17) ? "pmp " : "", - cap & (1 << 15) ? "pio " : "", - cap & (1 << 14) ? "slum " : "", - cap & (1 << 13) ? "part " : "" - ); + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n", + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : ""); } - -static int ahci_init_one (pci_dev_t pdev) +static int ahci_init_one(pci_dev_t pdev) { u32 iobase, vendor; int rc; - memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); probe_ent = malloc(sizeof(probe_ent)); memset(probe_ent, 0, sizeof(probe_ent)); @@ -273,20 +265,22 @@ static int ahci_init_one (pci_dev_t pdev) pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); iobase &= ~0xf; - probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY - | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA - | ATA_FLAG_NO_ATAPI; - probe_ent->pio_mask = 0x1f; - probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6*/ + probe_ent->host_flags = ATA_FLAG_SATA + | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO + | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ - probe_ent->mmio_base = iobase; + probe_ent->mmio_base = iobase; /* Take from kernel: * JMicron-specific fixup: * make sure we're in AHCI mode */ pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); - if(vendor == 0x197b) + if (vendor == 0x197b) pci_write_config_byte(pdev, 0x41, 0xa1); /* initialize adapter */ @@ -298,34 +292,34 @@ static int ahci_init_one (pci_dev_t pdev) return 0; -err_out: + err_out: return rc; } #define MAX_DATA_BYTE_COUNT (4*1024*1024) + static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) { - struct ahci_ioports *pp = &(probe_ent->port[port]); struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; u32 sg_count; int i; sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; - if(sg_count > AHCI_MAX_SG){ + if (sg_count > AHCI_MAX_SG) { printf("Error:Too much sg!\n"); return -1; } - for(i = 0;i < sg_count; i++) - { - ahci_sg->addr = cpu_to_le32((u32)buf + i * MAX_DATA_BYTE_COUNT); + for (i = 0; i < sg_count; i++) { + ahci_sg->addr = + cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); ahci_sg->addr_hi = 0; - ahci_sg->flags_size = cpu_to_le32( 0x3fffff & - (buf_len < MAX_DATA_BYTE_COUNT - ? (buf_len - 1) - : (MAX_DATA_BYTE_COUNT - 1))); + ahci_sg->flags_size = cpu_to_le32(0x3fffff & + (buf_len < MAX_DATA_BYTE_COUNT + ? (buf_len - 1) + : (MAX_DATA_BYTE_COUNT - 1))); ahci_sg++; buf_len -= MAX_DATA_BYTE_COUNT; } @@ -345,26 +339,25 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) static void ahci_set_feature(u8 port) { - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; - u32 cmd_fis_len = 5; /* five dwords */ + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ u8 fis[20]; - /*set feature*/ - memset(fis,0,20); + /*set feature */ + memset(fis, 0, 20); fis[0] = 0x27; fis[1] = 1 << 7; fis[2] = ATA_CMD_SETF; fis[3] = SETFEATURES_XFER; fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; - memcpy((unsigned char *)pp->cmd_tbl,fis,20); + memcpy((unsigned char *)pp->cmd_tbl, fis, 20); ahci_fill_cmd_slot(pp, cmd_fis_len); writel(1, port_mmio + PORT_CMD_ISSUE); readl(port_mmio + PORT_CMD_ISSUE); - if(waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { printf("set feature error!\n"); } } @@ -372,94 +365,94 @@ static void ahci_set_feature(u8 port) static int ahci_port_start(u8 port) { - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; u32 port_status; u32 mem; - debug("Enter start port: %d\n",port); + debug("Enter start port: %d\n", port); port_status = readl(port_mmio + PORT_SCR_STAT); - debug("Port %d status: %x\n",port,port_status); - if((port_status & 0xf) != 0x03){ + debug("Port %d status: %x\n", port, port_status); + if ((port_status & 0xf) != 0x03) { printf("No Link on this port!\n"); return -1; } - mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); if (!mem) { free(pp); printf("No mem for table!\n"); return -ENOMEM; } - mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); - memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); /* * First item in chunk of DMA memory: 32-slot command table, * 32 bytes each in size */ pp->cmd_slot = (struct ahci_cmd_hdr *)mem; - debug("cmd_slot = 0x%x\n",pp->cmd_slot); - + debug("cmd_slot = 0x%x\n", pp->cmd_slot); mem += (AHCI_CMD_SLOT_SZ + 224); + /* * Second item: Received-FIS area */ pp->rx_fis = mem; - mem += AHCI_RX_FIS_SZ; + /* * Third item: data area for storing a single command * and its scatter-gather table */ pp->cmd_tbl = mem; - debug("cmd_tbl_dma = 0x%x\n",pp->cmd_tbl); + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); mem += AHCI_CMD_TBL_HDR; pp->cmd_tbl_sg = (struct ahci_sg *)mem; - writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR); + writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | - PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | - PORT_CMD_START, port_mmio + PORT_CMD); + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, port_mmio + PORT_CMD); - debug("Exit start port %d\n",port); + debug("Exit start port %d\n", port); return 0; } -static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_len) +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, + int buf_len) { - struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8* port_mmio = (volatile u8 *)pp->port_mmio; + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; u32 opts; u32 port_status; int sg_count; - debug("Enter get_ahci_device_data: for port %d\n",port); + debug("Enter get_ahci_device_data: for port %d\n", port); - if(port > probe_ent->n_ports){ + if (port > probe_ent->n_ports) { printf("Invaild port number %d\n", port); return -1; } port_status = readl(port_mmio + PORT_SCR_STAT); - if((port_status & 0xf) != 0x03){ - debug("No Link on port %d!\n",port); + if ((port_status & 0xf) != 0x03) { + debug("No Link on port %d!\n", port); return -1; } memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); - sg_count = ahci_fill_sg(port,buf,buf_len); - opts = (fis_len >> 2) | (sg_count << 16) ; + sg_count = ahci_fill_sg(port, buf, buf_len); + opts = (fis_len >> 2) | (sg_count << 16); ahci_fill_cmd_slot(pp, opts); writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); @@ -469,7 +462,7 @@ static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_ return -1; } debug("get_ahci_device_data: %d byte transferred.\n", - pp->cmd_slot->status); + pp->cmd_slot->status); return 0; } @@ -478,7 +471,7 @@ static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, int buf_ static char *ata_id_strcpy(u16 *target, u16 *src, int len) { int i; - for(i = 0; i < len / 2; i++) + for (i = 0; i < len / 2; i++) target[i] = le16_to_cpu(src[i]); return (char *)target; } @@ -503,6 +496,7 @@ static void dump_ataid(hd_driveid_t *ataid) debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); } + /* * SCSI INQUIRY command operation. */ @@ -511,7 +505,7 @@ static int ata_scsiop_inquiry(ccb *pccb) u8 hdr[] = { 0, 0, - 0x5, /* claim SPC-3 version compatibility */ + 0x5, /* claim SPC-3 version compatibility */ 2, 95 - 4, }; @@ -524,33 +518,33 @@ static int ata_scsiop_inquiry(ccb *pccb) memcpy(pccb->pdata, hdr, sizeof(hdr)); - if(pccb->datalen <= 35) + if (pccb->datalen <= 35) return 0; memset(fis, 0, 20); /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_IDENT; /* Command byte. */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_IDENT; /* Command byte. */ /* Read id from sata */ port = pccb->target; - if(!(tmpid = malloc(sizeof(hd_driveid_t)))) + if (!(tmpid = malloc(sizeof(hd_driveid_t)))) return -ENOMEM; - if(get_ahci_device_data(port, (u8 *)&fis, 20, - tmpid, sizeof(hd_driveid_t))){ + if (get_ahci_device_data(port, (u8 *) & fis, 20, + tmpid, sizeof(hd_driveid_t))) { debug("scsi_ahci: SCSI inquiry command failure.\n"); return -EIO; } - if(ataid[port]) + if (ataid[port]) free(ataid[port]); - ataid[port] = (hd_driveid_t *)tmpid; + ataid[port] = (hd_driveid_t *) tmpid; memcpy(&pccb->pdata[8], "ATA ", 8); - ata_id_strcpy((u16 *)&pccb->pdata[16], (u16 *)ataid[port]->model, 16); - ata_id_strcpy((u16 *)&pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); + ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); dump_ataid(ataid[port]); return 0; @@ -560,15 +554,15 @@ static int ata_scsiop_inquiry(ccb *pccb) /* * SCSI READ10 command operation. */ -static int ata_scsiop_read10(ccb *pccb) +static int ata_scsiop_read10(ccb * pccb) { u64 lba = 0; u32 len = 0; u8 fis[20]; - lba = (((u64)pccb->cmd[2]) << 24) | (((u64)pccb->cmd[3]) << 16) - | (((u64)pccb->cmd[4]) << 8) | ((u64)pccb->cmd[5]); - len = (((u32)pccb->cmd[7]) << 8) | ((u32)pccb->cmd[8]); + lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16) + | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]); + len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); /* For 10-byte and 16-byte SCSI R/W commands, transfer * length 0 means transfer 0 block of data. @@ -577,15 +571,16 @@ static int ata_scsiop_read10(ccb *pccb) * * WARNING: one or two older ATA drives treat 0 as 0... */ - if(!len) return 0; + if (!len) + return 0; memset(fis, 0, 20); /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ - /* LBA address, only support LBA28 in this driver*/ + /* LBA address, only support LBA28 in this driver */ fis[4] = pccb->cmd[5]; fis[5] = pccb->cmd[4]; fis[6] = pccb->cmd[3]; @@ -596,8 +591,8 @@ static int ata_scsiop_read10(ccb *pccb) fis[13] = pccb->cmd[7]; /* Read from ahci */ - if(get_ahci_device_data(pccb->target, (u8*)&fis, 20, - pccb->pdata, pccb->datalen)){ + if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, + pccb->pdata, pccb->datalen)) { debug("scsi_ahci: SCSI READ10 command failure.\n"); return -EIO; } @@ -613,16 +608,16 @@ static int ata_scsiop_read_capacity10(ccb *pccb) { u8 buf[8]; - if(!ataid[pccb->target]) { + if (!ataid[pccb->target]) { printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " - "\tNo ATA info!\n" - "\tPlease run SCSI commmand INQUIRY firstly!\n"); + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); return -EPERM; } memset(buf, 0, 8); - *(u32 *)buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); + *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity); buf[6] = 512 >> 8; buf[7] = 512 & 0xff; @@ -641,11 +636,12 @@ static int ata_scsiop_test_unit_ready(ccb *pccb) return (ataid[pccb->target]) ? 0 : -EPERM; } + int scsi_exec(ccb *pccb) { int ret; - switch(pccb->cmd[0]) { + switch (pccb->cmd[0]) { case SCSI_READ10: ret = ata_scsiop_read10(pccb); break; @@ -663,8 +659,8 @@ int scsi_exec(ccb *pccb) return FALSE; } - if(ret) { - debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0],ret); + if (ret) { + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); return FALSE; } return TRUE; @@ -681,13 +677,13 @@ void scsi_low_level_init(int busdevfunc) linkmap = probe_ent->link_port_map; - for(i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++){ - if( ((linkmap >> i) & 0x01) ){ - if(ahci_port_start((u8)i)){ - printf("Can not start port %d\n",i); + for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) { + if (((linkmap >> i) & 0x01)) { + if (ahci_port_start((u8) i)) { + printf("Can not start port %d\n", i); continue; } - ahci_set_feature((u8)i); + ahci_set_feature((u8) i); } } } @@ -695,12 +691,12 @@ void scsi_low_level_init(int busdevfunc) void scsi_bus_reset(void) { -/*Not implement*/ + /*Not implement*/ } -void scsi_print_error(ccb *pccb) +void scsi_print_error(ccb * pccb) { -/*The ahci error info can be read in the ahci driver*/ + /*The ahci error info can be read in the ahci driver*/ } #endif From 5567806b67d0ae83493aa8823ad3b6c914f581d7 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 25 Aug 2006 14:38:34 -0400 Subject: [PATCH 076/101] Change ramdiskaddr and dtbaddr Remove PEX fluff commands. Signed-off-by: Haiying Wang Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7097b3eee..c704d4659 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -610,15 +610,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ + "ramdiskaddr=2000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "dtbaddr=2000000\0" \ + "dtbaddr=400000\0" \ "dtbfile=mpc8641_hpcn.dtb\0" \ - "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ - "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ - "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ - "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ - "pex=run pexstat; run pex1; run pexd\0" \ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ "maxcpus=2" From 2f15776ccc6dc32377d8ba9652b8f58059c27c6d Mon Sep 17 00:00:00 2001 From: Zhang Wei Date: Mon, 28 Aug 2006 14:25:31 +0800 Subject: [PATCH 077/101] Fixed an OF-tree off-by-one bug when adding a new property name. This bug will cause the kernel booting to pause a long time. Signed-off-by: Zhang Wei --- common/ft_build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/ft_build.c b/common/ft_build.c index b5a997c1b..b5937e35f 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -103,7 +103,7 @@ void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz) if (off == -1) { memcpy(cxt->p_end, name, strlen(name) + 1); off = cxt->p_end - cxt->p; - cxt->p_end += strlen(name) + 2; + cxt->p_end += strlen(name) + 1; } /* now put offset from beginning of *STRUCTURE* */ From 778d45049ce5927b65b3ff1d8e6692b654bdd49e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 29 Aug 2006 08:17:14 -0500 Subject: [PATCH 078/101] Add myself as maintainer for MPC8641HPCN. --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0ef9e0349..b0fc54e2d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -217,6 +217,8 @@ Jon Loeliger MPC8541CDS MPC8541 MPC8555CDS MPC8555 + MPC8641HPCN MPC8641D + Dan Malek STxGP3 MPC85xx From cd6d73d5b895a5935ac4fde0a356288142a584e0 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 29 Aug 2006 09:48:49 -0500 Subject: [PATCH 079/101] Remove bogus msync and use volatile asm. --- cpu/mpc86xx/spd_sdram.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index a4b9d54c7..44b0d4133 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -834,7 +834,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); #endif - asm("sync;isync"); + asm volatile("sync;isync"); udelay(500); /* @@ -1032,7 +1032,7 @@ unsigned int enable_ddr(unsigned int ddr_num) */ if (config == 0x02) { ddr->err_disable = 0x00000000; - asm("sync;isync;"); + asm volatile("sync;isync;"); ddr->err_sbe = 0x00ff0000; ddr->err_int_en = 0x0000000d; sdram_cfg_1 |= 0x20000000; /* ECC_EN */ @@ -1325,7 +1325,7 @@ ddr_enable_ecc(unsigned int dram_size) */ debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); ddr1->err_disable = 0x00000000; - asm("sync;isync;msync"); + asm volatile("sync;isync"); debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); } From 9bff7a69a885adebbd2bd45990494ec4cf998a30 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 29 Aug 2006 11:05:09 -0500 Subject: [PATCH 080/101] Remove trailing empty lines. --- cpu/mpc86xx/cpu_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 6ed7c3720..4673d05e7 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -115,8 +115,3 @@ int cpu_init_r(void) { return 0; } - - - - - From d14ba6a798beb753e7a864500414fcc2d198b8bc Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 14 Sep 2006 08:40:36 -0500 Subject: [PATCH 081/101] Handle 86xx SVR values according to the new Reference Manual. Both 8641 and 8641D have SVR == 0x8090, and are distinguished by the byte in bits 16-23 instead. Thanks to Jason Jin for noticing. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/cpu.c | 9 +++++---- include/asm-ppc/processor.h | 5 +++-- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index ddd0ad3b3..551b24307 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -76,11 +76,12 @@ checkcpu(void) puts(" System: "); switch (ver) { case SVR_8641: - puts("8641"); - break; - case SVR_8641D: + if (SVR_SUBVER(svr) == 1) { puts("8641D"); - break; + } else { + puts("8641"); + } + break; default: puts("Unknown"); break; diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0060cd030..553ef3d94 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -802,6 +802,8 @@ #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ + #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ @@ -819,9 +821,8 @@ #define SVR_8541 0x807A #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 - #define SVR_8641 0x8090 -#define SVR_8641D 0x8091 + /* I am just adding a single entry for 8260 boards. I think we may be * able to combine mbx, fads, rpxlite, bseip, and classic into a single From afbdc649f8751e4f4f1a6f527edfe139773f2c15 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 19 Sep 2006 09:34:10 -0500 Subject: [PATCH 082/101] Modified makefile for new build mechanism. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/Makefile | 19 +++++++++++-------- cpu/mpc86xx/Makefile | 17 ++++++++++------- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index f70f44ba2..46214ed21 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -23,12 +23,16 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := $(BOARD).o pixis.o sys_eeprom.o +COBJS := $(BOARD).o pixis.o sys_eeprom.o SOBJS := init.o -$(LIB): $(OBJS) $(SOBJS) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) clean: @@ -40,10 +44,9 @@ distclean: clean ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -ifeq ($(filter distclean, $(MAKECMDGOALS)),) --include .depend -endif +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend ######################################################################### diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index 799594516..ad5b36def 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -25,24 +25,27 @@ include $(TOPDIR)/config.mk -LIB = lib$(CPU).a +LIB = $(obj)lib$(CPU).a START = start.o #resetvec.o -ASOBJS = cache.o +SOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ pci.o pcie_indirect.o i2c.o spd_sdram.o -OBJS = $(COBJS) -all: .depend $(START) $(ASOBJS) $(LIB) +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) $(LIB): $(OBJS) $(AR) crv $@ $(ASOBJS) $(OBJS) ######################################################################### -.depend: Makefile $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(COBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### From 084d648b109c8984f83674043c1a7fa3885ef801 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:33:56 -0500 Subject: [PATCH 083/101] Added code to support 2.6.18 PCI changes in u-boot * Added code to swizzle the IRQ map for the PCI --- board/cds/common/ft_board.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c index 77d1d851d..a897d045a 100644 --- a/board/cds/common/ft_board.c +++ b/board/cds/common/ft_board.c @@ -24,9 +24,35 @@ #if defined(CONFIG_OF_FLAT_TREE) #include -extern void ft_cpu_setup(void *blob, bd_t *bd); -#endif +#include "cadmus.h" +extern void ft_cpu_setup(void *blob, bd_t *bd); + +static void cds_pci_fixup(void *blob) +{ + int len; + u32 *map; + int slot; + int i; + + map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len); + + len /= sizeof(u32); + + slot = get_pci_slot(); + + for (i=0;ibi_memstart); *p = cpu_to_be32(bd->bi_memsize); } + + cds_pci_fixup(blob); } #endif From 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:34:18 -0500 Subject: [PATCH 084/101] Add support for eTSEC 3 & 4 on 8548 CDS * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems --- board/cds/mpc8548cds/mpc8548cds.c | 32 ++++++++++++++ drivers/tsec.c | 69 ++++++++++++++++++++++++++----- drivers/tsec.h | 17 ++++++++ include/configs/MPC8548CDS.h | 4 +- 4 files changed, 111 insertions(+), 11 deletions(-) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 6eedb4a20..66219e395 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -327,3 +328,34 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif } + +int last_stage_init(void) +{ + unsigned int temp; + + /* Change the resistors for the PHY */ + /* This is needed to get the RGMII working for the 1.3+ + * CDS cards */ + if (get_board_version() == 0x13) { + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 18); + + miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, &temp); + + temp = (temp & 0xf03f); + temp |= 2 << 9; /* 36 ohm */ + temp |= 2 << 6; /* 39 ohm */ + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, temp); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 3); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, 0x8000); + } + + return 0; +} diff --git a/drivers/tsec.c b/drivers/tsec.c index 7ec565ca6..bfc49c462 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -44,9 +44,7 @@ struct tsec_info_struct { /* The tsec_info structure contains 3 values which the * driver uses to determine how to operate a given ethernet - * device. For now, the structure is initialized with the - * knowledge that all current implementations have 2 TSEC - * devices, and one FEC. The information needed is: + * device. The information needed is: * phyaddr - The address of the PHY which is attached to * the given device. * @@ -56,18 +54,16 @@ struct tsec_info_struct { * * phyregidx - This variable specifies which ethernet device * controls the MII Management registers which are connected - * to the PHY. For 8540/8560, only TSEC1 (index 0) has + * to the PHY. For now, only TSEC1 (index 0) has * access to the PHYs, so all of the entries have "0". * * The values specified in the table are taken from the board's * config file in include/configs/. When implementing a new * board with ethernet capability, it is necessary to define: - * TSEC1_PHY_ADDR - * TSEC1_PHYIDX - * TSEC2_PHY_ADDR - * TSEC2_PHYIDX + * TSECn_PHY_ADDR + * TSECn_PHYIDX * - * and for 8560: + * for n = 1,2,3, etc. And for FEC: * FEC_PHY_ADDR * FEC_PHYIDX */ @@ -91,7 +87,7 @@ static struct tsec_info_struct tsec_info[] = { { 0, 0, 0}, # endif # if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) - {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, + {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, # else { 0, 0, 0}, # endif @@ -805,6 +801,58 @@ struct phy_info phy_info_M88E1111S = { }, }; +static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) +{ + unsigned int temp; + uint mii_data = read_phy_reg(priv, mii_reg); + + + /* Setting MIIM_88E1145_PHY_EXT_CR */ + if (priv->flags & TSEC_REDUCED) + return mii_data | + MIIM_M88E1145_RGMII_RX_DELAY | + MIIM_M88E1145_RGMII_TX_DELAY; + else + return mii_data; +} + +static struct phy_info phy_info_M88E1145 = { + 0x01410cd, + "Marvell 88E1145", + 4, + (struct phy_cmd[]) { /* config */ + /* Errata E0, E1 */ + {29, 0x001b, NULL}, + {30, 0x418f, NULL}, + {29, 0x0016, NULL}, + {30, 0xa2da, NULL}, + + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, + {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, + /* Read the Status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + + struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", @@ -999,6 +1047,7 @@ struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_M88E1011S, &phy_info_M88E1111S, + &phy_info_M88E1145, &phy_info_dm9161, &phy_info_lxt971, &phy_info_dp83865, diff --git a/drivers/tsec.h b/drivers/tsec.h index b55b2992b..0bfca3a3d 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -142,6 +142,23 @@ #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 +#define MIIM_88E1011_PHY_SCR 0x10 +#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +/* 88E1145 Extended PHY Specific Control Register */ +#define MIIM_88E1145_PHY_EXT_CR 20 +#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 +#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 + +#define MIIM_88E1145_PHY_PAGE 29 +#define MIIM_88E1145_PHY_CAL_OV 30 + + /* DM9161 Control register values */ #define MIIM_DM9161_CR_STOP 0x0400 #define MIIM_DM9161_CR_RSTAN 0x1200 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 37b518cca..767ab337b 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -381,7 +381,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#undef CONFIG_MPC85XX_TSEC4 +#define CONFIG_MPC85XX_TSEC4 1 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC @@ -483,6 +483,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 From 8272dc2f58f2473d8995fcc9b916440cfba080f0 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 13 Sep 2006 10:33:35 -0500 Subject: [PATCH 085/101] Updated config headers to add default FDT-based booting --- include/configs/MPC8540ADS.h | 10 +++++++--- include/configs/MPC8541CDS.h | 9 ++++++--- include/configs/MPC8548CDS.h | 13 ++++++++----- include/configs/MPC8555CDS.h | 9 ++++++--- 4 files changed, 27 insertions(+), 14 deletions(-) diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 8e4d2c95a..31ffbaf15 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -517,8 +517,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -526,13 +528,15 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index f73caf031..2b87f1bd6 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 767ab337b..03ab976d1 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -389,13 +389,11 @@ extern unsigned long get_clock_freq(void); #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 #define TSEC4_PHY_ADDR 3 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 -#define FEC_PHYIDX 0 /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" @@ -507,8 +505,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" + #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -516,7 +517,9 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b94e38ae3..771a9d3b9 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -489,8 +489,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -498,7 +500,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ From f55df18187e7a45cb73fec4370d12135e6691ae1 Mon Sep 17 00:00:00 2001 From: John Traill Date: Fri, 29 Sep 2006 08:23:12 +0100 Subject: [PATCH 086/101] Fix missing tCycle/modfreq calculation. Signed-off-by: John Traill --- cpu/mpc86xx/spd_sdram.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 44b0d4133..39da3cc53 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -466,6 +466,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, * are slower than the DDR module. */ busfreq = get_bus_freq(0) / 1000000; /* MHz */ + tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3); + modfreq = 2 * 1000 * 1000 / tCycle_ps; if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) { printf("DDR: platform frequency too low for correct DDR2 controller operation\n"); From 333961ae7095fc66d8a041fce1ac9ee873b09d86 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:02:22 -0500 Subject: [PATCH 087/101] Fix whitespace and 80-col issues. --- board/cds/common/via.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/board/cds/common/via.c b/board/cds/common/via.c index 68c8d212f..e79bd02a1 100644 --- a/board/cds/common/via.c +++ b/board/cds/common/via.c @@ -24,7 +24,8 @@ #include /* Config the VIA chip */ -void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +void mpc85xx_config_via(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) { pci_dev_t bridge; @@ -47,7 +48,8 @@ void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_c } /* Function 1, IDE */ -void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +void mpc85xx_config_via_usbide(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) { pciauto_config_device(hose, dev); /* @@ -64,7 +66,8 @@ void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struc } /* Function 2, USB ports 0-1 */ -void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +void mpc85xx_config_via_usb(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) { pciauto_config_device(hose, dev); @@ -72,7 +75,8 @@ void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct p } /* Function 3, USB ports 2-3 */ -void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +void mpc85xx_config_via_usb2(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) { pciauto_config_device(hose, dev); @@ -80,7 +84,8 @@ void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct } /* Function 5, Power Management */ -void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +void mpc85xx_config_via_power(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) { pciauto_config_device(hose, dev); @@ -90,10 +95,10 @@ void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct } /* Function 6, AC97 Interface */ -void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +void mpc85xx_config_via_ac97(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) { pciauto_config_device(hose, dev); pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); } - From 89875e96ba3f023157bf50d5f8e33bf254964a76 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:03:43 -0500 Subject: [PATCH 088/101] Ran lindent and cleaned up whitespace issues. Format for 80-columns too. --- drivers/tsec.c | 892 +++++++++++++++++++++++++------------------------ 1 file changed, 453 insertions(+), 439 deletions(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index 0fb3ca229..30dca1152 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -1,5 +1,4 @@ /* - * tsec.c * Freescale Three Speed Ethernet Controller driver * * This software may be used and distributed according to the @@ -28,13 +27,13 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUF_CNT 2 -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ typedef volatile struct rtxbd { txbd8_t txbd[TX_BUF_CNT]; rxbd8_t rxbd[PKTBUFSRX]; -} RTXBD; +} RTXBD; struct tsec_info_struct { unsigned int phyaddr; @@ -42,7 +41,6 @@ struct tsec_info_struct { unsigned int phyregidx; }; - /* The tsec_info structure contains 3 values which the * driver uses to determine how to operate a given ethernet * device. The information needed is: @@ -74,14 +72,14 @@ static struct tsec_info_struct tsec_info[] = { #elif defined(CONFIG_MPC86XX_TSEC1) {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, #else - { 0, 0, 0}, + {0, 0, 0}, #endif #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, #elif defined(CONFIG_MPC86XX_TSEC2) - {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, + {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, #else - { 0, 0, 0}, + {0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC {FEC_PHY_ADDR, 0, FEC_PHYIDX}, @@ -89,12 +87,12 @@ static struct tsec_info_struct tsec_info[] = { #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3) {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, #else - { 0, 0, 0}, + {0, 0, 0}, #endif #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4) {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, #else - { 0, 0, 0}, + {0, 0, 0}, #endif #endif }; @@ -111,68 +109,69 @@ static RTXBD rtx __attribute__ ((aligned(8))); #error "rtx must be 64-bit aligned" #endif -static int tsec_send(struct eth_device* dev, volatile void *packet, int length); -static int tsec_recv(struct eth_device* dev); -static int tsec_init(struct eth_device* dev, bd_t * bd); -static void tsec_halt(struct eth_device* dev); -static void init_registers(volatile tsec_t *regs); +static int tsec_send(struct eth_device *dev, + volatile void *packet, int length); +static int tsec_recv(struct eth_device *dev); +static int tsec_init(struct eth_device *dev, bd_t * bd); +static void tsec_halt(struct eth_device *dev); +static void init_registers(volatile tsec_t * regs); static void startup_tsec(struct eth_device *dev); static int init_phy(struct eth_device *dev); void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); uint read_phy_reg(struct tsec_private *priv, uint regnum); -struct phy_info * get_phy_info(struct eth_device *dev); +struct phy_info *get_phy_info(struct eth_device *dev); void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); static void adjust_link(struct eth_device *dev); static void relocate_cmds(void); static int tsec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); + unsigned char reg, unsigned short value); static int tsec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); + unsigned char reg, unsigned short *value); /* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) */ -int tsec_initialize(bd_t *bis, int index, char *devname) +int tsec_initialize(bd_t * bis, int index, char *devname) { - struct eth_device* dev; + struct eth_device *dev; int i; struct tsec_private *priv; - dev = (struct eth_device*) malloc(sizeof *dev); + dev = (struct eth_device *)malloc(sizeof *dev); - if(NULL == dev) + if (NULL == dev) return 0; memset(dev, 0, sizeof *dev); - priv = (struct tsec_private *) malloc(sizeof(*priv)); + priv = (struct tsec_private *)malloc(sizeof(*priv)); - if(NULL == priv) + if (NULL == priv) return 0; privlist[index] = priv; - priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE); + priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + - tsec_info[index].phyregidx*TSEC_SIZE); + tsec_info[index].phyregidx * + TSEC_SIZE); priv->phyaddr = tsec_info[index].phyaddr; priv->flags = tsec_info[index].flags; sprintf(dev->name, devname); dev->iobase = 0; - dev->priv = priv; - dev->init = tsec_init; - dev->halt = tsec_halt; - dev->send = tsec_send; - dev->recv = tsec_recv; + dev->priv = priv; + dev->init = tsec_init; + dev->halt = tsec_halt; + dev->send = tsec_send; + dev->recv = tsec_recv; /* Tell u-boot to get the addr from the env */ - for(i=0;i<6;i++) + for (i = 0; i < 6; i++) dev->enetaddr[i] = 0; eth_register(dev); - /* Reset the MAC */ priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); @@ -186,12 +185,12 @@ int tsec_initialize(bd_t *bis, int index, char *devname) return init_phy(dev); } - /* Initializes data structures and registers for the controller, * and brings the interface up. Returns the link status, meaning * that it returns success if the link is up, failure otherwise. - * This allows u-boot to find the first active controller. */ -int tsec_init(struct eth_device* dev, bd_t * bd) + * This allows u-boot to find the first active controller. + */ +int tsec_init(struct eth_device *dev, bd_t * bd) { uint tempval; char tmpbuf[MAC_ADDR_LEN]; @@ -210,12 +209,12 @@ int tsec_init(struct eth_device* dev, bd_t * bd) /* Copy the station address into the address registers. * Backwards, because little endian MACS are dumb */ - for(i=0;ienetaddr[i]; } - regs->macstnaddr1 = *((uint *)(tmpbuf)); + regs->macstnaddr1 = *((uint *) (tmpbuf)); - tempval = *((uint *)(tmpbuf +4)); + tempval = *((uint *) (tmpbuf + 4)); regs->macstnaddr2 = tempval; @@ -234,7 +233,6 @@ int tsec_init(struct eth_device* dev, bd_t * bd) } - /* Write value to the device's PHY through the registers * specified in priv, modifying the register specified in regnum. * It will wait for the write to be done (or for a timeout to @@ -244,17 +242,16 @@ void write_phy_reg(struct tsec_private *priv, uint regnum, uint value) { volatile tsec_t *regbase = priv->phyregs; uint phyid = priv->phyaddr; - int timeout=1000000; + int timeout = 1000000; regbase->miimadd = (phyid << 8) | regnum; regbase->miimcon = value; asm("sync"); - timeout=1000000; - while((regbase->miimind & MIIMIND_BUSY) && timeout--); + timeout = 1000000; + while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; } - /* Reads register regnum on the device's PHY through the * registers specified in priv. It lowers and raises the read * command, and waits for the data to become valid (miimind @@ -280,7 +277,7 @@ uint read_phy_reg(struct tsec_private *priv, uint regnum) asm("sync"); /* Wait for the the indication that the read is done */ - while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))); + while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; /* Grab the value read from the PHY */ value = regbase->miimstat; @@ -288,7 +285,6 @@ uint read_phy_reg(struct tsec_private *priv, uint regnum) return value; } - /* Discover which PHY is attached to the device, and configure it * properly. If the PHY is not recognized, then return 0 * (failure). Otherwise, return 1 @@ -297,32 +293,29 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; + volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); /* Assign a Physical address to the TBI */ - - { - volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); - regs->tbipa = TBIPA_VALUE; - regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); - regs->tbipa = TBIPA_VALUE; - asm("sync"); - } + regs->tbipa = TBIPA_VALUE; + regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); + regs->tbipa = TBIPA_VALUE; + asm("sync"); /* Reset MII (due to new addresses) */ priv->phyregs->miimcfg = MIIMCFG_RESET; asm("sync"); priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; asm("sync"); - while(priv->phyregs->miimind & MIIMIND_BUSY); + while (priv->phyregs->miimind & MIIMIND_BUSY) ; - if(0 == relocated) + if (0 == relocated) relocate_cmds(); /* Get the cmd structure corresponding to the attached * PHY */ curphy = get_phy_info(dev); - if(NULL == curphy) { + if (NULL == curphy) { printf("%s: No PHY found\n", dev->name); return 0; @@ -335,49 +328,53 @@ static int init_phy(struct eth_device *dev) return 1; } - -/* Returns which value to write to the control register. */ -/* For 10/100, the value is slightly different */ -uint mii_cr_init(uint mii_reg, struct tsec_private *priv) +/* + * Returns which value to write to the control register. + * For 10/100, the value is slightly different + */ +uint mii_cr_init(uint mii_reg, struct tsec_private * priv) { - if(priv->flags & TSEC_GIGABIT) + if (priv->flags & TSEC_GIGABIT) return MIIM_CONTROL_INIT; else return MIIM_CR_INIT; } - /* Parse the status register for link, and then do - * auto-negotiation */ -uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) + * auto-negotiation + */ +uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) { /* - * Wait if PHY is capable of autonegotiation and autonegotiation is not complete + * Wait if PHY is capable of autonegotiation and autonegotiation + * is not complete. */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if ((mii_reg & PHY_BMSR_AUTN_ABLE) + && !(mii_reg & PHY_BMSR_AUTN_COMP)) { int i = 0; - puts ("Waiting for PHY auto negotiation to complete"); - while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) { + puts("Waiting for PHY auto negotiation to complete"); + while (!((mii_reg & PHY_BMSR_AUTN_COMP) + && (mii_reg & MIIM_STATUS_LINK))) { /* * Timeout reached ? */ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); + puts(" TIMEOUT !\n"); priv->link = 0; return 0; } if ((i++ % 1000) == 0) { - putc ('.'); + putc('.'); } - udelay (1000); /* 1 ms */ + udelay(1000); /* 1 ms */ mii_reg = read_phy_reg(priv, MIIM_STATUS); } - puts (" done\n"); + puts(" done\n"); priv->link = 1; - udelay (500000); /* another 500 ms (results in faster booting) */ + udelay(500000); /* another 500 ms (results in faster booting) */ } else { priv->link = 1; } @@ -385,10 +382,10 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) return 0; } - /* Parse the 88E1011's status register for speed and duplex - * information */ -uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv) + * information + */ +uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) { uint speed; @@ -398,114 +395,116 @@ uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv) (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { int i = 0; - puts ("Waiting for PHY realtime link"); + puts("Waiting for PHY realtime link"); while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { /* * Timeout reached ? */ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); + puts(" TIMEOUT !\n"); priv->link = 0; break; } if ((i++ % 1000) == 0) { - putc ('.'); + putc('.'); } - udelay (1000); /* 1 ms */ + udelay(1000); /* 1 ms */ mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); } - puts (" done\n"); - udelay (500000); /* another 500 ms (results in faster booting) */ + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ } - if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) + if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) priv->duplexity = 1; else priv->duplexity = 0; - speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED); + speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); - switch(speed) { - case MIIM_88E1011_PHYSTAT_GBIT: - priv->speed = 1000; - break; - case MIIM_88E1011_PHYSTAT_100: - priv->speed = 100; - break; - default: - priv->speed = 10; + switch (speed) { + case MIIM_88E1011_PHYSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_88E1011_PHYSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; } return 0; } - /* Parse the cis8201's status register for speed and duplex - * information */ -uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv) + * information + */ +uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) { uint speed; - if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) + if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) priv->duplexity = 1; else priv->duplexity = 0; speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; - switch(speed) { - case MIIM_CIS8201_AUXCONSTAT_GBIT: - priv->speed = 1000; - break; - case MIIM_CIS8201_AUXCONSTAT_100: - priv->speed = 100; - break; - default: - priv->speed = 10; - break; + switch (speed) { + case MIIM_CIS8201_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_CIS8201_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; } return 0; } + /* Parse the vsc8244's status register for speed and duplex - * information */ -uint mii_parse_vsc8244(uint mii_reg, struct tsec_private *priv) + * information + */ +uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) { - uint speed; - - if(mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) - priv->duplexity = 1; - else - priv->duplexity = 0; - - speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; - switch(speed) { - case MIIM_VSC8244_AUXCONSTAT_GBIT: - priv->speed = 1000; - break; - case MIIM_VSC8244_AUXCONSTAT_100: - priv->speed = 100; - break; - default: - priv->speed = 10; - break; - } - - return 0; + uint speed; + + if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; + switch (speed) { + case MIIM_VSC8244_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_VSC8244_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; + } + + return 0; } - /* Parse the DM9161's status register for speed and duplex - * information */ -uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv) + * information + */ +uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) { - if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) + if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) priv->speed = 100; else priv->speed = 10; - if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) + if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) priv->duplexity = 1; else priv->duplexity = 0; @@ -513,27 +512,28 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv) return 0; } - -/* Hack to write all 4 PHYs with the LED values */ -uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv) +/* + * Hack to write all 4 PHYs with the LED values + */ +uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; volatile tsec_t *regbase = priv->phyregs; - int timeout=1000000; + int timeout = 1000000; - for(phyid=0;phyid<4;phyid++) { + for (phyid = 0; phyid < 4; phyid++) { regbase->miimadd = (phyid << 8) | mii_reg; regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; asm("sync"); - timeout=1000000; - while((regbase->miimind & MIIMIND_BUSY) && timeout--); + timeout = 1000000; + while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; } return MIIM_CIS8204_SLEDCON_INIT; } -uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv) +uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) { if (priv->flags & TSEC_REDUCED) return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; @@ -543,8 +543,9 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv) /* Initialized required registers to appropriate values, zeroing * those we don't care about (unless zero is bad, in which case, - * choose a more appropriate value) */ -static void init_registers(volatile tsec_t *regs) + * choose a more appropriate value) + */ +static void init_registers(volatile tsec_t * regs) { /* Clear IEVENT */ regs->ievent = IEVENT_INIT_CLEAR; @@ -586,55 +587,55 @@ static void init_registers(volatile tsec_t *regs) } - /* Configure maccfg2 based on negotiated speed and duplex - * reported by PHY handling code */ + * reported by PHY handling code + */ static void adjust_link(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; volatile tsec_t *regs = priv->regs; - if(priv->link) { - if(priv->duplexity != 0) + if (priv->link) { + if (priv->duplexity != 0) regs->maccfg2 |= MACCFG2_FULL_DUPLEX; else regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); - switch(priv->speed) { - case 1000: - regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) - | MACCFG2_GMII); - break; - case 100: - case 10: - regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) - | MACCFG2_MII); + switch (priv->speed) { + case 1000: + regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) + | MACCFG2_GMII); + break; + case 100: + case 10: + regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) + | MACCFG2_MII); - /* If We're in reduced mode, we need - * to say whether we're 10 or 100 MB. - */ - if ((priv->speed == 100) - && (priv->flags & TSEC_REDUCED)) - regs->ecntrl |= ECNTRL_R100; - else - regs->ecntrl &= ~(ECNTRL_R100); - break; - default: - printf("%s: Speed was bad\n", dev->name); - break; + /* If We're in reduced mode, we need + * to say whether we're 10 or 100 MB. + */ + if ((priv->speed == 100) + && (priv->flags & TSEC_REDUCED)) + regs->ecntrl |= ECNTRL_R100; + else + regs->ecntrl &= ~(ECNTRL_R100); + break; + default: + printf("%s: Speed was bad\n", dev->name); + break; } printf("Speed: %d, %s duplex\n", priv->speed, - (priv->duplexity) ? "full" : "half"); + (priv->duplexity) ? "full" : "half"); } else { printf("%s: No link.\n", dev->name); } } - /* Set up the buffers and their descriptors, and bring up the - * interface */ + * interface + */ static void startup_tsec(struct eth_device *dev) { int i; @@ -649,17 +650,17 @@ static void startup_tsec(struct eth_device *dev) for (i = 0; i < PKTBUFSRX; i++) { rtx.rxbd[i].status = RXBD_EMPTY; rtx.rxbd[i].length = 0; - rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i]; + rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; } - rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP; + rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; /* Initialize the TX Buffer Descriptors */ - for(i=0; iphyinfo->startup); @@ -677,8 +678,9 @@ static void startup_tsec(struct eth_device *dev) /* This returns the status bits of the device. The return value * is never checked, and this is what the 8260 driver did, so we * do the same. Presumably, this would be zero if there were no - * errors */ -static int tsec_send(struct eth_device* dev, volatile void *packet, int length) + * errors + */ +static int tsec_send(struct eth_device *dev, volatile void *packet, int length) { int i; int result = 0; @@ -686,24 +688,25 @@ static int tsec_send(struct eth_device* dev, volatile void *packet, int length) volatile tsec_t *regs = priv->regs; /* Find an empty buffer descriptor */ - for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { if (i >= TOUT_LOOP) { - debug ("%s: tsec: tx buffers full\n", dev->name); + debug("%s: tsec: tx buffers full\n", dev->name); return result; } } - rtx.txbd[txIdx].bufPtr = (uint)packet; + rtx.txbd[txIdx].bufPtr = (uint) packet; rtx.txbd[txIdx].length = length; - rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); + rtx.txbd[txIdx].status |= + (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); /* Tell the DMA to go */ regs->tstat = TSTAT_CLEAR_THALT; /* Wait for buffer to be transmitted */ - for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { if (i >= TOUT_LOOP) { - debug ("%s: tsec: tx error\n", dev->name); + debug("%s: tsec: tx error\n", dev->name); return result; } } @@ -714,13 +717,13 @@ static int tsec_send(struct eth_device* dev, volatile void *packet, int length) return result; } -static int tsec_recv(struct eth_device* dev) +static int tsec_recv(struct eth_device *dev) { int length; struct tsec_private *priv = (struct tsec_private *)dev->priv; volatile tsec_t *regs = priv->regs; - while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { + while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { length = rtx.rxbd[rxIdx].length; @@ -729,18 +732,19 @@ static int tsec_recv(struct eth_device* dev) NetReceive(NetRxPackets[rxIdx], length - 4); } else { printf("Got error %x\n", - (rtx.rxbd[rxIdx].status & RXBD_STATS)); + (rtx.rxbd[rxIdx].status & RXBD_STATS)); } rtx.rxbd[rxIdx].length = 0; /* Set the wrap bit if this is the last element in the list */ - rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + rtx.rxbd[rxIdx].status = + RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); rxIdx = (rxIdx + 1) % PKTBUFSRX; } - if(regs->ievent&IEVENT_BSY) { + if (regs->ievent & IEVENT_BSY) { regs->ievent = IEVENT_BSY; regs->rstat = RSTAT_CLEAR_RHALT; } @@ -749,9 +753,8 @@ static int tsec_recv(struct eth_device* dev) } - /* Stop the interface */ -static void tsec_halt(struct eth_device* dev) +static void tsec_halt(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; volatile tsec_t *regs = priv->regs; @@ -759,7 +762,7 @@ static void tsec_halt(struct eth_device* dev) regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); - while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))); + while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); @@ -767,69 +770,70 @@ static void tsec_halt(struct eth_device* dev) phy_run_commands(priv, priv->phyinfo->shutdown); } - struct phy_info phy_info_M88E1011S = { 0x01410c6, "Marvell 88E1011S", 4, - (struct phy_cmd[]) { /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; struct phy_info phy_info_M88E1111S = { 0x01410cc, "Marvell 88E1111S", 4, - (struct phy_cmd[]) { /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) @@ -837,12 +841,10 @@ static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) unsigned int temp; uint mii_data = read_phy_reg(priv, mii_reg); - /* Setting MIIM_88E1145_PHY_EXT_CR */ if (priv->flags & TSEC_REDUCED) return mii_data | - MIIM_M88E1145_RGMII_RX_DELAY | - MIIM_M88E1145_RGMII_TX_DELAY; + MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; else return mii_data; } @@ -851,64 +853,70 @@ static struct phy_info phy_info_M88E1145 = { 0x01410cd, "Marvell 88E1145", 4, - (struct phy_cmd[]) { /* config */ - /* Errata E0, E1 */ - {29, 0x001b, NULL}, - {30, 0x418f, NULL}, - {29, 0x0016, NULL}, - {30, 0xa2da, NULL}, + (struct phy_cmd[]){ /* config */ + /* Errata E0, E1 */ + {29, 0x001b, NULL}, + {30, 0x418f, NULL}, + {29, 0x0016, NULL}, + {30, 0xa2da, NULL}, - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, - {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, - /* Read the Status */ - {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, + NULL}, + {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_88E1111_PHY_LED_CONTROL, + MIIM_88E1111_PHY_LED_DIRECT, NULL}, + /* Read the Status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; - struct phy_info phy_info_cis8204 = { 0x3f11, "Cicada Cis8204", 6, - (struct phy_cmd[]) { /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled}, - {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, + MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, + &mii_cis8204_fixled}, + {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, + &mii_cis8204_setmode}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, + &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; /* Cicada 8201 */ @@ -916,81 +924,86 @@ struct phy_info phy_info_cis8201 = { 0xfc41, "CIS8201", 4, - (struct phy_cmd[]) { /* config */ - /* Override PHY config settings */ - {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, - /* Set up the interface mode */ - {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, + MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, + NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, + &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; struct phy_info phy_info_VSC8244 = { - 0x3f1b, - "Vitesse VSC8244", - 6, - (struct phy_cmd[]) { /* config */ - /* Override PHY config settings */ - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Read the Status (2x to make sure link is right) */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + 0x3f1b, + "Vitesse VSC8244", + 6, + (struct phy_cmd[]){ /* config */ + /* Override PHY config settings */ + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_VSC8244_AUX_CONSTAT, miim_read, + &mii_parse_vsc8244}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; - struct phy_info phy_info_dm9161 = { 0x0181b88, "Davicom DM9161E", 4, - (struct phy_cmd[]) { /* config */ - {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, - /* Do not bypass the scrambler/descrambler */ - {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, - /* Clear 10BTCSR to default */ - {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, - /* Configure some basic stuff */ - {MIIM_CONTROL, MIIM_CR_INIT, NULL}, - /* Restart Auto Negotiation */ - {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, + /* Do not bypass the scrambler/descrambler */ + {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, + /* Clear 10BTCSR to default */ + {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, + NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CR_INIT, NULL}, + /* Restart Auto Negotiation */ + {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_DM9161_SCSR, miim_read, + &mii_parse_dm9161_scsr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) @@ -1028,24 +1041,25 @@ static struct phy_info phy_info_lxt971 = { 0x0001378e, "LXT971", 4, - (struct phy_cmd []) { /* config */ - { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */ - { miim_end, } - }, - (struct phy_cmd []) { /* startup - enable interrupts */ - /* { 0x12, 0x00f2, NULL }, */ - { MIIM_STATUS, miim_read, NULL }, - { MIIM_STATUS, miim_read, &mii_parse_sr }, - { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 }, - { miim_end, } - }, - (struct phy_cmd []) { /* shutdown - disable interrupts */ - { miim_end, } - }, + (struct phy_cmd[]){ /* config */ + {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ + {miim_end,} + }, + (struct phy_cmd[]){ /* startup - enable interrupts */ + /* { 0x12, 0x00f2, NULL }, */ + {MIIM_STATUS, miim_read, NULL}, + {MIIM_STATUS, miim_read, &mii_parse_sr}, + {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown - disable interrupts */ + {miim_end,} + }, }; /* Parse the DP83865's link and auto-neg status register for speed and duplex - * information */ + * information + */ uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) { switch (mii_reg & MIIM_DP83865_SPD_MASK) { @@ -1076,22 +1090,23 @@ struct phy_info phy_info_dp83865 = { 0x20005c7, "NatSemi DP83865", 4, - (struct phy_cmd[]) { /* config */ - {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, - {miim_end,} - }, - (struct phy_cmd[]) { /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the link and auto-neg status */ - {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, - {miim_end,} - }, - (struct phy_cmd[]) { /* shutdown */ - {miim_end,} - }, + (struct phy_cmd[]){ /* config */ + {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the link and auto-neg status */ + {MIIM_DP83865_LANR, miim_read, + &mii_parse_dp83865_lanr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; struct phy_info *phy_info[] = { @@ -1109,11 +1124,11 @@ struct phy_info *phy_info[] = { NULL }; - /* Grab the identifier of the device's PHY, and search through * all of the known PHYs to see if one matches. If so, return - * it, if not, return NULL */ -struct phy_info * get_phy_info(struct eth_device *dev) + * it, if not, return NULL + */ +struct phy_info *get_phy_info(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; uint phy_reg, phy_ID; @@ -1130,13 +1145,12 @@ struct phy_info * get_phy_info(struct eth_device *dev) /* loop through all the known PHY types, and find one that */ /* matches the ID we read from the PHY. */ - for(i=0; phy_info[i]; i++) { - if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) + for (i = 0; phy_info[i]; i++) { + if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) theInfo = phy_info[i]; } - if(theInfo == NULL) - { + if (theInfo == NULL) { printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); return NULL; } else { @@ -1146,9 +1160,9 @@ struct phy_info * get_phy_info(struct eth_device *dev) return theInfo; } - /* Execute the given series of commands on the given device's - * PHY, running functions as necessary*/ + * PHY, running functions as necessary + */ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; @@ -1159,18 +1173,18 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) phyregs->miimcfg = MIIMCFG_INIT_VALUE; - while(phyregs->miimind & MIIMIND_BUSY); + while (phyregs->miimind & MIIMIND_BUSY) ; - for(i=0;cmd->mii_reg != miim_end;i++) { - if(cmd->mii_data == miim_read) { + for (i = 0; cmd->mii_reg != miim_end; i++) { + if (cmd->mii_data == miim_read) { result = read_phy_reg(priv, cmd->mii_reg); - if(cmd->funct != NULL) - (*(cmd->funct))(result, priv); + if (cmd->funct != NULL) + (*(cmd->funct)) (result, priv); } else { - if(cmd->funct != NULL) - result = (*(cmd->funct))(cmd->mii_reg, priv); + if (cmd->funct != NULL) + result = (*(cmd->funct)) (cmd->mii_reg, priv); else result = cmd->mii_data; @@ -1181,37 +1195,38 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) } } - /* Relocate the function pointers in the phy cmd lists */ static void relocate_cmds(void) { struct phy_cmd **cmdlistptr; struct phy_cmd *cmd; - int i,j,k; + int i, j, k; - for(i=0; phy_info[i]; i++) { + for (i = 0; phy_info[i]; i++) { /* First thing's first: relocate the pointers to the * PHY command structures (the structs were done) */ - phy_info[i] = (struct phy_info *) ((uint)phy_info[i] - + gd->reloc_off); + phy_info[i] = (struct phy_info *)((uint) phy_info[i] + + gd->reloc_off); phy_info[i]->name += gd->reloc_off; phy_info[i]->config = - (struct phy_cmd *)((uint)phy_info[i]->config - + gd->reloc_off); + (struct phy_cmd *)((uint) phy_info[i]->config + + gd->reloc_off); phy_info[i]->startup = - (struct phy_cmd *)((uint)phy_info[i]->startup - + gd->reloc_off); + (struct phy_cmd *)((uint) phy_info[i]->startup + + gd->reloc_off); phy_info[i]->shutdown = - (struct phy_cmd *)((uint)phy_info[i]->shutdown - + gd->reloc_off); + (struct phy_cmd *)((uint) phy_info[i]->shutdown + + gd->reloc_off); cmdlistptr = &phy_info[i]->config; - j=0; - for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) { - k=0; - for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) { + j = 0; + for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { + k = 0; + for (cmd = *cmdlistptr; + cmd->mii_reg != miim_end; + cmd++) { /* Only relocate non-NULL pointers */ - if(cmd->funct) + if (cmd->funct) cmd->funct += gd->reloc_off; k++; @@ -1223,16 +1238,15 @@ static void relocate_cmds(void) relocated = 1; } - #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ && !defined(BITBANGMII) -struct tsec_private * get_priv_for_phy(unsigned char phyaddr) +struct tsec_private *get_priv_for_phy(unsigned char phyaddr) { int i; - for(i=0;iphyaddr == phyaddr) + for (i = 0; i < MAXCONTROLLERS; i++) { + if (privlist[i]->phyaddr == phyaddr) return privlist[i]; } @@ -1246,12 +1260,12 @@ struct tsec_private * get_priv_for_phy(unsigned char phyaddr) * 0 on success */ static int tsec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) + unsigned char reg, unsigned short *value) { unsigned short ret; struct tsec_private *priv = get_priv_for_phy(addr); - if(NULL == priv) { + if (NULL == priv) { printf("Can't read PHY at address %d\n", addr); return -1; } @@ -1269,11 +1283,11 @@ static int tsec_miiphy_read(char *devname, unsigned char addr, * 0 on success */ static int tsec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) + unsigned char reg, unsigned short value) { struct tsec_private *priv = get_priv_for_phy(addr); - if(NULL == priv) { + if (NULL == priv) { printf("Can't write PHY at address %d\n", addr); return -1; } From e10390ddd736b0dad1528eec4b0fe35c0827139a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:06:53 -0500 Subject: [PATCH 089/101] Fix whitespace issues. --- doc/README.mpc8641hpcn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn index 8ea0b1e9e..4a650ce43 100644 --- a/doc/README.mpc8641hpcn +++ b/doc/README.mpc8641hpcn @@ -30,7 +30,7 @@ Switches: SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz 001 :: SYSCLK = 40MHz - SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X + SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X 0100 :: 4X 0110 :: 6X 1000 :: 8X @@ -109,7 +109,7 @@ To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): 4. Memory Map ------------- - Memory Range Device Size + Memory Range Device Size ------------ ------ ---- 0x0000_0000 0x7fff_ffff DDR 2G 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M From 7b382b7125f2397cce63253df62f183e3dfa2770 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:14:45 -0500 Subject: [PATCH 090/101] Fix whitespace issues. --- board/mpc8641hpcn/init.S | 1 - cpu/mpc86xx/start.S | 1 - 2 files changed, 2 deletions(-) diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index c6ea55ea7..6b3e2d275 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -177,4 +177,3 @@ law_entry: stwu r6, 0x20(r5) blr - diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index e537dcb32..1761963be 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -1224,4 +1224,3 @@ secondary_cpu_setup: /* Never Returns, Running in Linux Now */ #endif - From 8b283dbb3a08d1b8d406bc15f119e081b3e2606a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:16:04 -0500 Subject: [PATCH 091/101] Fix whitespace issues. --- include/asm-ppc/immap_86xx.h | 466 +++++++++++++++++----------------- include/configs/MPC8641HPCN.h | 9 - 2 files changed, 233 insertions(+), 242 deletions(-) diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 5b1f0f4ea..685fcafdf 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -59,29 +59,29 @@ typedef struct ccsr_local_mcm { char res22[20]; uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ char res23[4]; - uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ char res24[716]; uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ char res25[4]; - uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ - char res26[4]; - uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ - char res27[44]; - uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ - uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ - uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ - uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ - char res28[16]; - uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ - uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ - uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ - char res29[3476]; + uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ + char res26[4]; + uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ + char res27[44]; + uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ + uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ + uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ + uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ + char res28[16]; + uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ + uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ + uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ + char res29[3476]; uint edr; /* 0x1e00 - MCM Error Detect Register */ char res30[4]; uint eer; /* 0x1e08 - MCM Error Enable Register */ uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ - uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ + uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ char res31[488]; } ccsr_local_mcm_t; @@ -106,28 +106,28 @@ typedef struct ccsr_ddr { uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ - char res7[104]; - uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + char res7[104]; + uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ + uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ - uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ + uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ + uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ char res8[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res9[12]; - uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ - uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ - uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ - char res10[2728]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ + char res9[12]; + uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ + uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ + uint init_addr; /* 0x2148 - DDR training initialzation address */ + uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + char res10[2728]; + uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ + uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res11[512]; uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ @@ -142,7 +142,7 @@ typedef struct ccsr_ddr { uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ + uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ char res14[164]; uint debug_1; /* 0x2f00 */ @@ -279,7 +279,7 @@ typedef struct ccsr_lbc { typedef struct ccsr_pex { uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ - char res1[4]; + char res1[4]; uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ char res2[16]; uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ @@ -326,7 +326,7 @@ typedef struct ccsr_pex { uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ char res16[12]; uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ - char res17[4]; + char res17[4]; uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ @@ -355,73 +355,73 @@ typedef struct ccsr_pex { /* Hyper Transport Register Block (0xA000-0xB000) */ typedef struct ccsr_ht { - uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ - uint hcfg_data; /* 0xa004 - HT Configuration Data register */ + uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ + uint hcfg_data; /* 0xa004 - HT Configuration Data register */ char res1[3064]; - uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ + uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ char res2[12]; - uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ - char res3[12]; - uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ - char res4[4]; - uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ - char res5[4]; - uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ - char res6[12]; - uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ - char res7[4]; - uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ - char res8[4]; - uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ - char res9[12]; - uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ - char res10[4]; - uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ - char res11[4]; - uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ - char res12[12]; - uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ - char res13[4]; - uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ - char res14[4]; - uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ - char res15[236]; - uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ - char res16[4]; - uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ - char res17[4]; - uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ - char res18[12]; - uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ - char res19[4]; - uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ - char res20[4]; - uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ - char res21[12]; - uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ - char res22[4]; - uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ - char res23[4]; - uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ - char res24[12]; - uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ - char res25[4]; - uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ - char res26[4]; - uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ - char res27[12]; - uint hedr; /* 0xae00 - HT Error Detect register */ - char res28[4]; - uint heier; /* 0xae08 - HT Error Interrupt Enable register */ - char res29[4]; - uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ - char res30[12]; - uint hecsr; /* 0xae20 - HT Error Capture Status register */ - char res31[4]; - uint hec0; /* 0xae28 - HT Error Capture 0 register */ - uint hec1; /* 0xae2c - HT Error Capture 1 register */ - uint hec2; /* 0xae30 - HT Error Capture 2 register */ - char res32[460]; + uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ + char res3[12]; + uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ + char res4[4]; + uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ + char res5[4]; + uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ + char res6[12]; + uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ + char res7[4]; + uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ + char res8[4]; + uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ + char res9[12]; + uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ + char res10[4]; + uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ + char res11[4]; + uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ + char res12[12]; + uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ + char res13[4]; + uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ + char res14[4]; + uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ + char res15[236]; + uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ + char res16[4]; + uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ + char res17[4]; + uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ + char res18[12]; + uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ + char res19[4]; + uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ + char res20[4]; + uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ + char res21[12]; + uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ + char res22[4]; + uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ + char res23[4]; + uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ + char res24[12]; + uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ + char res25[4]; + uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ + char res26[4]; + uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ + char res27[12]; + uint hedr; /* 0xae00 - HT Error Detect register */ + char res28[4]; + uint heier; /* 0xae08 - HT Error Interrupt Enable register */ + char res29[4]; + uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ + char res30[12]; + uint hecsr; /* 0xae20 - HT Error Capture Status register */ + char res31[4]; + uint hec0; /* 0xae28 - HT Error Capture 0 register */ + uint hec1; /* 0xae2c - HT Error Capture 1 register */ + uint hec2; /* 0xae30 - HT Error Capture 2 register */ + char res32[460]; } ccsr_ht_t; /* DMA Registers(0x2_1000-0x2_2000) */ @@ -505,14 +505,14 @@ typedef struct ccsr_dma { /* tsec1-4: 24000-28000 */ typedef struct ccsr_tsec { - uint id; /* 0x24000 - Controller ID Register */ + uint id; /* 0x24000 - Controller ID Register */ char res1[12]; uint ievent; /* 0x24010 - Interrupt Event Register */ uint imask; /* 0x24014 - Interrupt Mask Register */ uint edis; /* 0x24018 - Error Disabled Register */ char res2[4]; uint ecntrl; /* 0x24020 - Ethernet Control Register */ - char res2_1[4]; + char res2_1[4]; uint ptv; /* 0x24028 - Pause Time Value Register */ uint dmactrl; /* 0x2402c - DMA Control Register */ uint tbipa; /* 0x24030 - TBI PHY Address Register */ @@ -521,102 +521,102 @@ typedef struct ccsr_tsec { char res4[8]; uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ - char res4_1[4]; - uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ - uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ + char res4_1[4]; + uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ + uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ char res5[84]; uint tctrl; /* 0x24100 - Transmit Control Register */ uint tstat; /* 0x24104 - Transmit Status Register */ - uint dfvlan; /* 0x24108 - Default VLAN control word */ - char res6[4]; - uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ - uint tqueue; /* 0x24114 - Transmit Queue Control Register */ + uint dfvlan; /* 0x24108 - Default VLAN control word */ + char res6[4]; + uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ + uint tqueue; /* 0x24114 - Transmit Queue Control Register */ char res7[40]; - uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ - uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ - char res8[52]; - uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ - char res9[4]; - uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ - char res10[4]; - uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ - char res11[4]; - uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ - char res12[4]; - uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ - char res13[4]; - uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ - char res14[4]; - uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ - char res15[4]; - uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ - char res16[4]; - uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ - char res17[64]; + uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ + uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ + char res8[52]; + uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ + char res9[4]; + uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ + char res10[4]; + uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ + char res11[4]; + uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ + char res12[4]; + uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ + char res13[4]; + uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ + char res14[4]; + uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ + char res15[4]; + uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ + char res16[4]; + uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ + char res17[64]; uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ - char res18[4]; - uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ - char res19[4]; - uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ - char res20[4]; - uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ - char res21[4]; - uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ - char res22[4]; - uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ - char res23[4]; - uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ - char res24[4]; - uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ - char res25[192]; + char res18[4]; + uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ + char res19[4]; + uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ + char res20[4]; + uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ + char res21[4]; + uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ + char res22[4]; + uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ + char res23[4]; + uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ + char res24[4]; + uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ + char res25[192]; uint rctrl; /* 0x24300 - Receive Control Register */ uint rstat; /* 0x24304 - Receive Status Register */ char res26[8]; - uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ - uint rqueue; /* 0x24314 - Receive queue control register */ + uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ + uint rqueue; /* 0x24314 - Receive queue control register */ char res27[24]; - uint rbifx; /* 0x24330 - Receive bit field extract control Register */ - uint rqfar; /* 0x24334 - Receive queue filing table address Register */ - uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ - uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint rbifx; /* 0x24330 - Receive bit field extract control Register */ + uint rqfar; /* 0x24334 - Receive queue filing table address Register */ + uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ char res28[56]; - uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ - char res29[4]; - uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ - char res30[4]; - uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ - char res31[4]; - uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ - char res32[4]; - uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ - char res33[4]; - uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ - char res34[4]; - uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ - char res35[4]; - uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ - char res36[4]; - uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ - char res37[64]; + uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ + char res29[4]; + uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ + char res30[4]; + uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ + char res31[4]; + uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ + char res32[4]; + uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ + char res33[4]; + uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ + char res34[4]; + uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ + char res35[4]; + uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ + char res36[4]; + uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ + char res37[64]; uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ - char res38[4]; + char res38[4]; uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ - char res39[4]; + char res39[4]; uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ - char res40[4]; + char res40[4]; uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ - char res41[4]; + char res41[4]; uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ - char res42[4]; + char res42[4]; uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ - char res43[4]; + char res43[4]; uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ - char res44[4]; + char res44[4]; uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ - char res45[192]; + char res45[192]; uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ @@ -629,40 +629,40 @@ typedef struct ccsr_tsec { uint miimcon; /* 0x2452c - MII Management Control Register */ uint miimstat; /* 0x24530 - MII Management Status Register */ uint miimind; /* 0x24534 - MII Management Indicator Register */ - uint ifctrl; /* 0x24538 - Interface Contrl Register */ + uint ifctrl; /* 0x24538 - Interface Contrl Register */ uint ifstat; /* 0x2453c - Interface Status Register */ uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ - uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ - uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ - uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ - uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ - uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ - uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ - uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ - uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ - uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ - uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ - uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ - uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ - uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ - uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ - uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ - uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ - uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ - uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ - uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ - uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ - uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ - uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ - uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ - uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ - uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ - uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ - uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ - uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ - uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ - uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ + uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ + uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ + uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ + uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ + uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ + uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ + uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ + uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ + uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ + uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ + uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ + uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ + uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ + uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ + uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ + uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ + uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ + uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ + uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ + uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ + uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ + uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ + uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ + uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ + uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ + uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ + uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ + uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ + uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ + uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ char res48[192]; uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ @@ -712,7 +712,7 @@ typedef struct ccsr_tsec { uint car2; /* 0x24734 - Carry Register Two */ uint cam1; /* 0x24738 - Carry Mask Register One */ uint cam2; /* 0x2473c - Carry Mask Register Two */ - uint rrej; /* 0x24740 - Receive filer rejected packet counter */ + uint rrej; /* 0x24740 - Receive filer rejected packet counter */ char res50[188]; uint iaddr0; /* 0x24800 - Indivdual address register 0 */ uint iaddr1; /* 0x24804 - Indivdual address register 1 */ @@ -732,11 +732,11 @@ typedef struct ccsr_tsec { uint gaddr6; /* 0x24898 - Global address register 6 */ uint gaddr7; /* 0x2489c - Global address register 7 */ char res52[352]; - uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ - char res53[500]; - uint attr; /* 0x24BF8 - DMA Attribute register */ - uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ - char res54[1024]; + uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ + char res53[500]; + uint attr; /* 0x24BF8 - DMA Attribute register */ + uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ + char res54[1024]; } ccsr_tsec_t; /* PIC Registers(0x4_0000-0x6_1000) */ @@ -833,7 +833,7 @@ typedef struct ccsr_pic { char res45[12]; uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ char res46[12]; - uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ + uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ char res47[12]; uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ char res48[60]; @@ -1024,7 +1024,7 @@ typedef struct ccsr_pic { uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ char res141[12]; uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ - char res142[4108]; + char res142[4108]; uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ char res143[12]; uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ @@ -1109,7 +1109,7 @@ typedef struct ccsr_rio { uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ - uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ char res13[12]; uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ @@ -1133,7 +1133,7 @@ typedef struct ccsr_rio { char res22[20]; uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ char res23[4]; - uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ char res24[2716]; uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ @@ -1282,13 +1282,13 @@ typedef struct ccsr_rio { uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ - uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ char res57[100]; uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ uint pwsr; /* 0xd34e4 - Port-Write Status Register */ uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ - char res58[51984]; + char res58[51984]; } ccsr_rio_t; /* Global Utilities Register Block(0xe_0000-0xf_ffff) */ @@ -1313,7 +1313,7 @@ typedef struct ccsr_gur { char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ #define MPC86xx_DEVDISR_PCIEX1 0x80000000 -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 +#define MPC86xx_DEVDISR_PCIEX2 0x40000000 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1327,11 +1327,11 @@ typedef struct ccsr_gur { uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ char res12[12]; uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - int res13[57]; - uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ - int res14[6]; - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ - char res15[61656]; + int res13[57]; + uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ + int res14[6]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15[61656]; } ccsr_gur_t; typedef struct immap { @@ -1340,21 +1340,21 @@ typedef struct immap { ccsr_i2c_t im_i2c; ccsr_duart_t im_duart; ccsr_lbc_t im_lbc; - ccsr_ddr_t im_ddr2; - char res1[4096]; + ccsr_ddr_t im_ddr2; + char res1[4096]; ccsr_pex_t im_pex1; - ccsr_pex_t im_pex2; - ccsr_ht_t im_ht; - char res2[90112]; + ccsr_pex_t im_pex2; + ccsr_ht_t im_ht; + char res2[90112]; ccsr_dma_t im_dma; - char res3[8192]; + char res3[8192]; ccsr_tsec_t im_tsec1; ccsr_tsec_t im_tsec2; - ccsr_tsec_t im_tsec3; - ccsr_tsec_t im_tsec4; - char res4[98304]; + ccsr_tsec_t im_tsec3; + ccsr_tsec_t im_tsec4; + char res4[98304]; ccsr_pic_t im_pic; - char res5[389120]; + char res5[389120]; ccsr_rio_t im_rio; ccsr_gur_t im_gur; } immap_t; diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index c704d4659..6e883f73f 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -85,7 +85,6 @@ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 - /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -94,7 +93,6 @@ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - /* * DDR Setup */ @@ -317,7 +315,6 @@ #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ - #if defined(CONFIG_PCI) #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -353,7 +350,6 @@ #endif /* CONFIG_PCI */ - #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI @@ -384,7 +380,6 @@ #endif /* CONFIG_TSEC_ENET */ - /* * BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR @@ -462,9 +457,6 @@ #define CFG_IBAT7L 0x00000000 #define CFG_IBAT7U 0x00000000 - - - /* * Environment */ @@ -572,7 +564,6 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif - /* * Environment Configuration */ From 1fd5699a4a24f5c1dab1b32f480bace1ebb9fc3e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Oct 2006 17:19:03 -0500 Subject: [PATCH 092/101] Coding style changes to remove local varible blocks and reformat a bit nicer. --- cpu/mpc85xx/spd_sdram.c | 134 +++++++++++++++++++------------------- cpu/mpc86xx/spd_sdram.c | 138 +++++++++++++++++++--------------------- 2 files changed, 128 insertions(+), 144 deletions(-) diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index af99282dd..7507801ee 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -131,8 +131,8 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) 800, 900, 250, - 330, /* FIXME: Is 333 better/valid? */ - 660, /* FIXME: Is 667 better/valid? */ + 330, + 660, 750, 0, /* undefined */ 0 /* undefined */ @@ -146,6 +146,28 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) } +/* + * Determine Refresh Rate. Ignore self refresh bit on DDR I. + * Table from SPD Spec, Byte 12, converted to picoseconds and + * filled in with "default" normal values. + */ +unsigned int determine_refresh_rate(unsigned int spd_refresh) +{ + unsigned int refresh_time_ns[8] = { + 15625000, /* 0 Normal 1.00x */ + 3900000, /* 1 Reduced .25x */ + 7800000, /* 2 Extended .50x */ + 31300000, /* 3 Extended 2.00x */ + 62500000, /* 4 Extended 4.00x */ + 125000000, /* 5 Extended 8.00x */ + 15625000, /* 6 Normal 1.00x filler */ + 15625000, /* 7 Normal 1.00x filler */ + }; + + return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]); +} + + long int spd_sdram(void) { @@ -157,6 +179,10 @@ spd_sdram(void) unsigned int rank_density; unsigned int odt_rd_cfg, odt_wr_cfg; unsigned int odt_cfg, mode_odt_enable; + unsigned int refresh_clk; +#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL + unsigned char clk_adjust; +#endif unsigned int dqs_cfg; unsigned char twr_clk, twtr_clk, twr_auto_clk; unsigned int tCKmin_ps, tCKmax_ps; @@ -740,38 +766,21 @@ spd_sdram(void) ddr->sdram_mode_2 = 0; debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); - /* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. + * Determine Refresh Rate. */ - { - unsigned int refresh_clk; - unsigned int refresh_time_ns[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]); - - /* - * Set BSTOPRE to 0x100 for page mode - * If auto-charge is used, set BSTOPRE = 0 - */ - ddr->sdram_interval = - (0 - | (refresh_clk & 0x3fff) << 16 - | 0x100 - ); - debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); - } + refresh_clk = determine_refresh_rate(spd.refresh & 0x7); + + /* + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 + */ + ddr->sdram_interval = + (0 + | (refresh_clk & 0x3fff) << 16 + | 0x100 + ); + debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); /* * Is this an ECC DDR chip? @@ -835,28 +844,23 @@ spd_sdram(void) #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL - { - unsigned char clk_adjust; + /* + * Setup the clock control. + * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 + * SDRAM_CLK_CNTL[5-7] = Clock Adjust + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) + clk_adjust = 0x6; + else + clk_adjust = 0x7; - /* - * Setup the clock control. - * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 - * SDRAM_CLK_CNTL[5-7] = Clock Adjust - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - clk_adjust = 0x6; - } else { - clk_adjust = 0x7; - } - - ddr->sdram_clk_cntl = (0 + ddr->sdram_clk_cntl = (0 | 0x80000000 | (clk_adjust << 23) ); - debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); - } + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); #endif /* @@ -1081,26 +1085,16 @@ ddr_enable_ecc(unsigned int dram_size) } } - /* 8K */ - dma_xfer((uint *)0x2000, 0x2000, (uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000, 0x4000, (uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000, 0x8000, (uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000, 0x10000, (uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000, 0x20000, (uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000, 0x40000, (uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000, 0x80000, (uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000, 0x100000, (uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000, 0x200000, (uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000, 0x400000, (uint *)0); + dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */ + dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */ + dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */ + dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */ + dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */ + dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */ + dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ for (i = 1; i < dram_size / 0x800000; i++) { dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 39da3cc53..97bbf4386 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -152,6 +152,28 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) } +/* + * Determine Refresh Rate. Ignore self refresh bit on DDR I. + * Table from SPD Spec, Byte 12, converted to picoseconds and + * filled in with "default" normal values. + */ +unsigned int determine_refresh_rate(unsigned int spd_refresh) +{ + unsigned int refresh_time_ns[8] = { + 15625000, /* 0 Normal 1.00x */ + 3900000, /* 1 Reduced .25x */ + 7800000, /* 2 Extended .50x */ + 31300000, /* 3 Extended 2.00x */ + 62500000, /* 4 Extended 4.00x */ + 125000000, /* 5 Extended 8.00x */ + 15625000, /* 6 Normal 1.00x filler */ + 15625000, /* 7 Normal 1.00x filler */ + }; + + return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]); +} + + long int spd_init(unsigned char i2c_address, unsigned int ddr_num, unsigned int dimm_num, unsigned int start_addr) @@ -164,6 +186,10 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, unsigned int rank_density; unsigned int odt_rd_cfg, odt_wr_cfg; unsigned int odt_cfg, mode_odt_enable; + unsigned int refresh_clk; +#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL + unsigned char clk_adjust; +#endif unsigned int dqs_cfg; unsigned char twr_clk, twtr_clk, twr_auto_clk; unsigned int tCKmin_ps, tCKmax_ps; @@ -197,7 +223,6 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, /* * Read SPD information. */ - debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address); memset((void *)&spd, 0, sizeof(spd)); CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd)); @@ -757,7 +782,6 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps; } - /* * Mode Reg in bits 16 ~ 31, * Extended Mode Reg 1 in bits 0 ~ 15. @@ -783,45 +807,28 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1); - /* * Clear EMRS2 and EMRS3. */ ddr->sdram_mode_2 = 0; debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); + /* + * Determine Refresh Rate. + */ + refresh_clk = determine_refresh_rate(spd.refresh & 0x7); /* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 */ - { - unsigned int refresh_clk; - unsigned int refresh_time_ns[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; + ddr->sdram_interval = + (0 + | (refresh_clk & 0x3fff) << 16 + | 0x100 + ); + debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); - refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]); - - /* - * Set BSTOPRE to 0x100 for page mode - * If auto-charge is used, set BSTOPRE = 0 - */ - ddr->sdram_interval = - (0 - | (refresh_clk & 0x3fff) << 16 - | 0x100 - ); - debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); - } /* * Is this an ECC DDR chip? @@ -885,31 +892,25 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL - { - unsigned char clk_adjust; + /* + * Setup the clock control. + * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 + * SDRAM_CLK_CNTL[5-7] = Clock Adjust + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) + clk_adjust = 0x6; + else + clk_adjust = 0x7; - /* - * Setup the clock control. - * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 - * SDRAM_CLK_CNTL[5-7] = Clock Adjust - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - clk_adjust = 0x6; - } else { - clk_adjust = 0x7; - } - - ddr->sdram_clk_cntl = (0 + ddr->sdram_clk_cntl = (0 | 0x80000000 | (clk_adjust << 23) ); - debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); - } + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); #endif - /* * Figure out memory size in Megabytes. */ @@ -1259,10 +1260,9 @@ spd_sdram(void) */ if (!ddr1_enabled && !ddr2_enabled) return 0; - else { - printf("Non-interleaved"); - return memsize_total * 1024 * 1024; - } + + printf("Non-interleaved"); + return memsize_total * 1024 * 1024; #endif /* CONFIG_DDR_INTERLEAVE */ } @@ -1297,26 +1297,16 @@ ddr_enable_ecc(unsigned int dram_size) } } - /* 8K */ - dma_xfer((uint *)0x2000, 0x2000, (uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000, 0x4000, (uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000, 0x8000, (uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000, 0x10000, (uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000, 0x20000, (uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000, 0x40000, (uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000, 0x80000, (uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000, 0x100000, (uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000, 0x200000, (uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000, 0x400000, (uint *)0); + dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */ + dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */ + dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */ + dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */ + dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */ + dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */ + dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ for (i = 1; i < dram_size / 0x800000; i++) { dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); From bf651baa365e5447246aad6a633ccd667cf24a39 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 11 Oct 2006 10:10:43 -0500 Subject: [PATCH 093/101] Move "ar" flags to config.mk to allow for silent "make -s" --- board/mpc8641hpcn/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 46214ed21..4b68c3674 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: rm -f $(OBJS) $(SOBJS) From 1eaf3a5ff4960a46f3a9063568ba2af7883f07c5 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 10 Oct 2006 00:23:32 -0600 Subject: [PATCH 094/101] Fix possible uninitialized variable compiler warning. When CONFIG_OF_FLAG_TREE is set, the compiler complains that 'len' in do_bootm_linux() may be uninitialized. There is no possibility in the current code that len will get used uninitialized, but this fix follows the existing convention of setting both len and data to zero at the same time. Signed-off-by: Grant Likely --- common/cmd_bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index e2cb6b93c..c533c00d6 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -625,7 +625,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, /* Look for a '-' which indicates to ignore the ramdisk argument */ if (argc >= 3 && strcmp(argv[2], "-") == 0) { debug ("Skipping initrd\n"); - data = 0; + len = data = 0; } else #endif From 0ee90cb77e01d6e8ccd37e1bd96678597875c391 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 12 Oct 2006 10:42:36 -0500 Subject: [PATCH 095/101] Remove unneeded include files and local variable. Signed-off-by: Jon Loeliger --- drivers/tsec.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/tsec.c b/drivers/tsec.c index 30dca1152..770517b87 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -12,8 +12,6 @@ */ #include -#include -#include #include #include #include @@ -838,7 +836,6 @@ struct phy_info phy_info_M88E1111S = { static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) { - unsigned int temp; uint mii_data = read_phy_reg(priv, mii_reg); /* Setting MIIM_88E1145_PHY_EXT_CR */ From 5f3249a0a168e446a4cc9669b2bce0bc456f0a09 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 13 Oct 2006 16:47:53 -0500 Subject: [PATCH 096/101] Fixed leading whitespace issues. Removed spurious LAWAR thing. Signed-off-by: Jon Loeliger --- include/asm-ppc/mmu.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 5c38ce1e7..914f28b46 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -117,8 +117,8 @@ typedef struct _P601_BAT { */ typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ } pte; #define PD_SHIFT (10+12) /* Page directory */ @@ -448,7 +448,6 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_HT 0x00200000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 From 13a7fcdf37f6ea9429ae04c9df67f893364cfe4b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 11:33:52 -0500 Subject: [PATCH 097/101] * Fix a bunch of compiler warnings for gcc 4.0 Signed-off-by: Matthew McClintock --- board/cds/mpc8541cds/mpc8541cds.c | 4 +--- board/cds/mpc8548cds/mpc8548cds.c | 2 -- board/cds/mpc8555cds/mpc8555cds.c | 2 -- board/mpc8540ads/mpc8540ads.c | 3 --- board/mpc8560ads/mpc8560ads.c | 2 -- board/pm854/pm854.c | 2 -- board/pm856/pm856.c | 2 -- board/stxgp3/stxgp3.c | 2 -- board/tqm85xx/tqm85xx.c | 2 -- common/ft_build.c | 10 +++++----- cpu/mpc85xx/pci.c | 5 +++++ include/ft_build.h | 2 ++ include/pci.h | 3 +++ 13 files changed, 16 insertions(+), 25 deletions(-) diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index c2b3009fd..a42904cf7 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -497,8 +497,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller **hose); - - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 66219e395..41bcf8851 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -323,8 +323,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller **hose); - pci_mpc85xx_init(&hose); #endif } diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 012181c31..d980ea631 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -497,8 +497,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(hose); #endif } diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index fbcb39729..914e51a76 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -33,7 +33,6 @@ #if defined(CONFIG_OF_FLAT_TREE) #include -extern void ft_cpu_setup(void *blob, bd_t *bd); #endif @@ -327,8 +326,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index f9d75e805..c1572a35d 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -539,8 +539,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 94c492f78..6ead1d063 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -289,8 +289,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 504470837..a10075451 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -442,8 +442,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index 2b3949cd7..a58c043b6 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -375,8 +375,6 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index b4ef5afe7..256c076c7 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -408,8 +408,6 @@ static struct pci_controller hose = { void pci_init_board (void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init (struct pci_controller *hose); - pci_mpc85xx_init (&hose); #endif /* CONFIG_PCI */ } diff --git a/common/ft_build.c b/common/ft_build.c index 87883cc7d..980e40f55 100644 --- a/common/ft_build.c +++ b/common/ft_build.c @@ -87,9 +87,9 @@ static int lookup_string(struct ft_cxt *cxt, const char *name) p = cxt->p; while (p < cxt->p_end) { - if (strcmp(p, name) == 0) + if (strcmp((char *)p, name) == 0) return p - cxt->p; - p += strlen(p) + 1; + p += strlen((char *)p) + 1; } return -1; @@ -143,9 +143,9 @@ void ft_init_cxt(struct ft_cxt *cxt, void *blob) cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY; } - cxt->p_start = (char*)bph + bph->off_dt_struct; - cxt->p_end = (char *)bph + bph->totalsize; - cxt->p = (char *)bph + bph->off_dt_strings; + cxt->p_start = (u8 *)bph + bph->off_dt_struct; + cxt->p_end = (u8 *)bph + bph->totalsize; + cxt->p = (u8 *)bph + bph->off_dt_strings; } /* add a reserver physical area to the rsvmap */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index cfb7dcdc8..84f839ae1 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,6 +29,9 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #if defined(CONFIG_PCI) @@ -42,7 +45,9 @@ pci_mpc85xx_init(struct pci_controller *board_hose) volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; volatile ccsr_pcix_t *pcix = &immap->im_pcix; +#ifdef CONFIG_MPC85XX_PCI2 volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2; +#endif volatile ccsr_gur_t *gur = &immap->im_gur; struct pci_controller * hose; diff --git a/include/ft_build.h b/include/ft_build.h index f5156879d..89c689c08 100644 --- a/include/ft_build.h +++ b/include/ft_build.h @@ -64,6 +64,8 @@ void *ft_get_prop(void *bphp, const char *propname, int *szp); #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup(void *blob, bd_t *bd); +void ft_cpu_setup(void *blob, bd_t *bd); +void ft_pci_setup(void *blob, bd_t *bd); #endif #endif diff --git a/include/pci.h b/include/pci.h index e0e8783a7..7c9a0e344 100644 --- a/include/pci.h +++ b/include/pci.h @@ -501,4 +501,7 @@ extern int pci_hose_config_device(struct pci_controller *hose, extern void pci_mpc824x_init (struct pci_controller *hose); #endif +#ifdef CONFIG_MPC85xx +extern void pci_mpc85xx_init (struct pci_controller *hose); +#endif #endif /* _PCI_H */ From 7237c033b02fe295880435f1eb80819a0c987532 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 11:02:16 -0500 Subject: [PATCH 098/101] Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.c in an effort to begin to unify the umpteen FSL I2C drivers that are all otherwise very similar. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/Makefile | 2 +- drivers/Makefile | 3 +- cpu/mpc86xx/i2c.c => drivers/fsl_i2c.c | 118 ++++++++++--------------- include/asm-ppc/fsl_i2c.h | 90 +++++++++++++++++++ include/configs/MPC8641HPCN.h | 1 + 5 files changed, 142 insertions(+), 72 deletions(-) rename cpu/mpc86xx/i2c.c => drivers/fsl_i2c.c (56%) create mode 100644 include/asm-ppc/fsl_i2c.h diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index ad5b36def..de5561e92 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a START = start.o #resetvec.o SOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o pcie_indirect.o i2c.o spd_sdram.o + pci.o pcie_indirect.o spd_sdram.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/drivers/Makefile b/drivers/Makefile index 0f84969a9..b191018c7 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -50,7 +50,8 @@ COBJS = 3c589.o 5701rls.o ali512x.o \ videomodes.o w83c553f.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ - rpx_pcmcia.o + rpx_pcmcia.o \ + fsl_i2c.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/cpu/mpc86xx/i2c.c b/drivers/fsl_i2c.c similarity index 56% rename from cpu/mpc86xx/i2c.c rename to drivers/fsl_i2c.c index d99ecb92d..72b2556b2 100644 --- a/cpu/mpc86xx/i2c.c +++ b/drivers/fsl_i2c.c @@ -1,23 +1,9 @@ /* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao - * Adapted for Motorola 85xx chip. - * - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Modified for MPC86xx by Jeff Brown - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. + * Copyright 2006 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -30,56 +16,49 @@ * MA 02111-1307 USA */ + #include #include -#include #ifdef CONFIG_HARD_I2C -#include -#define TIMEOUT (CFG_HZ/4) +#include +#include -#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3100)) +#define I2C_TIMEOUT (CFG_HZ / 4) -#define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[4] -#define I2CCCR &I2C_Addr[8] -#define I2CCSR &I2C_Addr[12] -#define I2CCDR &I2C_Addr[16] -#define I2CDFSRR &I2C_Addr[20] +#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) -#define I2C_READ 1 -#define I2C_WRITE 0 void i2c_init(int speed, int slaveadd) { /* stop I2C controller */ - writeb(0x0, I2CCCR); + writeb(0x0 , &I2C->cr); /* set clock */ - writeb(0x3f, I2CFDR); + writeb(0x3f, &I2C->fdr); /* set default filter */ - writeb(0x10, I2CDFSRR); + writeb(0x10, &I2C->dfsrr); /* write slave address */ - writeb(slaveadd, I2CADR); + writeb(slaveadd, &I2C->adr); /* clear status register */ - writeb(0x0, I2CCSR); + writeb(0x0, &I2C->sr); /* start I2C controller */ - writeb(MPC86xx_I2CCR_MEN, I2CCCR); + writeb(I2C_CR_MEN, &I2C->cr); } static __inline__ int i2c_wait4bus(void) { - ulong timeval = get_timer(0); + ulong timeval = get_timer (0); - while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { - if (get_timer(timeval) > TIMEOUT) { + while (readb(&I2C->sr) & I2C_SR_MBB) { + if (get_timer(timeval) > I2C_TIMEOUT) { return -1; } } @@ -94,42 +73,42 @@ i2c_wait(int write) ulong timeval = get_timer(0); do { - csr = readb(I2CCSR); - if (!(csr & MPC86xx_I2CSR_MIF)) + csr = readb(&I2C->sr); + if (!(csr & I2C_SR_MIF)) continue; - writeb(0x0, I2CCSR); + writeb(0x0, &I2C->sr); - if (csr & MPC86xx_I2CSR_MAL) { + if (csr & I2C_SR_MAL) { debug("i2c_wait: MAL\n"); return -1; } - if (!(csr & MPC86xx_I2CSR_MCF)) { + if (!(csr & I2C_SR_MCF)) { debug("i2c_wait: unfinished\n"); return -1; } - if (write == I2C_WRITE && (csr & MPC86xx_I2CSR_RXAK)) { + if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { debug("i2c_wait: No RXACK\n"); return -1; } return 0; - } while (get_timer(timeval) < TIMEOUT); + } while (get_timer (timeval) < I2C_TIMEOUT); debug("i2c_wait: timed out\n"); return -1; } static __inline__ int -i2c_write_addr(u8 dev, u8 dir, int rsta) +i2c_write_addr (u8 dev, u8 dir, int rsta) { - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX - | (rsta ? MPC86xx_I2CCR_RSTA : 0), - I2CCCR); + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX + | (rsta ? I2C_CR_RSTA : 0), + &I2C->cr); - writeb((dev << 1) | dir, I2CCDR); + writeb((dev << 1) | dir, &I2C->dr); if (i2c_wait(I2C_WRITE) < 0) return 0; @@ -142,11 +121,11 @@ __i2c_write(u8 *data, int length) { int i; - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX, - I2CCCR); + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, + &I2C->cr); for (i = 0; i < length; i++) { - writeb(data[i], I2CCDR); + writeb(data[i], &I2C->dr); if (i2c_wait(I2C_WRITE) < 0) break; @@ -160,12 +139,11 @@ __i2c_read(u8 *data, int length) { int i; - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA - | ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), - I2CCCR); + writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), + &I2C->cr); /* dummy read */ - readb(I2CCDR); + readb(&I2C->dr); for (i = 0; i < length; i++) { if (i2c_wait(I2C_READ) < 0) @@ -173,14 +151,14 @@ __i2c_read(u8 *data, int length) /* Generate ack on last next to last byte */ if (i == length - 2) - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA - | MPC86xx_I2CCR_TXAK, I2CCCR); + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, + &I2C->cr); /* Generate stop on last byte */ if (i == length - 1) - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR); + writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); - data[i] = readb(I2CCDR); + data[i] = readb(&I2C->dr); } return i; @@ -190,9 +168,9 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) { int i = 0; - u8 *a = (u8 *) &addr; + u8 *a = (u8*)&addr; - if (i2c_wait4bus() < 0) + if (i2c_wait4bus () < 0) goto exit; if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) @@ -206,8 +184,8 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_read(data, length); -exit: - writeb(MPC86xx_I2CCR_MEN, I2CCCR); + exit: + writeb(I2C_CR_MEN, &I2C->cr); return !(i == length); } @@ -216,7 +194,7 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) { int i = 0; - u8 *a = (u8 *) &addr; + u8 *a = (u8*)&addr; if (i2c_wait4bus() < 0) goto exit; @@ -229,8 +207,8 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_write(data, length); -exit: - writeb(MPC86xx_I2CCR_MEN, I2CCCR); + exit: + writeb(I2C_CR_MEN, &I2C->cr); return !(i == length); } @@ -247,13 +225,13 @@ i2c_probe(uchar chip) */ udelay(10000); - return i2c_read(chip, 0, 1, (char *)&tmp, 1); + return i2c_read(chip, 0, 1, (uchar *)&tmp, 1); } uchar i2c_reg_read(uchar i2c_addr, uchar reg) { - char buf[1]; + uchar buf[1]; i2c_read(i2c_addr, reg, 1, buf, 1); diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h new file mode 100644 index 000000000..76b1c4309 --- /dev/null +++ b/include/asm-ppc/fsl_i2c.h @@ -0,0 +1,90 @@ +/* + * Freescale I2C Controller + * + * Copyright 2006 Freescale Semiconductor, Inc. + * + * Based on earlier versions by Gleb Natapov , + * Xianghua Xiao , Eran Liberty (liberty@freescale.com), + * and Jeff Brown. + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_FSL_I2C_H_ +#define _ASM_FSL_I2C_H_ + +#include + +typedef struct fsl_i2c { + + u8 adr; /* I2C slave address */ + u8 res0[3]; +#define I2C_ADR 0xFE +#define I2C_ADR_SHIFT 1 +#define I2C_ADR_RES ~(I2C_ADR) + + u8 fdr; /* I2C frequency divider register */ + u8 res1[3]; +#define IC2_FDR 0x3F +#define IC2_FDR_SHIFT 0 +#define IC2_FDR_RES ~(IC2_FDR) + + u8 cr; /* I2C control redister */ + u8 res2[3]; +#define I2C_CR_MEN 0x80 +#define I2C_CR_MIEN 0x40 +#define I2C_CR_MSTA 0x20 +#define I2C_CR_MTX 0x10 +#define I2C_CR_TXAK 0x08 +#define I2C_CR_RSTA 0x04 +#define I2C_CR_BCST 0x01 + + u8 sr; /* I2C status register */ + u8 res3[3]; +#define I2C_SR_MCF 0x80 +#define I2C_SR_MAAS 0x40 +#define I2C_SR_MBB 0x20 +#define I2C_SR_MAL 0x10 +#define I2C_SR_BCSTM 0x08 +#define I2C_SR_SRW 0x04 +#define I2C_SR_MIF 0x02 +#define I2C_SR_RXAK 0x01 + + u8 dr; /* I2C data register */ + u8 res4[3]; +#define I2C_DR 0xFF +#define I2C_DR_SHIFT 0 +#define I2C_DR_RES ~(I2C_DR) + + u8 dfsrr; /* I2C digital filter sampling rate register */ + u8 res5[3]; +#define I2C_DFSRR 0x3F +#define I2C_DFSRR_SHIFT 0 +#define I2C_DFSRR_RES ~(I2C_DR) + + /* Fill out the reserved block */ + u8 res6[0xE8]; +} fsl_i2c_t; + + +#define I2C_READ 1 +#define I2C_WRITE 0 + +#endif /* _ASM_I2C_H_ */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 6e883f73f..81bb7cf13 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -279,6 +279,7 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x3100 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* From 4d45f69e362b05892c9e92a7907e5820995612aa Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 19 Oct 2006 12:02:24 -0500 Subject: [PATCH 099/101] Rewrite a series of goto statements as a sequences of conditional expressions instead. Use consistent return code 0/-1 for good/bad indicators. Include one fewer file if the driver isn't used at all. Signed-off-by: Jon Loeliger --- drivers/fsl_i2c.c | 52 +++++++++++++++++++---------------------------- 1 file changed, 21 insertions(+), 31 deletions(-) diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index 72b2556b2..af191915e 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -16,18 +16,16 @@ * MA 02111-1307 USA */ - #include -#include #ifdef CONFIG_HARD_I2C +#include #include #include #define I2C_TIMEOUT (CFG_HZ / 4) - -#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) +#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) void @@ -170,24 +168,19 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) - goto exit; + if (i2c_wait4bus() >= 0 + && i2c_write_addr(dev, I2C_WRITE, 0) != 0 + && __i2c_write(&a[4 - alen], alen) == alen + && i2c_write_addr(dev, I2C_READ, 1) != 0) { + i = __i2c_read(data, length); + } - if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write(&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr(dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read(data, length); - - exit: writeb(I2C_CR_MEN, &I2C->cr); - return !(i == length); + if (i == length) + return 0; + + return -1; } int @@ -196,21 +189,18 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus() < 0) - goto exit; + if (i2c_wait4bus() >= 0 + && i2c_write_addr(dev, I2C_WRITE, 0) != 0 + && __i2c_write(&a[4 - alen], alen) == alen) { + i = __i2c_write(data, length); + } - if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write(&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write(data, length); - - exit: writeb(I2C_CR_MEN, &I2C->cr); - return !(i == length); + if (i == length) + return 0; + + return -1; } int From 2047672684cf85cb6f96a1fbc993180aaaf19a99 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Oct 2006 15:50:15 -0500 Subject: [PATCH 100/101] Converted all 85xx boards to use a common FSL I2C driver. Introduced COFIG_FSL_I2C to select the common FSL I2C driver. And removed hard i2c path from a few u-boot.lds scipts too. Minor whitespace cleanups along the way. Signed-off-by: Jon Loeliger --- board/mpc8560ads/u-boot.lds | 1 - board/sbc8560/u-boot.lds | 1 - board/stxgp3/u-boot.lds | 1 - cpu/mpc85xx/Makefile | 2 +- cpu/mpc85xx/i2c.c | 265 ---------------------------------- drivers/fsl_i2c.c | 10 +- include/configs/MPC8540ADS.h | 8 +- include/configs/MPC8540EVAL.h | 8 +- include/configs/MPC8541CDS.h | 8 +- include/configs/MPC8548CDS.h | 8 +- include/configs/MPC8555CDS.h | 8 +- include/configs/MPC8560ADS.h | 8 +- include/configs/MPC8641HPCN.h | 5 +- include/configs/PM854.h | 8 +- include/configs/PM856.h | 8 +- include/configs/SBC8540.h | 8 +- include/configs/TQM85xx.h | 7 +- include/configs/sbc8560.h | 8 +- include/configs/stxgp3.h | 8 +- 19 files changed, 83 insertions(+), 297 deletions(-) delete mode 100644 cpu/mpc85xx/i2c.c diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds index 8dcee1f10..726a153f9 100644 --- a/board/mpc8560ads/u-boot.lds +++ b/board/mpc8560ads/u-boot.lds @@ -74,7 +74,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds index 48e19fe2a..048ac26b4 100644 --- a/board/sbc8560/u-boot.lds +++ b/board/sbc8560/u-boot.lds @@ -77,7 +77,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds index 3bc615021..1bbf20ae2 100644 --- a/board/stxgp3/u-boot.lds +++ b/board/stxgp3/u-boot.lds @@ -79,7 +79,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 7b32305dc..ff67dcdd3 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a START = start.o resetvec.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o + pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/i2c.c b/cpu/mpc85xx/i2c.c deleted file mode 100644 index 32dcf5d47..000000000 --- a/cpu/mpc85xx/i2c.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao - * Adapted for Motorola 85xx chip. - * - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_HARD_I2C -#include - -#define TIMEOUT (CFG_HZ/4) - -#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000)) - -#define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[4] -#define I2CCCR &I2C_Addr[8] -#define I2CCSR &I2C_Addr[12] -#define I2CCDR &I2C_Addr[16] -#define I2CDFSRR &I2C_Addr[20] - -#define I2C_READ 1 -#define I2C_WRITE 0 - -void -i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writeb(0x0, I2CCCR); - - /* set clock */ - writeb(0x3f, I2CFDR); - - /* set default filter */ - writeb(0x10,I2CDFSRR); - - /* write slave address */ - writeb(slaveadd, I2CADR); - - /* clear status register */ - writeb(0x0, I2CCSR); - - /* start I2C controller */ - writeb(MPC85xx_I2CCR_MEN, I2CCCR); -} - -static __inline__ int -i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - - while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) { - if (get_timer (timeval) > TIMEOUT) { - return -1; - } - } - - return 0; -} - -static __inline__ int -i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer (0); - - do { - csr = readb(I2CCSR); - - if (!(csr & MPC85xx_I2CSR_MIF)) - continue; - - writeb(0x0, I2CCSR); - - if (csr & MPC85xx_I2CSR_MAL) { - debug("i2c_wait: MAL\n"); - return -1; - } - - if (!(csr & MPC85xx_I2CSR_MCF)) { - debug("i2c_wait: unfinished\n"); - return -1; - } - - if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) { - debug("i2c_wait: No RXACK\n"); - return -1; - } - - return 0; - } while (get_timer (timeval) < TIMEOUT); - - debug("i2c_wait: timed out\n"); - return -1; -} - -static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | - (rsta?MPC85xx_I2CCR_RSTA:0), - I2CCCR); - - writeb((dev << 1) | dir, I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - - return 1; -} - -static __inline__ int -__i2c_write (u8 *data, int length) -{ - int i; - - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, - I2CCCR); - - for (i=0; i < length; i++) { - writeb(data[i], I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - - return i; -} - -static __inline__ int -__i2c_read (u8 *data, int length) -{ - int i; - - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), - I2CCCR); - - /* dummy read */ - readb(I2CCDR); - - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - MPC85xx_I2CCR_TXAK, - I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); - - data[i] = readb(I2CCDR); - } - - return i; -} - -int -i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - - exit: - writeb(MPC85xx_I2CCR_MEN, I2CCCR); - - return !(i == length); -} - -int -i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - - exit: - writeb(MPC85xx_I2CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay(10000); - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); -} - -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index af191915e..65c27439e 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -18,11 +18,14 @@ #include +#ifdef CONFIG_FSL_I2C #ifdef CONFIG_HARD_I2C #include +#include /* Functional interface */ + #include -#include +#include /* HW definitions */ #define I2C_TIMEOUT (CFG_HZ / 4) #define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) @@ -32,7 +35,7 @@ void i2c_init(int speed, int slaveadd) { /* stop I2C controller */ - writeb(0x0 , &I2C->cr); + writeb(0x0, &I2C->cr); /* set clock */ writeb(0x3f, &I2C->fdr); @@ -53,7 +56,7 @@ i2c_init(int speed, int slaveadd) static __inline__ int i2c_wait4bus(void) { - ulong timeval = get_timer (0); + ulong timeval = get_timer(0); while (readb(&I2C->sr) & I2C_SR_MBB) { if (get_timer(timeval) > I2C_TIMEOUT) { @@ -235,3 +238,4 @@ i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) } #endif /* CONFIG_HARD_I2C */ +#endif /* CONFIG_FSL_I2C */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 31ffbaf15..74a84f4e8 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -312,12 +312,16 @@ #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 1af923103..418a3a38e 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -179,12 +179,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* General PCI */ #define CFG_PCI_MEM_BASE 0x80000000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 2b87f1bd6..db389cfe6 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -320,13 +320,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 03ab976d1..be8f93ffb 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -326,13 +326,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 771a9d3b9..4c8b4e73f 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -320,13 +320,17 @@ extern unsigned long get_clock_freq(void); #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 1c684f2fd..835bf5cb6 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -302,12 +302,16 @@ #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 81bb7cf13..246ac7f31 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -275,12 +275,13 @@ /* * I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_OFFSET 0x3100 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 /* * RapidIO MMU diff --git a/include/configs/PM854.h b/include/configs/PM854.h index da0118677..4fb54402b 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -193,12 +193,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 4d834878e..87ab93487 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -190,12 +190,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 0451b2081..f8e3397a3 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -214,12 +214,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index bc3b9aa1d..cce462490 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -192,12 +192,17 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* I2C RTC */ #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 5a434dc76..6e4fdb249 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -197,12 +197,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index e218597db..625cf2014 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -172,8 +172,11 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -183,6 +186,7 @@ /* I did the 'if 0' so we could keep the syntax above if ever needed. */ #undef CFG_I2C_NOPROBES #endif +#define CFG_I2C_OFFSET 0x3000 /* RapdIO Map configuration, mapped 1:1. */ From f5012827df11ca0c9be1df5f8b153e188dc2fa7c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 20 Oct 2006 15:54:34 -0500 Subject: [PATCH 101/101] Fix compilation warnings on a few 85xx boards. Signed-off-by: Jon Loeliger --- board/cds/common/ft_board.c | 2 -- board/cds/mpc8548cds/mpc8548cds.c | 2 +- board/mpc8560ads/mpc8560ads.c | 4 ++++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c index a897d045a..9d97905ca 100644 --- a/board/cds/common/ft_board.c +++ b/board/cds/common/ft_board.c @@ -45,8 +45,6 @@ static void cds_pci_fixup(void *blob) /* We rotate the interrupt pins so that the mapping * changes depending on the slot the carrier card is in. */ - int j; - map[3] = ((map[3] + slot - 2) % 4) + 1; map+=7; diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 41bcf8851..7433ebf25 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -329,7 +329,7 @@ pci_init_board(void) int last_stage_init(void) { - unsigned int temp; + unsigned short temp; /* Change the resistors for the PHY */ /* This is needed to get the RGMII working for the 1.3+ diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index c1572a35d..d19bad683 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -33,6 +33,10 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif