pinctrl: tegra: add XUSB pad controller
This is a combined pincontrol/PHY driver for the SerDes lanes on Tegra K1. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach
Sascha Hauer
parent
3e41e7561a
commit
d712ce1824
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@ -60,6 +60,14 @@ config PINCTRL_TEGRA30
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help
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The pinmux controller found on the Tegra 30+ line of SoCs.
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config PINCTRL_TEGRA_XUSB
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bool
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default y if ARCH_TEGRA_124_SOC
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select GENERIC_PHY
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help
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The pinmux controller found on the Tegra 124 line of SoCs used for
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the SerDes lanes.
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source drivers/pinctrl/mvebu/Kconfig
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endif
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@ -7,5 +7,6 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
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obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
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obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
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obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
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obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
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obj-$(CONFIG_ARCH_MVEBU) += mvebu/
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@ -0,0 +1,519 @@
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/*
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* Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* Partly based on code
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* Copyright (C) 2014, NVIDIA CORPORATION.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <clock.h>
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#include <init.h>
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#include <io.h>
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#include <malloc.h>
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#include <pinctrl.h>
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#include <linux/err.h>
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#include <linux/reset.h>
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#include <linux/phy/phy.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
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#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
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#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
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#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
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#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
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struct tegra_xusb_padctl_soc {
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const struct tegra_xusb_padctl_lane *lanes;
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unsigned int num_lanes;
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};
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struct tegra_xusb_padctl_lane {
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const char *name;
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unsigned int offset;
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unsigned int shift;
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unsigned int mask;
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unsigned int iddq;
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const char **funcs;
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unsigned int num_funcs;
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};
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struct tegra_xusb_padctl {
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struct device_d *dev;
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void __iomem *regs;
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struct reset_control *rst;
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const struct tegra_xusb_padctl_soc *soc;
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struct pinctrl_device pinctrl;
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struct phy_provider *provider;
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struct phy *phys[2];
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unsigned int enable;
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};
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static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
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unsigned long offset)
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{
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writel(value, padctl->regs + offset);
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}
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static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
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unsigned long offset)
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{
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return readl(padctl->regs + offset);
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}
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static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
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{
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u32 value;
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if (padctl->enable++ > 0)
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return 0;
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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return 0;
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}
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static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
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{
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u32 value;
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if (WARN_ON(padctl->enable == 0))
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return 0;
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if (--padctl->enable > 0)
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return 0;
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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udelay(100);
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value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
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value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
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return 0;
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}
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static int tegra_xusb_phy_init(struct phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
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return tegra_xusb_padctl_enable(padctl);
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}
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static int tegra_xusb_phy_exit(struct phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
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return tegra_xusb_padctl_disable(padctl);
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}
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static int pcie_phy_power_on(struct phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
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int err;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
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value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
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XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
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XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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err = wait_on_timeout(50 * MSECOND,
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padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1) &
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XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET);
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return err;
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}
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static int pcie_phy_power_off(struct phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
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return 0;
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}
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static const struct phy_ops pcie_phy_ops = {
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.init = tegra_xusb_phy_init,
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.exit = tegra_xusb_phy_exit,
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.power_on = pcie_phy_power_on,
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.power_off = pcie_phy_power_off,
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};
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static int sata_phy_power_on(struct phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
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int err;
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
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value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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err = wait_on_timeout(50 * MSECOND,
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padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1) &
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XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET);
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return err;
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}
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static int sata_phy_power_off(struct phy *phy)
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{
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struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
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u32 value;
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
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value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
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value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
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value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
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padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
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return 0;
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}
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static const struct phy_ops sata_phy_ops = {
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.init = tegra_xusb_phy_init,
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.exit = tegra_xusb_phy_exit,
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.power_on = sata_phy_power_on,
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.power_off = sata_phy_power_off,
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};
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static struct phy *tegra_xusb_padctl_xlate(struct device_d *dev,
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struct of_phandle_args *args)
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{
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struct tegra_xusb_padctl *padctl = dev->priv;
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unsigned int index = args->args[0];
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if (args->args_count <= 0)
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return ERR_PTR(-EINVAL);
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if (index >= ARRAY_SIZE(padctl->phys))
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return ERR_PTR(-EINVAL);
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return padctl->phys[index];
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}
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static int pinctrl_tegra_xusb_set_state(struct pinctrl_device *pdev,
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struct device_node *np)
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{
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struct tegra_xusb_padctl *padctl =
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container_of(pdev, struct tegra_xusb_padctl, pinctrl);
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struct device_node *childnode;
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int iddq = -1, i, j, k;
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const char *lanes, *func = NULL;
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const struct tegra_xusb_padctl_lane *lane = NULL;
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u32 val;
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/*
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* At first look if the node we are pointed at has children,
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* which we may want to visit.
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*/
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list_for_each_entry(childnode, &np->children, parent_list)
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pinctrl_tegra_xusb_set_state(pdev, childnode);
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/* read relevant state from devicetree */
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of_property_read_string(np, "nvidia,function", &func);
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of_property_read_u32_array(np, "nvidia,iddq", &iddq, 1);
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/* iterate over all lanes referenced in the dt node */
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for (i = 0; ; i++) {
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if (of_property_read_string_index(np, "nvidia,lanes", i, &lanes))
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break;
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for (j = 0; j < padctl->soc->num_lanes; j++) {
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if (!strcmp(lanes, padctl->soc->lanes[j].name)) {
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lane = &padctl->soc->lanes[j];
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break;
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}
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}
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/* if no matching lane is found */
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if (j == padctl->soc->num_lanes) {
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/* nothing matching found, warn and bail out */
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dev_warn(padctl->pinctrl.dev,
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"invalid lane %s referenced in node %s\n",
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lanes, np->name);
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continue;
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}
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if (func) {
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for (k = 0; k < lane->num_funcs; k++) {
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if (!strcmp(func, lane->funcs[k]))
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break;
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}
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if (k < lane->num_funcs) {
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val = padctl_readl(padctl, lane->offset);
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val &= ~(lane->mask << lane->shift);
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val |= k << lane->shift;
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padctl_writel(padctl, val, lane->offset);
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} else {
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dev_warn(padctl->pinctrl.dev,
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"invalid function %s for lane %s in node %s\n",
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func, lane->name, np->name);
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}
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}
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if (iddq >= 0) {
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if (lane->iddq) {
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val = padctl_readl(padctl, lane->offset);
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if (iddq)
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val &= ~BIT(lane->iddq);
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else
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val |= BIT(lane->iddq);
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padctl_writel(padctl, val, lane->offset);
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} else {
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dev_warn(padctl->pinctrl.dev,
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"invalid iddq setting for lane %s in node %s\n",
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lane->name, np->name);
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}
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}
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}
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return 0;
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}
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static struct pinctrl_ops pinctrl_tegra_xusb_ops = {
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.set_state = pinctrl_tegra_xusb_set_state,
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};
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static int pinctrl_tegra_xusb_probe(struct device_d *dev)
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{
|
||||
struct tegra_xusb_padctl *padctl;
|
||||
struct phy *phy;
|
||||
int err;
|
||||
|
||||
padctl = xzalloc(sizeof(*padctl));
|
||||
|
||||
dev->priv = padctl;
|
||||
padctl->dev = dev;
|
||||
|
||||
dev_get_drvdata(dev, (unsigned long *)&padctl->soc);
|
||||
|
||||
padctl->regs = dev_request_mem_region(dev, 0);
|
||||
if (IS_ERR(padctl->regs)) {
|
||||
dev_err(dev, "Could not get iomem region\n");
|
||||
return PTR_ERR(padctl->regs);
|
||||
}
|
||||
|
||||
padctl->rst = reset_control_get(dev, NULL);
|
||||
if (IS_ERR(padctl->rst))
|
||||
return PTR_ERR(padctl->rst);
|
||||
|
||||
err = reset_control_deassert(padctl->rst);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
padctl->pinctrl.dev = dev;
|
||||
padctl->pinctrl.ops = &pinctrl_tegra_xusb_ops;
|
||||
|
||||
err = pinctrl_register(&padctl->pinctrl);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to register pincontrol\n");
|
||||
err = -ENODEV;
|
||||
goto reset;
|
||||
}
|
||||
|
||||
phy = phy_create(dev, NULL, &pcie_phy_ops, NULL);
|
||||
if (IS_ERR(phy)) {
|
||||
err = PTR_ERR(phy);
|
||||
goto unregister;
|
||||
}
|
||||
|
||||
padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
|
||||
phy_set_drvdata(phy, padctl);
|
||||
|
||||
phy = phy_create(dev, NULL, &sata_phy_ops, NULL);
|
||||
if (IS_ERR(phy)) {
|
||||
err = PTR_ERR(phy);
|
||||
goto unregister;
|
||||
}
|
||||
|
||||
padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
|
||||
phy_set_drvdata(phy, padctl);
|
||||
|
||||
padctl->provider = of_phy_provider_register(dev, tegra_xusb_padctl_xlate);
|
||||
if (IS_ERR(padctl->provider)) {
|
||||
err = PTR_ERR(padctl->provider);
|
||||
dev_err(dev, "failed to register PHYs: %d\n", err);
|
||||
goto unregister;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
unregister:
|
||||
pinctrl_unregister(&padctl->pinctrl);
|
||||
reset:
|
||||
reset_control_assert(padctl->rst);
|
||||
return err;
|
||||
}
|
||||
|
||||
static const char *tegra124_otg_functions[] = {
|
||||
"snps",
|
||||
"xusb",
|
||||
"uart",
|
||||
"rsvd",
|
||||
};
|
||||
|
||||
static const char *tegra124_usb_functions[] = {
|
||||
"snps",
|
||||
"xusb",
|
||||
};
|
||||
|
||||
static const char *tegra124_pci_functions[] = {
|
||||
"pcie",
|
||||
"usb3",
|
||||
"sata",
|
||||
"rsvd",
|
||||
};
|
||||
|
||||
#define TEGRA124_LANE(_name, _offs, _shift, _mask, _iddq, _funcs, _num) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.offset = _offs, \
|
||||
.shift = _shift, \
|
||||
.mask = _mask, \
|
||||
.iddq = _iddq, \
|
||||
.num_funcs = _num, \
|
||||
.funcs = tegra124_##_funcs##_functions, \
|
||||
}
|
||||
|
||||
static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
|
||||
TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg, 4),
|
||||
TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg, 4),
|
||||
TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg, 4),
|
||||
TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb, 2),
|
||||
TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb, 2),
|
||||
TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb, 2),
|
||||
TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci, 4),
|
||||
TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci, 4),
|
||||
TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci, 4),
|
||||
TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci, 4),
|
||||
TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci, 4),
|
||||
TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci, 4),
|
||||
};
|
||||
|
||||
static const struct tegra_xusb_padctl_soc tegra124_soc = {
|
||||
.num_lanes = ARRAY_SIZE(tegra124_lanes),
|
||||
.lanes = tegra124_lanes,
|
||||
};
|
||||
|
||||
static __maybe_unused struct of_device_id pinctrl_tegra_xusb_dt_ids[] = {
|
||||
{
|
||||
.compatible = "nvidia,tegra124-xusb-padctl",
|
||||
.data = (unsigned long)&tegra124_soc,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct driver_d pinctrl_tegra_xusb_driver = {
|
||||
.name = "pinctrl-tegra-xusb",
|
||||
.probe = pinctrl_tegra_xusb_probe,
|
||||
.of_compatible = DRV_OF_COMPAT(pinctrl_tegra_xusb_dt_ids),
|
||||
};
|
||||
|
||||
static int pinctrl_tegra_xusb_init(void)
|
||||
{
|
||||
return platform_driver_register(&pinctrl_tegra_xusb_driver);
|
||||
}
|
||||
postcore_initcall(pinctrl_tegra_xusb_init);
|
||||
Loading…
Reference in New Issue