From d85cee442096f13d8677c5d61d0e0438cc8ecb0f Mon Sep 17 00:00:00 2001 From: Jan Luebbe Date: Sun, 22 Nov 2015 14:41:51 +0100 Subject: [PATCH] sysmobts: configure AEMIF CS3 for the FPGA Signed-off-by: Jan Luebbe --- arch/arm/boards/sysmobts/board.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boards/sysmobts/board.c b/arch/arm/boards/sysmobts/board.c index 149338ca2..e80e92585 100644 --- a/arch/arm/boards/sysmobts/board.c +++ b/arch/arm/boards/sysmobts/board.c @@ -180,8 +180,29 @@ static int sysmobts_coredevices_init(void) coredevice_initcall(sysmobts_coredevices_init); +#define DAVINCI_PLLM (0x01C40910) /* PLL 1 Multiplier */ +#define DAVINCI_AWCCR (0x01E00004) /* EMIF-A async wait cycle config register. */ +#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */ +#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */ +#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */ +#define DAVINCI_A2CR_VAL8 (0x00630591) /* EMIF-A CS3 value for FPGA. */ + static int sysmobts_devices_init(void) { + /* Configure AEMIF AWCCR */ + writel(DAVINCI_AWCCR_VAL, DAVINCI_AWCCR); + + /* DM644X @ 594/297 MHz */ + if ( (readl(DAVINCI_PLLM) & 0x0FF) < 22 ) { + /* Configure AEMIF CS3 (fpga) */ + writel(DAVINCI_A2CR_VAL, DAVINCI_A2CR); + + /* DM644X @ 810/405 MHz */ + } else { + /* Configure AEMIF CS3 (fpga) */ + writel(DAVINCI_A2CR_VAL8, DAVINCI_A2CR); + } + sysmobts_set_ethaddr(); platform_device_register(&dm644x_emac_device);