at91: Introduction of at91sam9261 SOC.
AT91sam9261 series is an ARM 926ej-s SOC family clocked at 190/100MHz. The first board that embeds at91sam9261 chip is the AT91SAM9261-EK. http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
parent
6a84a019ab
commit
d923f0dedb
|
|
@ -52,6 +52,7 @@ machine-$(CONFIG_ARCH_S3C24xx) := s3c24xx
|
|||
board-$(CONFIG_MACH_A9M2410) := a9m2410
|
||||
board-$(CONFIG_MACH_A9M2440) := a9m2440
|
||||
board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek
|
||||
board-$(CONFIG_MACH_AT91SAM9261EK) := at91sam9261ek
|
||||
board-$(CONFIG_MACH_AT91SAM9263EK) := at91sam9263ek
|
||||
board-$(CONFIG_MACH_AT91SAM9G20EK) := at91sam9260ek
|
||||
board-$(CONFIG_MACH_EDB9301) := edb93xx
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
obj-y += init.o
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
#!/bin/sh
|
||||
|
||||
# use 'dhcp' to do dhcp in barebox and in kernel
|
||||
# use 'none' if you want to skip kernel ip autoconfiguration
|
||||
ip=dhcp
|
||||
|
||||
# or set your networking parameters here
|
||||
#eth0.ipaddr=a.b.c.d
|
||||
#eth0.netmask=a.b.c.d
|
||||
#eth0.gateway=a.b.c.d
|
||||
#eth0.serverip=a.b.c.d
|
||||
|
||||
# can be either 'net' or 'nand'
|
||||
kernel_loc=net
|
||||
# can be either 'net', 'nand' or 'initrd'
|
||||
rootfs_loc=net
|
||||
|
||||
# can be either 'jffs2' or 'ubifs'
|
||||
rootfs_type=ubifs
|
||||
rootfsimage=root.$rootfs_type
|
||||
|
||||
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
|
||||
#kernelimage_type=zimage
|
||||
#kernelimage=zImage
|
||||
kernelimage_type=uimage
|
||||
kernelimage=uImage
|
||||
#kernelimage_type=raw
|
||||
#kernelimage=Image
|
||||
#kernelimage_type=raw_lzo
|
||||
#kernelimage=Image.lzo
|
||||
|
||||
nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)"
|
||||
rootfs_mtdblock_nand=3
|
||||
|
||||
autoboot_timeout=3
|
||||
|
||||
bootargs="console=ttyS0,115200"
|
||||
|
||||
# set a fancy prompt (if support is compiled in)
|
||||
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
|
||||
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sascha Hauer, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <net.h>
|
||||
#include <init.h>
|
||||
#include <environment.h>
|
||||
#include <asm/armlinux.h>
|
||||
#include <generated/mach-types.h>
|
||||
#include <partition.h>
|
||||
#include <fs.h>
|
||||
#include <fcntl.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <nand.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/io.h>
|
||||
#include <mach/at91sam9_smc.h>
|
||||
#include <mach/sam9_smc.h>
|
||||
#include <dm9000.h>
|
||||
|
||||
static struct atmel_nand_data nand_pdata = {
|
||||
.ale = 22,
|
||||
.cle = 21,
|
||||
/* .det_pin = ... not connected */
|
||||
.rdy_pin = AT91_PIN_PC15,
|
||||
.enable_pin = AT91_PIN_PC14,
|
||||
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
|
||||
.bus_width_16 = 1,
|
||||
#else
|
||||
.bus_width_16 = 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct sam9_smc_config ek_nand_smc_config = {
|
||||
.ncs_read_setup = 0,
|
||||
.nrd_setup = 1,
|
||||
.ncs_write_setup = 0,
|
||||
.nwe_setup = 1,
|
||||
|
||||
.ncs_read_pulse = 3,
|
||||
.nrd_pulse = 3,
|
||||
.ncs_write_pulse = 3,
|
||||
.nwe_pulse = 3,
|
||||
|
||||
.read_cycle = 5,
|
||||
.write_cycle = 5,
|
||||
|
||||
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
|
||||
.tdf_cycles = 2,
|
||||
};
|
||||
|
||||
static void ek_add_device_nand(void)
|
||||
{
|
||||
/* setup bus-width (8 or 16) */
|
||||
if (nand_pdata.bus_width_16)
|
||||
ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
|
||||
else
|
||||
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
|
||||
|
||||
/* configure chip-select 3 (NAND) */
|
||||
sam9_smc_configure(3, &ek_nand_smc_config);
|
||||
|
||||
at91_add_device_nand(&nand_pdata);
|
||||
}
|
||||
|
||||
/*
|
||||
* DM9000 ethernet device
|
||||
*/
|
||||
#if defined(CONFIG_DRIVER_NET_DM9000)
|
||||
static struct dm9000_platform_data dm9000_data = {
|
||||
.iobase = AT91_CHIPSELECT_2,
|
||||
.iodata = AT91_CHIPSELECT_2 + 4,
|
||||
.buswidth = DM9000_WIDTH_16,
|
||||
.srom = 0,
|
||||
};
|
||||
|
||||
static struct device_d dm9000_dev = {
|
||||
.id = 0,
|
||||
.name = "dm9000",
|
||||
.map_base = AT91_CHIPSELECT_2,
|
||||
.size = 8,
|
||||
.platform_data = &dm9000_data,
|
||||
};
|
||||
|
||||
/*
|
||||
* SMC timings for the DM9000.
|
||||
* Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
|
||||
*/
|
||||
static struct sam9_smc_config __initdata dm9000_smc_config = {
|
||||
.ncs_read_setup = 0,
|
||||
.nrd_setup = 2,
|
||||
.ncs_write_setup = 0,
|
||||
.nwe_setup = 2,
|
||||
|
||||
.ncs_read_pulse = 8,
|
||||
.nrd_pulse = 4,
|
||||
.ncs_write_pulse = 8,
|
||||
.nwe_pulse = 4,
|
||||
|
||||
.read_cycle = 16,
|
||||
.write_cycle = 16,
|
||||
|
||||
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
|
||||
.tdf_cycles = 1,
|
||||
};
|
||||
|
||||
static void __init ek_add_device_dm9000(void)
|
||||
{
|
||||
/* Configure chip-select 2 (DM9000) */
|
||||
sam9_smc_configure(2, &dm9000_smc_config);
|
||||
|
||||
/* Configure Reset signal as output */
|
||||
at91_set_gpio_output(AT91_PIN_PC10, 0);
|
||||
|
||||
/* Configure Interrupt pin as input, no pull-up */
|
||||
at91_set_gpio_input(AT91_PIN_PC11, 0);
|
||||
|
||||
register_device(&dm9000_dev);
|
||||
}
|
||||
#else
|
||||
static void __init ek_add_device_dm9000(void) {}
|
||||
#endif /* CONFIG_DRIVER_NET_DM9000 */
|
||||
|
||||
static int at91sam9261ek_devices_init(void)
|
||||
{
|
||||
|
||||
at91_add_device_sdram(64 * 1024 * 1024);
|
||||
ek_add_device_nand();
|
||||
ek_add_device_dm9000();
|
||||
|
||||
devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw");
|
||||
dev_add_bb_dev("self_raw", "self0");
|
||||
devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw");
|
||||
dev_add_bb_dev("env_raw", "env0");
|
||||
|
||||
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
|
||||
armlinux_set_architecture(MACH_TYPE_AT91SAM9261EK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(at91sam9261ek_devices_init);
|
||||
|
||||
static int at91sam9261ek_console_init(void)
|
||||
{
|
||||
at91_register_uart(0, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
console_initcall(at91sam9261ek_console_init);
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
CONFIG_ARCH_AT91SAM9261=y
|
||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||
CONFIG_PROMPT="9261-EK:"
|
||||
CONFIG_LONGHELP=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_HUSH_FANCY_PROMPT=y
|
||||
CONFIG_CMDLINE_EDITING=y
|
||||
CONFIG_AUTO_COMPLETE=y
|
||||
CONFIG_MENU=y
|
||||
CONFIG_PARTITION=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9261ek/env"
|
||||
CONFIG_CMD_EDIT=y
|
||||
CONFIG_CMD_SLEEP=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
CONFIG_CMD_LOADENV=y
|
||||
CONFIG_CMD_EXPORT=y
|
||||
CONFIG_CMD_PRINTENV=y
|
||||
CONFIG_CMD_READLINE=y
|
||||
CONFIG_CMD_MENU=y
|
||||
CONFIG_CMD_MENU_MANAGEMENT=y
|
||||
CONFIG_CMD_PASSWD=y
|
||||
CONFIG_CMD_ECHO_E=y
|
||||
CONFIG_CMD_LOADB=y
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_MTEST=y
|
||||
CONFIG_CMD_FLASH=y
|
||||
CONFIG_CMD_BOOTM_ZLIB=y
|
||||
CONFIG_CMD_BOOTM_BZLIB=y
|
||||
CONFIG_CMD_BOOTM_SHOW_TYPE=y
|
||||
CONFIG_CMD_RESET=y
|
||||
CONFIG_CMD_GO=y
|
||||
CONFIG_CMD_TIMEOUT=y
|
||||
CONFIG_CMD_PARTITION=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_UNLZO=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_NET_DHCP=y
|
||||
CONFIG_NET_NFS=y
|
||||
CONFIG_NET_PING=y
|
||||
CONFIG_NET_TFTP=y
|
||||
CONFIG_NET_TFTP_PUSH=y
|
||||
CONFIG_NET_RESOLV=y
|
||||
CONFIG_DRIVER_NET_DM9000=y
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_ATMEL=y
|
||||
CONFIG_UBI=y
|
||||
|
|
@ -6,6 +6,7 @@ config ARCH_TEXT_BASE
|
|||
|
||||
config BOARDINFO
|
||||
default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260EK
|
||||
default "Atmel at91sam9261-ek" if MACH_AT91SAM9261EK
|
||||
default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK
|
||||
default "Atmel at91sam9g20-ek" if MACH_AT91SAM9G20EK
|
||||
default "Bucyrus MMC-CPU" if MACH_MMCCPU
|
||||
|
|
@ -24,6 +25,10 @@ config ARCH_AT91SAM9260
|
|||
select CPU_ARM926T
|
||||
select HAS_MACB
|
||||
|
||||
config ARCH_AT91SAM9261
|
||||
bool "AT91SAM9261"
|
||||
select CPU_ARM926T
|
||||
|
||||
config ARCH_AT91SAM9263
|
||||
bool "AT91SAM9263"
|
||||
select CPU_ARM926T
|
||||
|
|
@ -56,6 +61,25 @@ endif
|
|||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
if ARCH_AT91SAM9261
|
||||
|
||||
choice
|
||||
prompt "AT91SAM9261 Board Type"
|
||||
|
||||
config MACH_AT91SAM9261EK
|
||||
bool "Atmel AT91SAM9261-EK Evaluation Kit"
|
||||
select HAS_DM9000
|
||||
select HAVE_NAND_ATMEL_BUSWIDTH_16
|
||||
help
|
||||
Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
|
||||
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
if ARCH_AT91SAM9G20
|
||||
|
||||
choice
|
||||
|
|
|
|||
|
|
@ -4,5 +4,6 @@ obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
|
|||
|
||||
# CPU-specific support
|
||||
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,230 @@
|
|||
#include <common.h>
|
||||
#include <gpio.h>
|
||||
#include <init.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
|
||||
#include "generic.h"
|
||||
#include "clock.h"
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Clocks
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* The peripheral clocks.
|
||||
*/
|
||||
static struct clk pioA_clk = {
|
||||
.name = "pioA_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_PIOA,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioB_clk = {
|
||||
.name = "pioB_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_PIOB,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk pioC_clk = {
|
||||
.name = "pioC_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_PIOC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart0_clk = {
|
||||
.name = "usart0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_US0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart1_clk = {
|
||||
.name = "usart1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_US1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk usart2_clk = {
|
||||
.name = "usart2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_US2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk mmc_clk = {
|
||||
.name = "mci_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_MCI,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk udc_clk = {
|
||||
.name = "udc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_UDP,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk twi_clk = {
|
||||
.name = "twi_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_TWI,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi0_clk = {
|
||||
.name = "spi0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_SPI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk spi1_clk = {
|
||||
.name = "spi1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_SPI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc0_clk = {
|
||||
.name = "ssc0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_SSC0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc1_clk = {
|
||||
.name = "ssc1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_SSC1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ssc2_clk = {
|
||||
.name = "ssc2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_SSC2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tc0_clk = {
|
||||
.name = "tc0_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_TC0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tc1_clk = {
|
||||
.name = "tc1_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_TC1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk tc2_clk = {
|
||||
.name = "tc2_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_TC2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk ohci_clk = {
|
||||
.name = "ohci_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_UHP,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
static struct clk lcdc_clk = {
|
||||
.name = "lcdc_clk",
|
||||
.pmc_mask = 1 << AT91SAM9261_ID_LCDC,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
};
|
||||
|
||||
static struct clk *periph_clocks[] = {
|
||||
&pioA_clk,
|
||||
&pioB_clk,
|
||||
&pioC_clk,
|
||||
&usart0_clk,
|
||||
&usart1_clk,
|
||||
&usart2_clk,
|
||||
&mmc_clk,
|
||||
&udc_clk,
|
||||
&twi_clk,
|
||||
&spi0_clk,
|
||||
&spi1_clk,
|
||||
&ssc0_clk,
|
||||
&ssc1_clk,
|
||||
&ssc2_clk,
|
||||
&tc0_clk,
|
||||
&tc1_clk,
|
||||
&tc2_clk,
|
||||
&ohci_clk,
|
||||
&lcdc_clk,
|
||||
// irq0 .. irq2
|
||||
};
|
||||
|
||||
/*
|
||||
* The four programmable clocks.
|
||||
* You must configure pin multiplexing to bring these signals out.
|
||||
*/
|
||||
static struct clk pck0 = {
|
||||
.name = "pck0",
|
||||
.pmc_mask = AT91_PMC_PCK0,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 0,
|
||||
};
|
||||
static struct clk pck1 = {
|
||||
.name = "pck1",
|
||||
.pmc_mask = AT91_PMC_PCK1,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 1,
|
||||
};
|
||||
static struct clk pck2 = {
|
||||
.name = "pck2",
|
||||
.pmc_mask = AT91_PMC_PCK2,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 2,
|
||||
};
|
||||
static struct clk pck3 = {
|
||||
.name = "pck3",
|
||||
.pmc_mask = AT91_PMC_PCK3,
|
||||
.type = CLK_TYPE_PROGRAMMABLE,
|
||||
.id = 3,
|
||||
};
|
||||
|
||||
/* HClocks */
|
||||
static struct clk hck0 = {
|
||||
.name = "hck0",
|
||||
.pmc_mask = AT91_PMC_HCK0,
|
||||
.type = CLK_TYPE_SYSTEM,
|
||||
.id = 0,
|
||||
};
|
||||
static struct clk hck1 = {
|
||||
.name = "hck1",
|
||||
.pmc_mask = AT91_PMC_HCK1,
|
||||
.type = CLK_TYPE_SYSTEM,
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
static void at91sam9261_register_clocks(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||
clk_register(periph_clocks[i]);
|
||||
|
||||
clk_register(&pck0);
|
||||
clk_register(&pck1);
|
||||
clk_register(&pck2);
|
||||
clk_register(&pck3);
|
||||
|
||||
clk_register(&hck0);
|
||||
clk_register(&hck1);
|
||||
}
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* GPIO
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static struct at91_gpio_bank at91sam9261_gpio[] = {
|
||||
{
|
||||
.id = AT91SAM9261_ID_PIOA,
|
||||
.offset = AT91_PIOA,
|
||||
.clock = &pioA_clk,
|
||||
}, {
|
||||
.id = AT91SAM9261_ID_PIOB,
|
||||
.offset = AT91_PIOB,
|
||||
.clock = &pioB_clk,
|
||||
}, {
|
||||
.id = AT91SAM9261_ID_PIOC,
|
||||
.offset = AT91_PIOC,
|
||||
.clock = &pioC_clk,
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
static int at91sam9261_initialize(void)
|
||||
{
|
||||
/* Init clock subsystem */
|
||||
at91_clock_init(AT91_MAIN_CLOCK);
|
||||
|
||||
/* Register the processor-specific clocks */
|
||||
at91sam9261_register_clocks();
|
||||
|
||||
/* Register GPIO subsystem */
|
||||
at91_gpio_init(at91sam9261_gpio, 3);
|
||||
return 0;
|
||||
}
|
||||
|
||||
core_initcall(at91sam9261_initialize);
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/at91sam9261_devices.c
|
||||
*
|
||||
* Copyright (C) 2006 Atmel
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/armlinux.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/at91sam9261_matrix.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/io.h>
|
||||
|
||||
#include "generic.h"
|
||||
|
||||
static struct memory_platform_data ram_pdata = {
|
||||
.name = "ram0",
|
||||
.flags = DEVFS_RDWR,
|
||||
};
|
||||
|
||||
static struct device_d sdram_dev = {
|
||||
.id = 0,
|
||||
.name = "mem",
|
||||
.map_base = AT91_CHIPSELECT_1,
|
||||
.platform_data = &ram_pdata,
|
||||
};
|
||||
|
||||
void at91_add_device_sdram(u32 size)
|
||||
{
|
||||
sdram_dev.size = size;
|
||||
register_device(&sdram_dev);
|
||||
armlinux_add_dram(&sdram_dev);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_NAND_ATMEL)
|
||||
static struct device_d nand_dev = {
|
||||
.id = 0,
|
||||
.name = "atmel_nand",
|
||||
.map_base = AT91_CHIPSELECT_3,
|
||||
.size = 0x10,
|
||||
};
|
||||
|
||||
void at91_add_device_nand(struct atmel_nand_data *data)
|
||||
{
|
||||
unsigned long csa;
|
||||
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
||||
|
||||
/* enable pin */
|
||||
if (data->enable_pin)
|
||||
at91_set_gpio_output(data->enable_pin, 1);
|
||||
|
||||
/* ready/busy pin */
|
||||
if (data->rdy_pin)
|
||||
at91_set_gpio_input(data->rdy_pin, 1);
|
||||
|
||||
/* card detect pin */
|
||||
if (data->det_pin)
|
||||
at91_set_gpio_input(data->det_pin, 1);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
|
||||
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
|
||||
|
||||
nand_dev.platform_data = data;
|
||||
register_device(&nand_dev);
|
||||
}
|
||||
#else
|
||||
void at91_add_device_nand(struct atmel_nand_data *data) {}
|
||||
#endif
|
||||
|
||||
static struct device_d dbgu_serial_device = {
|
||||
.id = 0,
|
||||
.name = "atmel_serial",
|
||||
.map_base = (AT91_BASE_SYS + AT91_DBGU),
|
||||
.size = 4096,
|
||||
};
|
||||
|
||||
static inline void configure_dbgu_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
|
||||
at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
|
||||
}
|
||||
|
||||
static struct device_d uart0_serial_device = {
|
||||
.id = 1,
|
||||
.name = "atmel_serial",
|
||||
.map_base = AT91SAM9261_BASE_US0,
|
||||
.size = 4096,
|
||||
};
|
||||
|
||||
static inline void configure_usart0_pins(unsigned pins)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
|
||||
|
||||
if (pins & ATMEL_UART_RTS)
|
||||
at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
|
||||
if (pins & ATMEL_UART_CTS)
|
||||
at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
|
||||
}
|
||||
|
||||
static struct device_d uart1_serial_device = {
|
||||
.id = 2,
|
||||
.name = "atmel_serial",
|
||||
.map_base = AT91SAM9261_BASE_US1,
|
||||
.size = 4096,
|
||||
};
|
||||
|
||||
static inline void configure_usart1_pins(unsigned pins)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
|
||||
|
||||
if (pins & ATMEL_UART_RTS)
|
||||
at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
|
||||
if (pins & ATMEL_UART_CTS)
|
||||
at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
|
||||
}
|
||||
|
||||
static struct device_d uart2_serial_device = {
|
||||
.id = 3,
|
||||
.name = "atmel_serial",
|
||||
.map_base = AT91SAM9261_BASE_US2,
|
||||
.size = 4096,
|
||||
};
|
||||
|
||||
static inline void configure_usart2_pins(unsigned pins)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
|
||||
|
||||
if (pins & ATMEL_UART_RTS)
|
||||
at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
|
||||
if (pins & ATMEL_UART_CTS)
|
||||
at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
|
||||
}
|
||||
|
||||
void at91_register_uart(unsigned id, unsigned pins)
|
||||
{
|
||||
switch (id) {
|
||||
case 0: /* DBGU */
|
||||
configure_dbgu_pins();
|
||||
at91_clock_associate("mck", &dbgu_serial_device, "usart");
|
||||
register_device(&dbgu_serial_device);
|
||||
break;
|
||||
case AT91SAM9261_ID_US0:
|
||||
configure_usart0_pins(pins);
|
||||
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
|
||||
register_device(&uart0_serial_device);
|
||||
break;
|
||||
case AT91SAM9261_ID_US1:
|
||||
configure_usart1_pins(pins);
|
||||
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
|
||||
register_device(&uart1_serial_device);
|
||||
break;
|
||||
case AT91SAM9261_ID_US2:
|
||||
configure_usart2_pins(pins);
|
||||
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
|
||||
register_device(&uart2_serial_device);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
|
||||
*
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9261 datasheet revision E. (Preliminary)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9261_H
|
||||
#define AT91SAM9261_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91SAM9261_ID_US0 6 /* USART 0 */
|
||||
#define AT91SAM9261_ID_US1 7 /* USART 1 */
|
||||
#define AT91SAM9261_ID_US2 8 /* USART 2 */
|
||||
#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
|
||||
#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
|
||||
#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
|
||||
#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
|
||||
#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
|
||||
#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
|
||||
#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
|
||||
#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
|
||||
#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
|
||||
#define AT91SAM9261_ID_UHP 20 /* USB Host port */
|
||||
#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
|
||||
#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
|
||||
#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9261_BASE_TCB0 0xfffa0000
|
||||
#define AT91SAM9261_BASE_TC0 0xfffa0000
|
||||
#define AT91SAM9261_BASE_TC1 0xfffa0040
|
||||
#define AT91SAM9261_BASE_TC2 0xfffa0080
|
||||
#define AT91SAM9261_BASE_UDP 0xfffa4000
|
||||
#define AT91SAM9261_BASE_MCI 0xfffa8000
|
||||
#define AT91SAM9261_BASE_TWI 0xfffac000
|
||||
#define AT91SAM9261_BASE_US0 0xfffb0000
|
||||
#define AT91SAM9261_BASE_US1 0xfffb4000
|
||||
#define AT91SAM9261_BASE_US2 0xfffb8000
|
||||
#define AT91SAM9261_BASE_SSC0 0xfffbc000
|
||||
#define AT91SAM9261_BASE_SSC1 0xfffc0000
|
||||
#define AT91SAM9261_BASE_SSC2 0xfffc4000
|
||||
#define AT91SAM9261_BASE_SPI0 0xfffc8000
|
||||
#define AT91SAM9261_BASE_SPI1 0xfffcc000
|
||||
#define AT91_BASE_SYS 0xffffea00
|
||||
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91_USART0 AT91SAM9261_BASE_US0
|
||||
#define AT91_USART1 AT91SAM9261_BASE_US1
|
||||
#define AT91_USART2 AT91SAM9261_BASE_US2
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
|
||||
|
||||
#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
|
||||
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
|
||||
|
||||
/*
|
||||
* Cpu Name
|
||||
*/
|
||||
#define AT91_CPU_NAME "AT91SAM9261"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9261_MATRIX_H
|
||||
#define AT91SAM9261_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
|
||||
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_ITCM_64 (7 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
#define AT91_MATRIX_DTCM_64 (7 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
|
||||
#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
|
||||
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue