dts: update to v4.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
bfe946c959
commit
d9a1538546
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@ -61,7 +61,9 @@ Required Properties:
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- #address-cells: must be 1
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- #size-cells: must be 1
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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interrupt.
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- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
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- #interrupt-cells : must be set to 2.
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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@ -70,11 +72,23 @@ L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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On-Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ocram-ecc"
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- reg : Address and size for ECC block registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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Ethernet FIFO ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-eth-mac-ecc"
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- reg : Address and size for ECC block registers.
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- altr,ecc-parent : phandle to parent Ethernet node.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt, in this order.
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Example:
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@ -85,15 +99,37 @@ Example:
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#size-cells = <1>;
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interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ranges;
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l2-ecc@ffd06010 {
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compatible = "altr,socfpga-a10-l2-ecc";
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reg = <0xffd06010 0x4>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
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<32 IRQ_TYPE_LEVEL_HIGH>;
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};
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ocram-ecc@ff8c3000 {
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compatible = "altr,socfpga-a10-ocram-ecc";
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reg = <0xff8c3000 0x90>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
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<33 IRQ_TYPE_LEVEL_HIGH> ;
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};
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emac0-rx-ecc@ff8c0800 {
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compatible = "altr,socfpga-eth-mac-ecc";
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reg = <0xff8c0800 0x400>;
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altr,ecc-parent = <&gmac0>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
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<36 IRQ_TYPE_LEVEL_HIGH>;
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};
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emac0-tx-ecc@ff8c0c00 {
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compatible = "altr,socfpga-eth-mac-ecc";
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reg = <0xff8c0c00 0x400>;
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altr,ecc-parent = <&gmac0>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
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<37 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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@ -87,10 +87,33 @@ Required properties:
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implementation for the IDs to use. For Juno
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R0 and Juno R1 refer to [3].
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Power domain bindings for the power domains based on SCPI Message Protocol
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------------------------------------------------------------
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This binding uses the generic power domain binding[4].
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PM domain providers
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===================
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Required properties:
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- #power-domain-cells : Should be 1. Contains the device or the power
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domain ID value used by SCPI commands.
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- num-domains: Total number of power domains provided by SCPI. This is
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needed as the SCPI message protocol lacks a mechanism to
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query this information at runtime.
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PM domain consumers
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===================
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Required properties:
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- power-domains : A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle.
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[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/thermal/thermal.txt
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[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
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[4] Documentation/devicetree/bindings/power/power_domain.txt
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Example:
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@ -144,6 +167,12 @@ scpi_protocol: scpi@2e000000 {
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compatible = "arm,scpi-sensors";
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#thermal-sensor-cells = <1>;
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};
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scpi_devpd: scpi-power-domains {
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compatible = "arm,scpi-power-domains";
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num-domains = <2>;
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#power-domain-cells = <1>;
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};
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};
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cpu@0 {
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@ -156,6 +185,7 @@ hdlcd@7ff60000 {
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...
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reg = <0 0x7ff60000 0 0x1000>;
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clocks = <&scpi_clk 4>;
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power-domains = <&scpi_devpd 1>;
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};
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thermal-zones {
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@ -186,3 +216,7 @@ The thermal-sensors property in the soc_thermal node uses the
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temperature sensor provided by SCP firmware to setup a thermal
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zone. The ID "3" is the sensor identifier for the temperature sensor
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as used by the firmware.
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The num-domains property in scpi-power-domains domain specifies that
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SCPI provides 2 power domains. The hdlcd node uses the power domain with
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domain ID 1.
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@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs:
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BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
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The enable method is specified by defining the following required
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properties in the "cpus" device tree node:
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properties in the "cpu" device tree node:
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- enable-method = "brcm,bcm11351-cpu-method";
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- secondary-boot-reg = <...>;
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@ -19,8 +19,6 @@ Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm11351-cpu-method";
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secondary-boot-reg = <0x3500417c>;
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cpu0: cpu@0 {
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device_type = "cpu";
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@ -32,5 +30,7 @@ Example:
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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enable-method = "brcm,bcm11351-cpu-method";
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secondary-boot-reg = <0x3500417c>;
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};
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};
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@ -0,0 +1,36 @@
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Broadcom Kona Family CPU Enable Method
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--------------------------------------
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This binding defines the enable method used for starting secondary
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CPUs in the following Broadcom SoCs:
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BCM23550
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The enable method is specified by defining the following required
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properties in the "cpu" device tree node:
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- enable-method = "brcm,bcm23550";
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- secondary-boot-reg = <...>;
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The secondary-boot-reg property is a u32 value that specifies the
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physical address of the register used to request the ROM holding pen
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code release a secondary CPU. The value written to the register is
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formed by encoding the target CPU id into the low bits of the
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physical start address it should jump to.
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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enable-method = "brcm,bcm23550";
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secondary-boot-reg = <0x3500417c>;
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};
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};
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@ -0,0 +1,15 @@
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Broadcom BCM23550 device tree bindings
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--------------------------------------
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This document describes the device tree bindings for boards with the BCM23550
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SoC.
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Required root node property:
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- compatible: brcm,bcm23550
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Example:
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/ {
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model = "BCM23550 SoC";
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compatible = "brcm,bcm23550";
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[...]
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}
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@ -30,6 +30,10 @@ Raspberry Pi 2 Model B
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Required root node properties:
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compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
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Raspberry Pi 3 Model B
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Required root node properties:
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compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
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Raspberry Pi Compute Module
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Required root node properties:
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compatible = "raspberrypi,compute-module", "brcm,bcm2835";
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@ -12,14 +12,33 @@ its hardware characteristcs.
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* compatible: These have to be supplemented with "arm,primecell" as
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drivers are using the AMBA bus interface. Possible values include:
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- "arm,coresight-etb10", "arm,primecell";
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- "arm,coresight-tpiu", "arm,primecell";
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- "arm,coresight-tmc", "arm,primecell";
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- "arm,coresight-funnel", "arm,primecell";
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- "arm,coresight-etm3x", "arm,primecell";
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- "arm,coresight-etm4x", "arm,primecell";
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- "qcom,coresight-replicator1x", "arm,primecell";
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- "arm,coresight-stm", "arm,primecell"; [1]
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- Embedded Trace Buffer (version 1.0):
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"arm,coresight-etb10", "arm,primecell";
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- Trace Port Interface Unit:
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"arm,coresight-tpiu", "arm,primecell";
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- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
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Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
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configuration. The configuration mode (ETB, ETF, ETR) is
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discovered at boot time when the device is probed.
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"arm,coresight-tmc", "arm,primecell";
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- Trace Funnel:
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"arm,coresight-funnel", "arm,primecell";
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- Embedded Trace Macrocell (version 3.x) and
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Program Flow Trace Macrocell:
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"arm,coresight-etm3x", "arm,primecell";
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- Embedded Trace Macrocell (version 4.x):
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"arm,coresight-etm4x", "arm,primecell";
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- Qualcomm Configurable Replicator (version 1.x):
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"qcom,coresight-replicator1x", "arm,primecell";
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- System Trace Macrocell:
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"arm,coresight-stm", "arm,primecell"; [1]
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* reg: physical base address and length of the register
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set(s) of the component.
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@ -193,6 +193,8 @@ nodes to be present and contain the properties described below.
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"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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"arm,realview-smp"
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"brcm,bcm11351-cpu-method"
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"brcm,bcm23550"
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"brcm,bcm-nsp-smp"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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@ -204,6 +206,7 @@ nodes to be present and contain the properties described below.
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v2"
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"renesas,apmu"
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"rockchip,rk3036-smp"
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"rockchip,rk3066-smp"
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"ste,dbx500-smp"
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@ -0,0 +1,14 @@
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* Hisilicon Hi3519 System Controller Block
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This bindings use the following binding:
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Documentation/devicetree/bindings/mfd/syscon.txt
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Required properties:
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- compatible: "hisilicon,hi3519-sysctrl".
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- reg: the register region of this block
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Examples:
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sysctrl: system-controller@12010000 {
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compatible = "hisilicon,hi3519-sysctrl", "syscon";
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reg = <0x12010000 0x1000>;
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};
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@ -86,10 +86,10 @@ Optional properties:
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firmware)
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- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
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disable), <1> (forcibly enable), property absent (OS specific behavior,
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preferrably retain firmware settings)
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preferably retain firmware settings)
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- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
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<1> (forcibly enable), property absent (OS specific behavior,
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preferrably retain firmware settings)
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preferably retain firmware settings)
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Example:
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@ -10,6 +10,7 @@ compatible: Must contain one of
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"mediatek,mt6580"
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"mediatek,mt6589"
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"mediatek,mt6592"
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"mediatek,mt6755"
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"mediatek,mt6795"
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"mediatek,mt7623"
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"mediatek,mt8127"
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@ -31,6 +32,9 @@ Supported boards:
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- Evaluation board for MT6592:
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Required root node properties:
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- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
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- Evaluation phone for MT6755(Helio P10):
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Required root node properties:
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- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
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- Evaluation board for MT6795(Helio X10):
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Required root node properties:
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- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
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@ -1,5 +1,9 @@
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Olimex i.MX Platforms Device Tree Bindings
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------------------------------------------
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Olimex Device Tree Bindings
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---------------------------
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SAM9-L9260 Board
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Required root node properties:
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- compatible = "olimex,sam9-l9260", "atmel,at91sam9260";
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i.MX23 Olinuxino Low Cost Board
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Required root node properties:
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|
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@ -39,7 +39,9 @@ Optional properties:
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When using a PPI, specifies a list of phandles to CPU
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nodes corresponding to the set of CPUs which have
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a PMU of this type signalling the PPI listed in the
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interrupts property.
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interrupts property, unless this is already specified
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by the PPI interrupt specifier itself (in which case
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the interrupt-affinity property shouldn't be present).
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This property should be present when there is more than
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a single SPI.
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|
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@ -107,6 +107,9 @@ Rockchip platforms device tree bindings
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Required root node properties:
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- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
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- Rockchip RK3229 Evaluation board:
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- compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
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- Rockchip RK3399 evb:
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Required root node properties:
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- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
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|
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|
@ -47,6 +47,7 @@ Required root node properties:
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- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
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- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
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- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
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- "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
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- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
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- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
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Odroid XU3 Lite board.
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|
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@ -29,6 +29,8 @@ SoCs:
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compatible = "renesas,r8a7794"
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- R-Car H3 (R8A77950)
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compatible = "renesas,r8a7795"
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- R-Car M3-W (R8A77960)
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compatible = "renesas,r8a7796"
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Boards:
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|
@ -39,6 +41,8 @@ Boards:
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compatible = "renesas,ape6evm", "renesas,r8a73a4"
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- Atmark Techno Armadillo-800 EVA
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compatible = "renesas,armadillo800eva"
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- Blanche (RTP0RC7792SEB00010S)
|
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compatible = "renesas,blanche", "renesas,r8a7792"
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- BOCK-W
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compatible = "renesas,bockw", "renesas,r8a7778"
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- Genmai (RTK772100BC00000BR)
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|
@ -61,5 +65,7 @@ Boards:
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compatible = "renesas,porter", "renesas,r8a7791"
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- Salvator-X (RTP0RC7795SIPB0010S)
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compatible = "renesas,salvator-x", "renesas,r8a7795";
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- Salvator-X
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compatible = "renesas,salvator-x", "renesas,r8a7796";
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- SILK (RTP0RC7794LCB00011S)
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compatible = "renesas,silk", "renesas,r8a7794"
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|
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@ -32,7 +32,11 @@ board-specific compatible values:
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nvidia,whistler
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toradex,apalis_t30
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toradex,apalis_t30-eval
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toradex,apalis-tk1
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toradex,apalis-tk1-eval
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toradex,colibri_t20-512
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toradex,colibri_t30
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toradex,colibri_t30-eval-v3
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toradex,iris
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Trusted Foundations
|
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|
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|
@ -11,10 +11,32 @@ the following properties:
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|||
memory where the grant table should be mapped to, using an
|
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HYPERVISOR_memory_op hypercall. The memory region is large enough to map
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the whole grant table (it is larger or equal to gnttab_max_grant_frames()).
|
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This property is unnecessary when booting Dom0 using ACPI.
|
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- interrupts: the interrupt used by Xen to inject event notifications.
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A GIC node is also required.
|
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This property is unnecessary when booting Dom0 using ACPI.
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|
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To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node
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under /hypervisor with following parameters:
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________________________________________________________________________________
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Name | Size | Description
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================================================================================
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xen,uefi-system-table | 64-bit | Guest physical address of the UEFI System
|
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| | Table.
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--------------------------------------------------------------------------------
|
||||
xen,uefi-mmap-start | 64-bit | Guest physical address of the UEFI memory
|
||||
| | map.
|
||||
--------------------------------------------------------------------------------
|
||||
xen,uefi-mmap-size | 32-bit | Size in bytes of the UEFI memory map
|
||||
| | pointed to in previous entry.
|
||||
--------------------------------------------------------------------------------
|
||||
xen,uefi-mmap-desc-size | 32-bit | Size in bytes of each entry in the UEFI
|
||||
| | memory map.
|
||||
--------------------------------------------------------------------------------
|
||||
xen,uefi-mmap-desc-ver | 32-bit | Version of the mmap descriptor format.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Example (assuming #address-cells = <2> and #size-cells = <2>):
|
||||
|
||||
|
@ -22,4 +44,17 @@ hypervisor {
|
|||
compatible = "xen,xen-4.3", "xen,xen";
|
||||
reg = <0 0xb0000000 0 0x20000>;
|
||||
interrupts = <1 15 0xf08>;
|
||||
uefi {
|
||||
xen,uefi-system-table = <0xXXXXXXXX>;
|
||||
xen,uefi-mmap-start = <0xXXXXXXXX>;
|
||||
xen,uefi-mmap-size = <0xXXXXXXXX>;
|
||||
xen,uefi-mmap-desc-size = <0xXXXXXXXX>;
|
||||
xen,uefi-mmap-desc-ver = <0xXXXXXXXX>;
|
||||
};
|
||||
};
|
||||
|
||||
The format and meaning of the "xen,uefi-*" parameters are similar to those in
|
||||
Documentation/arm/uefi.txt, which are provided by the regular UEFI stub. However
|
||||
they differ because they are provided by the Xen hypervisor, together with a set
|
||||
of UEFI runtime services implemented via hypercalls, see
|
||||
http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html.
|
||||
|
|
|
@ -10,6 +10,7 @@ PHYs.
|
|||
Required properties:
|
||||
- compatible : compatible string, one of:
|
||||
- "allwinner,sun4i-a10-ahci"
|
||||
- "brcm,iproc-ahci"
|
||||
- "hisilicon,hisi-ahci"
|
||||
- "cavium,octeon-7130-ahci"
|
||||
- "ibm,476gtr-ahci"
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
* Broadcom SATA3 AHCI Controller for STB
|
||||
* Broadcom SATA3 AHCI Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
@ -7,6 +7,7 @@ Required properties:
|
|||
- compatible : should be one or more of
|
||||
"brcm,bcm7425-ahci"
|
||||
"brcm,bcm7445-ahci"
|
||||
"brcm,bcm-nsp-ahci"
|
||||
"brcm,sata3-ahci"
|
||||
- reg : register mappings for AHCI and SATA_TOP_CTRL
|
||||
- reg-names : "ahci" and "top-ctrl"
|
|
@ -0,0 +1,45 @@
|
|||
NVIDIA Tegra ACONNECT Bus
|
||||
|
||||
The Tegra ACONNECT bus is an AXI switch which is used to connnect various
|
||||
components inside the Audio Processing Engine (APE). All CPU accesses to
|
||||
the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "nvidia,tegra210-aconnect".
|
||||
- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
|
||||
and APE interface clock (TEGRA210_CLK_APB2APE).
|
||||
- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
|
||||
'clocks' entries.
|
||||
- power-domains: Must contain a phandle that points to the audio powergate
|
||||
(namely 'aud') for Tegra210.
|
||||
- #address-cells: The number of cells used to represent physical base addresses
|
||||
in the aconnect address space. Should be 1.
|
||||
- #size-cells: The number of cells used to represent the size of an address
|
||||
range in the aconnect address space. Should be 1.
|
||||
- ranges: Mapping of the aconnect address space to the CPU address space.
|
||||
|
||||
All devices accessed via the ACONNNECT are described by child-nodes.
|
||||
|
||||
Example:
|
||||
|
||||
aconnect@702c0000 {
|
||||
compatible = "nvidia,tegra210-aconnect";
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
clock-names = "ape", "apb2ape";
|
||||
power-domains = <&pd_audio>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
child1 {
|
||||
...
|
||||
};
|
||||
|
||||
child2 {
|
||||
...
|
||||
};
|
||||
};
|
|
@ -0,0 +1,36 @@
|
|||
* Amlogic GXBB Clock and Reset Unit
|
||||
|
||||
The Amlogic GXBB clock controller generates and supplies clock to various
|
||||
controllers within the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "amlogic,gxbb-clkc"
|
||||
- reg: physical base address of the clock controller and length of memory
|
||||
mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clkc: clock-controller@c883c000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "amlogic,gxbb-clkc";
|
||||
reg = <0x0 0xc883c000 0x0 0x3db>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart_AO: serial@c81004c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0xc81004c0 0x14>;
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc CLKID_CLK81>;
|
||||
status = "disabled";
|
||||
};
|
|
@ -1,7 +1,7 @@
|
|||
* Clock bindings for the Cirrus Logic CLPS711X CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall contain "cirrus,clps711x-clk".
|
||||
- compatible : Shall contain "cirrus,ep7209-clk".
|
||||
- reg : Address of the internal register set.
|
||||
- startup-frequency: Factory set CPU startup frequency in HZ.
|
||||
- #clock-cells : Should be <1>.
|
||||
|
@ -13,7 +13,7 @@ for the full list of CLPS711X clock IDs.
|
|||
Example:
|
||||
clks: clks@80000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
|
||||
compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
|
||||
reg = <0x80000000 0xc000>;
|
||||
startup-frequency = <73728000>;
|
||||
};
|
||||
|
|
|
@ -14,6 +14,10 @@ Required properties:
|
|||
Optional properties:
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Some clocks that require special treatments are also handled by that
|
||||
driver, with the compatibles:
|
||||
- allwinner,sun4i-a10-pll3-2x-clk
|
||||
|
||||
Example:
|
||||
clock {
|
||||
compatible = "fixed-factor-clock";
|
||||
|
|
|
@ -13,7 +13,8 @@ They provide the following functionalities:
|
|||
|
||||
Required Properties:
|
||||
- compatible: Must be one of:
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG/MSSR
|
||||
block
|
||||
|
@ -21,8 +22,8 @@ Required Properties:
|
|||
- clocks: References to external parent clocks, one entry for each entry in
|
||||
clock-names
|
||||
- clock-names: List of external parent clock names. Valid names are:
|
||||
- "extal" (r8a7795)
|
||||
- "extalr" (r8a7795)
|
||||
- "extal" (r8a7795, r8a7796)
|
||||
- "extalr" (r8a7795, r8a7796)
|
||||
|
||||
- #clock-cells: Must be 2
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
|
|
|
@ -17,6 +17,7 @@ Required Properties:
|
|||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
|
||||
- "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
|
||||
- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
|
||||
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
|
||||
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
|
||||
|
|
|
@ -10,6 +10,7 @@ Required Properties:
|
|||
- compatible: Must be one of
|
||||
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
|
||||
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
|
||||
- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
|
||||
- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
|
||||
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
|
||||
and "renesas,rcar-gen2-cpg-clocks" as a fallback.
|
||||
|
|
|
@ -0,0 +1,24 @@
|
|||
Allwinner Clock Control Unit Binding
|
||||
------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible: must contain one of the following compatible:
|
||||
- "allwinner,sun8i-h3-ccu"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
|
||||
- "hosc": the high frequency oscillator (usually at 24MHz)
|
||||
- "losc": the low frequency oscillator (usually at 32kHz)
|
||||
- clock-names: Must contain the clock names described just above
|
||||
- #clock-cells : must contain 1
|
||||
- #reset-cells : must contain 1
|
||||
|
||||
Example:
|
||||
ccu: clock@01c20000 {
|
||||
compatible = "allwinner,sun8i-h3-ccu";
|
||||
reg = <0x01c20000 0x400>;
|
||||
clocks = <&osc24M>, <&osc32k>;
|
||||
clock-names = "hosc", "losc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
|
@ -0,0 +1,65 @@
|
|||
ARM Mali-DP
|
||||
|
||||
The following bindings apply to a family of Display Processors sold as
|
||||
licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
|
||||
DP650 processors that offer multiple composition layers, support for
|
||||
rotation and scaling output.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of
|
||||
"arm,mali-dp500"
|
||||
"arm,mali-dp550"
|
||||
"arm,mali-dp650"
|
||||
depending on the particular implementation present in the hardware
|
||||
- reg: Physical base address and size of the block of registers used by
|
||||
the processor.
|
||||
- interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
|
||||
interrupt client nodes.
|
||||
- interrupt-names: name of the engine inside the processor that will
|
||||
use the corresponding interrupt. Should be one of "DE" or "SE".
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each entry
|
||||
in 'clock-names'
|
||||
- clock-names: A list of clock names. It should contain:
|
||||
- "pclk": for the APB interface clock
|
||||
- "aclk": for the AXI interface clock
|
||||
- "mclk": for the main processor clock
|
||||
- "pxlclk": for the pixel clock feeding the output PLL of the processor.
|
||||
- arm,malidp-output-port-lines: Array of u8 values describing the number
|
||||
of output lines per channel (R, G and B).
|
||||
|
||||
Required sub-nodes:
|
||||
- port: The Mali DP connection to an encoder input port. The connection
|
||||
is modelled using the OF graph bindings specified in
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
|
||||
Optional properties:
|
||||
- memory-region: phandle to a node describing memory (see
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
|
||||
to be used for the framebuffer; if not present, the framebuffer may
|
||||
be located anywhere in memory.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
dp0: malidp@6f200000 {
|
||||
compatible = "arm,mali-dp650";
|
||||
reg = <0 0x6f200000 0 0x20000>;
|
||||
memory-region = <&display_reserved>;
|
||||
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "DE", "SE";
|
||||
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
|
||||
clock-names = "pxlclk", "mclk", "aclk", "pclk";
|
||||
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
|
||||
port {
|
||||
dp0_output: endpoint {
|
||||
remote-endpoint = <&tda998x_2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
};
|
|
@ -1,13 +1,19 @@
|
|||
Analog Device ADV7511(W)/13 HDMI Encoders
|
||||
Analog Device ADV7511(W)/13/33 HDMI Encoders
|
||||
-----------------------------------------
|
||||
|
||||
The ADV7511, ADV7511W and ADV7513 are HDMI audio and video transmitters
|
||||
The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters
|
||||
compatible with HDMI 1.4 and DVI 1.0. They support color space conversion,
|
||||
S/PDIF, CEC and HDCP.
|
||||
S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while
|
||||
the others support RGB interface.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be one of "adi,adv7511", "adi,adv7511w" or "adi,adv7513"
|
||||
- compatible: Should be one of:
|
||||
"adi,adv7511"
|
||||
"adi,adv7511w"
|
||||
"adi,adv7513"
|
||||
"adi,adv7533"
|
||||
|
||||
- reg: I2C slave address
|
||||
|
||||
The ADV7511 supports a large number of input data formats that differ by their
|
||||
|
@ -32,6 +38,11 @@ The following input format properties are required except in "rgb 1x" and
|
|||
- adi,input-justification: The input bit justification ("left", "evenly",
|
||||
"right").
|
||||
|
||||
The following properties are required for ADV7533:
|
||||
|
||||
- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
|
||||
be one of 1, 2, 3 or 4.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupts: Specifier for the ADV7511 interrupt
|
||||
|
@ -42,13 +53,18 @@ Optional properties:
|
|||
- adi,embedded-sync: The input uses synchronization signals embedded in the
|
||||
data stream (similar to BT.656). Defaults to separate H/V synchronization
|
||||
signals.
|
||||
- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
|
||||
generator. The chip will rely on the sync signals in the DSI data lanes,
|
||||
rather than generate its own timings for HDMI output.
|
||||
|
||||
Required nodes:
|
||||
|
||||
The ADV7511 has two video ports. Their connections are modelled using the OF
|
||||
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
- Video port 0 for the RGB or YUV input
|
||||
- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the
|
||||
remote endpoint phandle should be a reference to a valid mipi_dsi_host device
|
||||
node.
|
||||
- Video port 1 for the HDMI output
|
||||
|
||||
|
||||
|
|
|
@ -5,6 +5,7 @@ Required properties for dp-controller:
|
|||
platform specific such as:
|
||||
* "samsung,exynos5-dp"
|
||||
* "rockchip,rk3288-dp"
|
||||
* "rockchip,rk3399-edp"
|
||||
-reg:
|
||||
physical base address of the controller and length
|
||||
of memory mapped region.
|
||||
|
|
|
@ -0,0 +1,35 @@
|
|||
sii902x HDMI bridge bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: "sil,sii9022"
|
||||
- reg: i2c address of the bridge
|
||||
|
||||
Optional properties:
|
||||
- interrupts-extended or interrupt-parent + interrupts: describe
|
||||
the interrupt line used to inform the host about hotplug events.
|
||||
- reset-gpios: OF device-tree gpio specification for RST_N pin.
|
||||
|
||||
Optional subnodes:
|
||||
- video input: this subnode can contain a video input port node
|
||||
to connect the bridge to a display controller output (See this
|
||||
documentation [1]).
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
hdmi-bridge@39 {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
reset-gpios = <&pioA 1 0>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dc_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,53 @@
|
|||
Toshiba TC358767 eDP bridge bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: "toshiba,tc358767"
|
||||
- reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
|
||||
- clock-names: should be "ref"
|
||||
- clocks: OF device-tree clock specification for refclk input. The reference
|
||||
clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
|
||||
|
||||
Optional properties:
|
||||
- shutdown-gpios: OF device-tree gpio specification for SD pin
|
||||
(active high shutdown input)
|
||||
- reset-gpios: OF device-tree gpio specification for RSTX pin
|
||||
(active low system reset)
|
||||
- ports: the ports node can contain video interface port nodes to connect
|
||||
to a DPI/DSI source and to an eDP/DP sink according to [1][2]:
|
||||
- port@0: DSI input port
|
||||
- port@1: DPI input port
|
||||
- port@2: eDP/DP output port
|
||||
|
||||
[1]: Documentation/devicetree/bindings/graph.txt
|
||||
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
edp-bridge@68 {
|
||||
compatible = "toshiba,tc358767";
|
||||
reg = <0x68>;
|
||||
shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
|
||||
clock-names = "ref";
|
||||
clocks = <&edp_refclk>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
bridge_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -1,7 +1,7 @@
|
|||
* Currus Logic CLPS711X Framebuffer
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall contain "cirrus,clps711x-fb".
|
||||
- compatible: Shall contain "cirrus,ep7209-fb".
|
||||
- reg : Physical base address and length of the controller's registers +
|
||||
location and size of the framebuffer memory.
|
||||
- clocks : phandle + clock specifier pair of the FB reference clock.
|
||||
|
@ -18,7 +18,7 @@ Optional properties:
|
|||
|
||||
Example:
|
||||
fb: fb@800002c0 {
|
||||
compatible = "cirrus,ep7312-fb", "cirrus,clps711x-fb";
|
||||
compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb";
|
||||
reg = <0x800002c0 0xd44>, <0x60000000 0xc000>;
|
||||
clocks = <&clks 2>;
|
||||
lcd-supply = <®5v0>;
|
||||
|
|
|
@ -8,6 +8,7 @@ Required properties:
|
|||
Optional properties:
|
||||
- label: a symbolic name for the connector
|
||||
- hpd-gpios: HPD GPIO number
|
||||
- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing
|
||||
|
||||
Required nodes:
|
||||
- Video port for HDMI input
|
||||
|
|
|
@ -12,7 +12,7 @@ Required properties:
|
|||
- clock-names: Should be "dcu" and "pix"
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- big-endian Boolean property, LS1021A DCU registers are big-endian.
|
||||
- fsl,panel: The phandle to panel node.
|
||||
- port Video port for the panel output
|
||||
|
||||
Optional properties:
|
||||
- fsl,tcon: The phandle to the timing controller node.
|
||||
|
@ -24,6 +24,11 @@ dcu: dcu@2ce0000 {
|
|||
clocks = <&platform_clk 0>, <&platform_clk 0>;
|
||||
clock-names = "dcu", "pix";
|
||||
big-endian;
|
||||
fsl,panel = <&panel>;
|
||||
fsl,tcon = <&tcon>;
|
||||
|
||||
port {
|
||||
dcu_out: endpoint {
|
||||
remote-endpoint = <&panel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -0,0 +1,148 @@
|
|||
Mediatek HDMI Encoder
|
||||
=====================
|
||||
|
||||
The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
|
||||
its parallel input.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-hdmi".
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
|
||||
- phys: phandle link to the HDMI PHY node.
|
||||
See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
|
||||
- phy-names: must contain "hdmi"
|
||||
- mediatek,syscon-hdmi: phandle link and register offset to the system
|
||||
configuration registers. For mt8173 this must be offset 0x900 into the
|
||||
MMSYS_CONFIG region: <&mmsys 0x900>.
|
||||
- ports: A node containing input and output port nodes with endpoint
|
||||
definitions as documented in Documentation/devicetree/bindings/graph.txt.
|
||||
- port@0: The input port in the ports node should be connected to a DPI output
|
||||
port.
|
||||
- port@1: The output port in the ports node should be connected to the input
|
||||
port of a connector node that contains a ddc-i2c-bus property, or to the
|
||||
input port of an attached bridge chip, such as a SlimPort transmitter.
|
||||
|
||||
HDMI CEC
|
||||
========
|
||||
|
||||
The HDMI CEC controller handles hotplug detection and CEC communication.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-cec"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clock
|
||||
|
||||
HDMI DDC
|
||||
========
|
||||
|
||||
The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
|
||||
The Mediatek's I2C controller is used to interface with I2C devices.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: device clock
|
||||
- clock-names: Should be "ddc-i2c".
|
||||
|
||||
HDMI PHY
|
||||
========
|
||||
|
||||
The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
|
||||
output and drives the HDMI pads.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-hdmi-phy"
|
||||
- reg: Physical base address and length of the module's registers
|
||||
- clocks: PLL reference clock
|
||||
- clock-names: must contain "pll_ref"
|
||||
- clock-output-names: must be "hdmitx_dig_cts" on mt8173
|
||||
- #phy-cells: must be <0>
|
||||
- #clock-cells: must be <0>
|
||||
|
||||
Optional properties:
|
||||
- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
|
||||
- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
|
||||
|
||||
Example:
|
||||
|
||||
cec: cec@10013000 {
|
||||
compatible = "mediatek,mt8173-cec";
|
||||
reg = <0 0x10013000 0 0xbc>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_CEC>;
|
||||
};
|
||||
|
||||
hdmi_phy: hdmi-phy@10209100 {
|
||||
compatible = "mediatek,mt8173-hdmi-phy";
|
||||
reg = <0 0x10209100 0 0x24>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
|
||||
clock-names = "pll_ref";
|
||||
clock-output-names = "hdmitx_dig_cts";
|
||||
mediatek,ibias = <0xa>;
|
||||
mediatek,ibias_up = <0x1c>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
hdmi_ddc0: i2c@11012000 {
|
||||
compatible = "mediatek,mt8173-hdmi-ddc";
|
||||
reg = <0 0x11012000 0 0x1c>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_I2C5>;
|
||||
clock-names = "ddc-i2c";
|
||||
};
|
||||
|
||||
hdmi0: hdmi@14025000 {
|
||||
compatible = "mediatek,mt8173-hdmi";
|
||||
reg = <0 0x14025000 0 0x400>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
|
||||
<&mmsys CLK_MM_HDMI_PLLCK>,
|
||||
<&mmsys CLK_MM_HDMI_AUDIO>,
|
||||
<&mmsys CLK_MM_HDMI_SPDIF>;
|
||||
clock-names = "pixel", "pll", "bclk", "spdif";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pin>;
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi";
|
||||
mediatek,syscon-hdmi = <&mmsys 0x900>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
|
||||
assigned-clock-parents = <&hdmi_phy>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
ddc-i2c-bus = <&hdmiddc0>;
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -11,8 +11,7 @@ Required properties:
|
|||
be 0 or 1, since we have 2 DSI controllers at most for now.
|
||||
- interrupts: The interrupt signal from the DSI block.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- clocks: Phandles to device clocks.
|
||||
- clock-names: the following clocks are required:
|
||||
* "mdp_core_clk"
|
||||
* "iface_clk"
|
||||
|
@ -23,16 +22,21 @@ Required properties:
|
|||
* "core_clk"
|
||||
For DSIv2, we need an additional clock:
|
||||
* "src_clk"
|
||||
- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.
|
||||
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
|
||||
by a DSI PHY block. See [1] for details on clock bindings.
|
||||
- vdd-supply: phandle to vdd regulator device node
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
- vdda-supply: phandle to vdda regulator device node
|
||||
- qcom,dsi-phy: phandle to DSI PHY device node
|
||||
- phys: phandle to DSI PHY device node
|
||||
- phy-names: the name of the corresponding PHY device
|
||||
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
|
||||
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
|
||||
an endpoint subnode as defined in [2] and [3].
|
||||
|
||||
Optional properties:
|
||||
- panel@0: Node of panel connected to this DSI controller.
|
||||
See files in Documentation/devicetree/bindings/display/panel/ for each supported
|
||||
panel.
|
||||
See files in [4] for each supported panel.
|
||||
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
|
||||
driving a panel which needs 2 DSI links.
|
||||
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
|
||||
|
@ -44,34 +48,38 @@ Optional properties:
|
|||
- pinctrl-names: the pin control state names; should contain "default"
|
||||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-n: the "sleep" pinctrl state
|
||||
- port: DSI controller output port, containing one endpoint subnode.
|
||||
- ports: contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
DSI Endpoint properties:
|
||||
- remote-endpoint: set to phandle of the connected panel's endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for device graph info.
|
||||
- qcom,data-lane-map: this describes how the logical DSI lanes are mapped
|
||||
to the physical lanes on the given platform. The value contained in
|
||||
index n describes what logical data lane is mapped to the physical data
|
||||
lane n (DATAn, where n lies between 0 and 3).
|
||||
- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
|
||||
input endpoint. For port@1, set to the MDP interface output. See [2] for
|
||||
device graph info.
|
||||
|
||||
- data-lanes: this describes how the physical DSI data lanes are mapped
|
||||
to the logical lanes on the given platform. The value contained in
|
||||
index n describes what physical lane is mapped to the logical lane n
|
||||
(DATAn, where n lies between 0 and 3). The clock lane position is fixed
|
||||
and can't be changed. Hence, they aren't a part of the DT bindings. See
|
||||
[3] for more info on the data-lanes property.
|
||||
|
||||
For example:
|
||||
|
||||
qcom,data-lane-map = <3 0 1 2>;
|
||||
data-lanes = <3 0 1 2>;
|
||||
|
||||
The above mapping describes that the logical data lane DATA3 is mapped to
|
||||
the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
|
||||
to phys DATA2 and logic DATA2 to phys DATA3.
|
||||
The above mapping describes that the logical data lane DATA0 is mapped to
|
||||
the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
|
||||
to phys DATA1 and logic DATA3 to phys DATA2.
|
||||
|
||||
There are only a limited number of physical to logical mappings possible:
|
||||
|
||||
"0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
|
||||
"3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
|
||||
"2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
|
||||
"1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
|
||||
"0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
|
||||
"1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
|
||||
"2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
|
||||
"3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
|
||||
<0 1 2 3>
|
||||
<1 2 3 0>
|
||||
<2 3 0 1>
|
||||
<3 0 1 2>
|
||||
<0 3 2 1>
|
||||
<1 0 3 2>
|
||||
<2 1 0 3>
|
||||
<3 2 1 0>
|
||||
|
||||
DSI PHY:
|
||||
Required properties:
|
||||
|
@ -86,11 +94,12 @@ Required properties:
|
|||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_regulator"
|
||||
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
|
||||
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
|
||||
- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
|
||||
be 0 or 1, since we have 2 DSI PHYs at most for now.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
|
||||
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
|
||||
- clock-names: the following clocks are required:
|
||||
* "iface_clk"
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
|
@ -99,11 +108,16 @@ Optional properties:
|
|||
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
|
||||
regulator is wanted.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/graph.txt
|
||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[4] Documentation/devicetree/bindings/display/panel/
|
||||
|
||||
Example:
|
||||
mdss_dsi0: qcom,mdss_dsi@fd922800 {
|
||||
dsi0: dsi@fd922800 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
qcom,dsi-host-index = <0>;
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupt-parent = <&mdp>;
|
||||
interrupts = <4 0>;
|
||||
reg-names = "dsi_ctrl";
|
||||
reg = <0xfd922800 0x200>;
|
||||
|
@ -124,19 +138,48 @@ Example:
|
|||
<&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_PCLK0_CLK>;
|
||||
|
||||
assigned-clocks =
|
||||
<&mmcc BYTE0_CLK_SRC>,
|
||||
<&mmcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents =
|
||||
<&dsi_phy0 0>,
|
||||
<&dsi_phy0 1>;
|
||||
|
||||
vdda-supply = <&pma8084_l2>;
|
||||
vdd-supply = <&pma8084_l22>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0>;
|
||||
phys = <&dsi_phy0>;
|
||||
phy-names ="dsi-phy";
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
qcom,sync-dual-dsi;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mdss_dsi_active>;
|
||||
pinctrl-1 = <&mdss_dsi_suspend>;
|
||||
pinctrl-0 = <&dsi_active>;
|
||||
pinctrl-1 = <&dsi_suspend>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: panel@0 {
|
||||
compatible = "sharp,lq101r1sx01";
|
||||
|
@ -152,16 +195,9 @@ Example:
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
port {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
|
||||
dsi_phy0: dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-hpm";
|
||||
qcom,dsi-phy-index = <0>;
|
||||
reg-names =
|
||||
|
@ -173,6 +209,7 @@ Example:
|
|||
<0xfd922d80 0x7b>;
|
||||
clock-names = "iface_clk";
|
||||
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy-regulator-ldo-mode;
|
||||
|
|
|
@ -1,59 +0,0 @@
|
|||
Qualcomm adreno/snapdragon display controller
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp4" - mdp4
|
||||
* "qcom,mdp5" - mdp5
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- connectors: array of phandles for output device(s)
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
For MDP4:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "lut_clk"
|
||||
* "src_clk"
|
||||
* "hdmi_clk"
|
||||
* "mdp_clk"
|
||||
For MDP5:
|
||||
* "bus_clk"
|
||||
* "iface_clk"
|
||||
* "core_clk_src"
|
||||
* "core_clk"
|
||||
* "lut_clk" (some MDP5 versions may not need this)
|
||||
* "vsync_clk"
|
||||
|
||||
Optional properties:
|
||||
- gpus: phandle for gpu device
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdp: qcom,mdp@5100000 {
|
||||
compatible = "qcom,mdp4";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
connectors = <&hdmi>;
|
||||
gpus = <&gpu>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"lut_clk",
|
||||
"src_clk",
|
||||
"hdmi_clk",
|
||||
"mdp_clk";
|
||||
clocks =
|
||||
<&mmcc MDP_SRC>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc TV_SRC>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
};
|
||||
};
|
|
@ -0,0 +1,112 @@
|
|||
Qualcomm adreno/snapdragon MDP4 display controller
|
||||
|
||||
Description:
|
||||
|
||||
This is the bindings documentation for the MDP4 display controller found in
|
||||
SoCs like MSM8960, APQ8064 and MSM8660.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp4" - mdp4
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the display controller.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "bus_clk"
|
||||
* "lut_clk"
|
||||
* "hdmi_clk"
|
||||
* "tv_clk"
|
||||
- ports: contains the list of output ports from MDP. These connect to interfaces
|
||||
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
|
||||
special case since it is a part of the MDP block itself).
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
The output port mappings are:
|
||||
Port 0 -> LCDC/LVDS
|
||||
Port 1 -> DSI1 Cmd/Video
|
||||
Port 2 -> DSI2 Cmd/Video
|
||||
Port 3 -> DTV
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
hdmi: hdmi@4a00000 {
|
||||
...
|
||||
ports {
|
||||
...
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hdmi_in: endpoint {
|
||||
remote-endpoint = <&mdp_dtv_out>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
mdp: mdp@5100000 {
|
||||
compatible = "qcom,mdp4";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 0>;
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"lut_clk",
|
||||
"hdmi_clk",
|
||||
"tv_clk";
|
||||
clocks =
|
||||
<&mmcc MDP_CLK>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_AXI_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp_lvds_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdp_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
mdp_dsi2_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
mdp_dtv_out: endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,160 @@
|
|||
Qualcomm adreno/snapdragon MDP5 display controller
|
||||
|
||||
Description:
|
||||
|
||||
This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
|
||||
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
|
||||
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
|
||||
|
||||
MDSS:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdss" - MDSS
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "mdss_phys"
|
||||
* "vbif_phys"
|
||||
- interrupts: The interrupt signal from MDSS.
|
||||
- interrupt-controller: identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- power-domains: a power domain consumer specifier according to
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
* "iface_clk"
|
||||
* "bus_clk"
|
||||
* "vsync_clk"
|
||||
- #address-cells: number of address cells for the MDSS children. Should be 1.
|
||||
- #size-cells: Should be 1.
|
||||
- ranges: parent bus address space is the same as the child bus address space.
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
MDP5:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp5" - MDP5
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "mdp_phys"
|
||||
- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
|
||||
- interrupt-parent: phandle to the MDSS block
|
||||
through MDP block
|
||||
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
- * "bus_clk"
|
||||
- * "iface_clk"
|
||||
- * "core_clk"
|
||||
- * "vsync_clk"
|
||||
- ports: contains the list of output ports from MDP. These connect to interfaces
|
||||
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
|
||||
special case since it is a part of the MDP block itself).
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
The availability of output ports can vary across SoC revisions:
|
||||
|
||||
For MSM8974 and APQ8084:
|
||||
Port 0 -> MDP_INTF0 (eDP)
|
||||
Port 1 -> MDP_INTF1 (DSI1)
|
||||
Port 2 -> MDP_INTF2 (DSI2)
|
||||
Port 3 -> MDP_INTF3 (HDMI)
|
||||
|
||||
For MSM8916:
|
||||
Port 0 -> MDP_INTF1 (DSI1)
|
||||
|
||||
For MSM8994 and MSM8996:
|
||||
Port 0 -> MDP_INTF1 (DSI1)
|
||||
Port 1 -> MDP_INTF2 (DSI2)
|
||||
Port 2 -> MDP_INTF3 (HDMI)
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdss: mdss@1a00000 {
|
||||
compatible = "qcom,mdss";
|
||||
reg = <0x1a00000 0x1000>,
|
||||
<0x1ac8000 0x3000>;
|
||||
reg-names = "mdss_phys", "vbif_phys";
|
||||
|
||||
power-domains = <&gcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface_clk",
|
||||
"bus_clk",
|
||||
"vsync_clk"
|
||||
|
||||
interrupts = <0 72 0>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mdp: mdp@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
reg = <0x1a01000 0x90000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0 0>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface_clk",
|
||||
"bus_clk",
|
||||
"core_clk",
|
||||
"vsync_clk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@1a98000 {
|
||||
...
|
||||
ports {
|
||||
...
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf1_out>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
dsi_phy0: dsi-phy@1a98300 {
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,7 @@
|
|||
LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "lg,lp079qx1-sp0v"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
|
@ -0,0 +1,7 @@
|
|||
LG 9.7" (2048x1536 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "lg,lp097qx1-spa1"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
|
@ -7,6 +7,8 @@ Required properties:
|
|||
Optional properties:
|
||||
- label: a symbolic name for the panel
|
||||
- enable-gpios: panel enable gpio
|
||||
- reset-gpios: GPIO to control the RESET pin
|
||||
- vcc-supply: phandle of regulator that will be used to enable power to the display
|
||||
|
||||
Required nodes:
|
||||
- "panel-timing" containing video timings
|
||||
|
|
|
@ -0,0 +1,7 @@
|
|||
Samsung 12.2" (2560x1600 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "samsung,lsn122dl01-c01"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
|
@ -0,0 +1,7 @@
|
|||
Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "sharp,lq101k1ly04"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
|
@ -0,0 +1,7 @@
|
|||
Sharp 12.3" (2400x1600 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "sharp,lq123p1jx31"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
|
@ -0,0 +1,7 @@
|
|||
Starry 12.2" (1920x1200 pixels) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "starry,kr122ea0sra"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
|
@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display Port
|
|||
================================
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk3288-edp";
|
||||
- compatible: "rockchip,rk3288-dp",
|
||||
"rockchip,rk3399-edp";
|
||||
|
||||
- reg: physical base address of the controller and length
|
||||
|
||||
|
@ -27,6 +28,12 @@ Required properties:
|
|||
Port 0: contained 2 endpoints, connecting to the output of vop.
|
||||
Port 1: contained 1 endpoint, connecting to the input of panel.
|
||||
|
||||
Optional property for different chips:
|
||||
- clocks: from common clock binding: handle to grf_vio clock.
|
||||
|
||||
- clock-names: from common clock binding:
|
||||
Required elements: "grf"
|
||||
|
||||
For the below properties, please refer to Analogix DP binding document:
|
||||
* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
|
||||
- phys (required)
|
||||
|
|
|
@ -208,6 +208,7 @@ of the following host1x client modules:
|
|||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- sor: clock input for the SOR hardware
|
||||
- source: source clock for the SOR clock
|
||||
- parent: input for the pixel clock
|
||||
- dp: reference clock for the SOR clock
|
||||
- safe: safe reference for the SOR clock during power up
|
||||
|
@ -226,9 +227,9 @@ of the following host1x client modules:
|
|||
- nvidia,dpaux: phandle to a DispayPort AUX interface
|
||||
|
||||
- dpaux: DisplayPort AUX interface
|
||||
- compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
|
||||
must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
|
||||
<chip> is tegra132.
|
||||
- compatible : Should contain one of the following:
|
||||
- "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
|
||||
- "nvidia,tegra210-dpaux": for Tegra210
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
|
@ -241,6 +242,12 @@ of the following host1x client modules:
|
|||
- reset-names: Must include the following entries:
|
||||
- dpaux
|
||||
- vdd-supply: phandle of a supply that powers the DisplayPort link
|
||||
- i2c-bus: Subnode where I2C slave devices are listed. This subnode
|
||||
must be always present. If there are no I2C slave devices, an empty
|
||||
node should be added. See ../../i2c/i2c.txt for more information.
|
||||
|
||||
See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
|
||||
regarding the DPAUX pad controller bindings.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
@ -0,0 +1,24 @@
|
|||
* Marvell XOR v2 engines
|
||||
|
||||
Required properties:
|
||||
- compatible: one of the following values:
|
||||
"marvell,armada-7k-xor"
|
||||
"marvell,xor-v2"
|
||||
- reg: Should contain registers location and length (two sets)
|
||||
the first set is the DMA registers
|
||||
the second set is the global registers
|
||||
- msi-parent: Phandle to the MSI-capable interrupt controller used for
|
||||
interrupts.
|
||||
|
||||
Optional properties:
|
||||
- clocks: Optional reference to the clock used by the XOR engine.
|
||||
|
||||
Example:
|
||||
|
||||
xor0@400000 {
|
||||
compatible = "marvell,xor-v2";
|
||||
reg = <0x400000 0x1000>,
|
||||
<0x410000 0x1000>;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
dma-coherent;
|
||||
};
|
|
@ -15,7 +15,7 @@ Required properties:
|
|||
- reg: Memory map of eDMA CC
|
||||
- reg-names: "edma3_cc"
|
||||
- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
|
||||
- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
|
||||
- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
|
||||
- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
|
||||
<&tptc_phandle TC_priority_number>. The highest priority is 0.
|
||||
|
||||
|
@ -48,7 +48,7 @@ edma: edma@49000000 {
|
|||
reg = <0x49000000 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
|
|
|
@ -1,46 +1,96 @@
|
|||
Xilinx AXI VDMA engine, it does transfers between memory and video devices.
|
||||
It can be configured to have one channel or two channels. If configured
|
||||
as two channels, one is to transmit to the video device and another is
|
||||
to receive from the video device.
|
||||
|
||||
Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
|
||||
target devices. It can be configured to have one channel or two channels.
|
||||
If configured as two channels, one is to transmit to the device and another
|
||||
is to receive from the device.
|
||||
|
||||
Xilinx AXI CDMA engine, it does transfers between memory-mapped source
|
||||
address and a memory-mapped destination address.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "xlnx,axi-dma-1.00.a"
|
||||
- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
|
||||
"xlnx,axi-cdma-1.00.a""
|
||||
- #dma-cells: Should be <1>, see "dmas" property below
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- reg: Should contain VDMA registers location and length.
|
||||
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
|
||||
- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
|
||||
- dma-channel child node: Should have at least one channel and can have up to
|
||||
two channels per device. This node specifies the properties of each
|
||||
DMA channel (see child node properties below).
|
||||
- clocks: Input clock specifier. Refer to common clock bindings.
|
||||
- clock-names: List of input clocks
|
||||
For VDMA:
|
||||
Required elements: "s_axi_lite_aclk"
|
||||
Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
|
||||
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
|
||||
For CDMA:
|
||||
Required elements: "s_axi_lite_aclk", "m_axi_aclk"
|
||||
FOR AXIDMA:
|
||||
Required elements: "s_axi_lite_aclk"
|
||||
Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
|
||||
"m_axi_sg_aclk"
|
||||
|
||||
Required properties for VDMA:
|
||||
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
|
||||
|
||||
Optional properties:
|
||||
- xlnx,include-sg: Tells whether configured for Scatter-mode in
|
||||
- xlnx,include-sg: Tells configured for Scatter-mode in
|
||||
the hardware.
|
||||
Optional properties for AXI DMA:
|
||||
- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
|
||||
Optional properties for VDMA:
|
||||
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
|
||||
It takes following values:
|
||||
{1}, flush both channels
|
||||
{2}, flush mm2s channel
|
||||
{3}, flush s2mm channel
|
||||
|
||||
Required child node properties:
|
||||
- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
|
||||
- compatible:
|
||||
For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
|
||||
"xlnx,axi-vdma-s2mm-channel".
|
||||
For CDMA: It should be "xlnx,axi-cdma-channel".
|
||||
For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or
|
||||
"xlnx,axi-dma-s2mm-channel".
|
||||
- interrupts: Should contain per channel DMA interrupts.
|
||||
- interrupts: Should contain per channel VDMA interrupts.
|
||||
- xlnx,datawidth: Should contain the stream data width, take values
|
||||
{32,64...1024}.
|
||||
|
||||
Option child node properties:
|
||||
- xlnx,include-dre: Tells whether hardware is configured for Data
|
||||
Optional child node properties:
|
||||
- xlnx,include-dre: Tells hardware is configured for Data
|
||||
Realignment Engine.
|
||||
Optional child node properties for VDMA:
|
||||
- xlnx,genlock-mode: Tells Genlock synchronization is
|
||||
enabled/disabled in hardware.
|
||||
Optional child node properties for AXI DMA:
|
||||
-dma-channels: Number of dma channels in child node.
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
axi_dma_0: axidma@40400000 {
|
||||
compatible = "xlnx,axi-dma-1.00.a";
|
||||
axi_vdma_0: axivdma@40030000 {
|
||||
compatible = "xlnx,axi-vdma-1.00.a";
|
||||
#dma_cells = <1>;
|
||||
reg = < 0x40400000 0x10000 >;
|
||||
dma-channel@40400000 {
|
||||
compatible = "xlnx,axi-dma-mm2s-channel";
|
||||
interrupts = < 0 59 4 >;
|
||||
reg = < 0x40030000 0x10000 >;
|
||||
dma-ranges = <0x00000000 0x00000000 0x40000000>;
|
||||
xlnx,num-fstores = <0x8>;
|
||||
xlnx,flush-fsync = <0x1>;
|
||||
xlnx,addrwidth = <0x20>;
|
||||
clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
|
||||
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
|
||||
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
|
||||
dma-channel@40030000 {
|
||||
compatible = "xlnx,axi-vdma-mm2s-channel";
|
||||
interrupts = < 0 54 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
dma-channel@40400030 {
|
||||
compatible = "xlnx,axi-dma-s2mm-channel";
|
||||
interrupts = < 0 58 4 >;
|
||||
dma-channel@40030030 {
|
||||
compatible = "xlnx,axi-vdma-s2mm-channel";
|
||||
interrupts = < 0 53 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
} ;
|
||||
|
@ -49,7 +99,7 @@ axi_dma_0: axidma@40400000 {
|
|||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
|
||||
- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
|
||||
where Channel ID is '0' for write/tx and '1' for read/rx
|
||||
channel.
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
@ -57,9 +107,9 @@ Required properties:
|
|||
Example:
|
||||
++++++++
|
||||
|
||||
dmatest_0: dmatest@0 {
|
||||
compatible ="xlnx,axi-dma-test-1.00.a";
|
||||
dmas = <&axi_dma_0 0
|
||||
&axi_dma_0 1>;
|
||||
dma-names = "dma0", "dma1";
|
||||
vdmatest_0: vdmatest@0 {
|
||||
compatible ="xlnx,axi-vdma-test-1.00.a";
|
||||
dmas = <&axi_vdma_0 0
|
||||
&axi_vdma_0 1>;
|
||||
dma-names = "vdma0", "vdma1";
|
||||
} ;
|
||||
|
|
|
@ -1,107 +0,0 @@
|
|||
Xilinx AXI VDMA engine, it does transfers between memory and video devices.
|
||||
It can be configured to have one channel or two channels. If configured
|
||||
as two channels, one is to transmit to the video device and another is
|
||||
to receive from the video device.
|
||||
|
||||
Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
|
||||
target devices. It can be configured to have one channel or two channels.
|
||||
If configured as two channels, one is to transmit to the device and another
|
||||
is to receive from the device.
|
||||
|
||||
Xilinx AXI CDMA engine, it does transfers between memory-mapped source
|
||||
address and a memory-mapped destination address.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
|
||||
"xlnx,axi-cdma-1.00.a""
|
||||
- #dma-cells: Should be <1>, see "dmas" property below
|
||||
- reg: Should contain VDMA registers location and length.
|
||||
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
|
||||
- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
|
||||
- dma-channel child node: Should have at least one channel and can have up to
|
||||
two channels per device. This node specifies the properties of each
|
||||
DMA channel (see child node properties below).
|
||||
- clocks: Input clock specifier. Refer to common clock bindings.
|
||||
- clock-names: List of input clocks
|
||||
For VDMA:
|
||||
Required elements: "s_axi_lite_aclk"
|
||||
Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
|
||||
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
|
||||
For CDMA:
|
||||
Required elements: "s_axi_lite_aclk", "m_axi_aclk"
|
||||
FOR AXIDMA:
|
||||
Required elements: "s_axi_lite_aclk"
|
||||
Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
|
||||
"m_axi_sg_aclk"
|
||||
|
||||
Required properties for VDMA:
|
||||
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
|
||||
|
||||
Optional properties:
|
||||
- xlnx,include-sg: Tells configured for Scatter-mode in
|
||||
the hardware.
|
||||
Optional properties for VDMA:
|
||||
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
|
||||
It takes following values:
|
||||
{1}, flush both channels
|
||||
{2}, flush mm2s channel
|
||||
{3}, flush s2mm channel
|
||||
|
||||
Required child node properties:
|
||||
- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
|
||||
"xlnx,axi-vdma-s2mm-channel".
|
||||
- interrupts: Should contain per channel VDMA interrupts.
|
||||
- xlnx,datawidth: Should contain the stream data width, take values
|
||||
{32,64...1024}.
|
||||
|
||||
Optional child node properties:
|
||||
- xlnx,include-dre: Tells hardware is configured for Data
|
||||
Realignment Engine.
|
||||
Optional child node properties for VDMA:
|
||||
- xlnx,genlock-mode: Tells Genlock synchronization is
|
||||
enabled/disabled in hardware.
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
axi_vdma_0: axivdma@40030000 {
|
||||
compatible = "xlnx,axi-vdma-1.00.a";
|
||||
#dma_cells = <1>;
|
||||
reg = < 0x40030000 0x10000 >;
|
||||
dma-ranges = <0x00000000 0x00000000 0x40000000>;
|
||||
xlnx,num-fstores = <0x8>;
|
||||
xlnx,flush-fsync = <0x1>;
|
||||
xlnx,addrwidth = <0x20>;
|
||||
clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
|
||||
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
|
||||
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
|
||||
dma-channel@40030000 {
|
||||
compatible = "xlnx,axi-vdma-mm2s-channel";
|
||||
interrupts = < 0 54 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
dma-channel@40030030 {
|
||||
compatible = "xlnx,axi-vdma-s2mm-channel";
|
||||
interrupts = < 0 53 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
} ;
|
||||
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
|
||||
where Channel ID is '0' for write/tx and '1' for read/rx
|
||||
channel.
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
vdmatest_0: vdmatest@0 {
|
||||
compatible ="xlnx,axi-vdma-test-1.00.a";
|
||||
dmas = <&axi_vdma_0 0
|
||||
&axi_vdma_0 1>;
|
||||
dma-names = "vdma0", "vdma1";
|
||||
} ;
|
|
@ -0,0 +1,27 @@
|
|||
Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
|
||||
memory to device and device to memory transfers. It also has flow
|
||||
control and rate control support for slave/peripheral dma access.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "xlnx,zynqmp-dma-1.0"
|
||||
- reg : Memory map for gdma/adma module access.
|
||||
- interrupt-parent : Interrupt controller the interrupt is routed through
|
||||
- interrupts : Should contain DMA channel interrupt.
|
||||
- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
|
||||
- clock-names : List of input clocks "clk_main", "clk_apb"
|
||||
(see clock bindings for details)
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent : Present if dma operations are coherent.
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
fpd_dma_chan1: dma@fd500000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
reg = <0x0 0xFD500000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 117 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
xlnx,bus-width = <128>;
|
||||
dma-coherent;
|
||||
};
|
|
@ -46,7 +46,8 @@ Optional properties:
|
|||
The second cell represents the MICBIAS to be used.
|
||||
The third cell represents the value of the micd-pol-gpio pin.
|
||||
|
||||
- wlf,gpsw : Settings for the general purpose switch
|
||||
- wlf,gpsw : Settings for the general purpose switch, set as one of the
|
||||
ARIZONA_GPSW_XXX defines.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
@ -0,0 +1,28 @@
|
|||
QCOM Secure Channel Manager (SCM)
|
||||
|
||||
Qualcomm processors include an interface to communicate to the secure firmware.
|
||||
This interface allows for clients to request different types of actions. These
|
||||
can include CPU power up/down, HDCP requests, loading of firmware, and other
|
||||
assorted actions.
|
||||
|
||||
Required properties:
|
||||
- compatible: must contain one of the following:
|
||||
* "qcom,scm-apq8064" for APQ8064 platforms
|
||||
* "qcom,scm-msm8660" for MSM8660 platforms
|
||||
* "qcom,scm-msm8690" for MSM8690 platforms
|
||||
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
|
||||
- clocks: One to three clocks may be required based on compatible.
|
||||
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
|
||||
* Core, iface, and bus clocks required for "qcom,scm"
|
||||
- clock-names: Must contain "core" for the core clock, "iface" for the interface
|
||||
clock and "bus" for the bus clock per the requirements of the compatible.
|
||||
|
||||
Example for MSM8916:
|
||||
|
||||
firmware {
|
||||
scm {
|
||||
compatible = "qcom,scm";
|
||||
clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
|
||||
clock-names = "core", "bus", "iface";
|
||||
};
|
||||
};
|
|
@ -1,7 +1,7 @@
|
|||
* ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain "cirrus,clps711x-mctrl-gpio".
|
||||
- compatible: Should contain "cirrus,ep7209-mctrl-gpio".
|
||||
- gpio-controller: Marks the device node as a gpio controller.
|
||||
- #gpio-cells: Should be two. The first cell is the pin number and
|
||||
the second cell is used to specify the gpio polarity:
|
||||
|
@ -11,7 +11,7 @@ Required properties:
|
|||
Example:
|
||||
sysgpio: sysgpio {
|
||||
compatible = "cirrus,ep7312-mctrl-gpio",
|
||||
"cirrus,clps711x-mctrl-gpio";
|
||||
"cirrus,ep7209-mctrl-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
Cirrus Logic CLPS711X GPIO controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "cirrus,clps711x-gpio"
|
||||
- compatible: Should be "cirrus,ep7209-gpio"
|
||||
- reg: Physical base GPIO controller registers location and length.
|
||||
There should be two registers, first is DATA register, the second
|
||||
is DIRECTION.
|
||||
|
@ -21,7 +21,7 @@ aliases {
|
|||
};
|
||||
|
||||
porta: gpio@80000000 {
|
||||
compatible = "cirrus,clps711x-gpio";
|
||||
compatible = "cirrus,ep7312-gpio","cirrus,ep7209-gpio";
|
||||
reg = <0x80000000 0x1>, <0x80000040 0x1>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
|
@ -0,0 +1,25 @@
|
|||
GPIO driver for MAX77620 Power management IC from Maxim Semiconductor.
|
||||
|
||||
Device has 8 GPIO pins which can be configured as GPIO as well as the
|
||||
special IO functions.
|
||||
|
||||
Required properties:
|
||||
-------------------
|
||||
- gpio-controller : Marks the device node as a gpio controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and
|
||||
the second cell is used to specify the gpio polarity:
|
||||
0 = active high
|
||||
1 = active low
|
||||
For more details, please refer generic GPIO DT binding document
|
||||
<devicetree/bindings/gpio/gpio.txt>.
|
||||
|
||||
Example:
|
||||
--------
|
||||
#include <dt-bindings/mfd/max77620.h>
|
||||
...
|
||||
max77620@3c {
|
||||
compatible = "maxim,max77620";
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
|
@ -21,6 +21,7 @@ Required properties:
|
|||
maxim,max7313
|
||||
maxim,max7315
|
||||
ti,pca6107
|
||||
ti,pca9536
|
||||
ti,tca6408
|
||||
ti,tca6416
|
||||
ti,tca6424
|
||||
|
|
|
@ -0,0 +1,47 @@
|
|||
* Oxford Semiconductor OXNAS SoC GPIO Controller
|
||||
|
||||
Please refer to gpio.txt for generic information regarding GPIO bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: "oxsemi,ox810se-gpio"
|
||||
- reg: Base address and length for the device.
|
||||
- interrupts: The port interrupt shared by all pins.
|
||||
- gpio-controller: Marks the port as GPIO controller.
|
||||
- #gpio-cells: Two. The first cell is the pin number and
|
||||
the second cell is used to specify the gpio polarity as defined in
|
||||
defined in <dt-bindings/gpio/gpio.h>:
|
||||
0 = GPIO_ACTIVE_HIGH
|
||||
1 = GPIO_ACTIVE_LOW
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Two. The first cell is the GPIO number and second cell
|
||||
is used to specify the trigger type as defined in
|
||||
<dt-bindings/interrupt-controller/irq.h>:
|
||||
IRQ_TYPE_EDGE_RISING
|
||||
IRQ_TYPE_EDGE_FALLING
|
||||
IRQ_TYPE_EDGE_BOTH
|
||||
- gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
|
||||
gpio base and count, should be in the format of numeric-gpio-range as
|
||||
specified in the gpio.txt file.
|
||||
|
||||
Example:
|
||||
|
||||
gpio0: gpio@0 {
|
||||
compatible = "oxsemi,ox810se-gpio";
|
||||
reg = <0x000000 0x100000>;
|
||||
interrupts = <21>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
};
|
||||
|
||||
keys {
|
||||
...
|
||||
|
||||
button-esc {
|
||||
label = "ESC";
|
||||
linux,code = <1>;
|
||||
gpios = <&gpio0 12 0>;
|
||||
};
|
||||
};
|
|
@ -7,6 +7,7 @@ Required Properties:
|
|||
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7792": for R8A7792 (R-Car V2H) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
|
||||
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
|
||||
|
|
|
@ -0,0 +1,14 @@
|
|||
APM X-Gene hwmon driver
|
||||
|
||||
APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox.
|
||||
|
||||
Required properties :
|
||||
- compatible : should be "apm,xgene-slimpro-hwmon"
|
||||
- mboxes : use the label reference for the mailbox as the first parameter.
|
||||
The second parameter is the channel number.
|
||||
|
||||
Example :
|
||||
hwmonslimpro {
|
||||
compatible = "apm,xgene-slimpro-hwmon";
|
||||
mboxes = <&mailbox 7>;
|
||||
};
|
|
@ -0,0 +1,42 @@
|
|||
Properties for Jedec JC-42.4 compatible temperature sensors
|
||||
|
||||
Required properties:
|
||||
- compatible: May include a device-specific string consisting of the
|
||||
manufacturer and the name of the chip. A list of supported
|
||||
chip names follows.
|
||||
Must include "jedec,jc-42.4-temp" for any Jedec JC-42.4
|
||||
compatible temperature sensor.
|
||||
|
||||
Supported chip names:
|
||||
adi,adt7408
|
||||
atmel,at30ts00
|
||||
atmel,at30tse004
|
||||
onnn,cat6095
|
||||
onnn,cat34ts02
|
||||
maxim,max6604
|
||||
microchip,mcp9804
|
||||
microchip,mcp9805
|
||||
microchip,mcp9808
|
||||
microchip,mcp98243
|
||||
microchip,mcp98244
|
||||
microchip,mcp9843
|
||||
nxp,se97
|
||||
nxp,se98
|
||||
st,stts2002
|
||||
st,stts2004
|
||||
st,stts3000
|
||||
st,stts424
|
||||
st,stts424e
|
||||
idt,tse2002
|
||||
idt,tse2004
|
||||
idt,ts3000
|
||||
idt,ts3001
|
||||
|
||||
- reg: I2C address
|
||||
|
||||
Example:
|
||||
|
||||
temp-sensor@1a {
|
||||
compatible = "jedec,jc-42.4-temp";
|
||||
reg = <0x1a>;
|
||||
};
|
|
@ -6,10 +6,20 @@ RK3xxx SoCs.
|
|||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c",
|
||||
"rockchip,rk3228-i2c" or "rockchip,rk3288-i2c".
|
||||
- compatible: should be one of the following:
|
||||
- "rockchip,rk3066-i2c": for rk3066
|
||||
- "rockchip,rk3188-i2c": for rk3188
|
||||
- "rockchip,rk3228-i2c": for rk3228
|
||||
- "rockchip,rk3288-i2c": for rk3288
|
||||
- "rockchip,rk3399-i2c": for rk3399
|
||||
- interrupts : interrupt number
|
||||
- clocks : parent clock
|
||||
- clocks: See ../clock/clock-bindings.txt
|
||||
- For older hardware (rk3066, rk3188, rk3228, rk3288):
|
||||
- There is one clock that's used both to derive the functional clock
|
||||
for the device and as the bus clock.
|
||||
- For newer hardware (rk3399): specified by name
|
||||
- "i2c": This is used to derive the functional clock.
|
||||
- "pclk": This is the bus clock.
|
||||
|
||||
Required on RK3066, RK3188 :
|
||||
|
||||
|
|
|
@ -62,6 +62,13 @@ wants to support one of the below features, it should adapt the bindings below.
|
|||
- wakeup-source
|
||||
device can be used as a wakeup source.
|
||||
|
||||
- reg
|
||||
I2C slave addresses
|
||||
|
||||
- reg-names
|
||||
Names of map programmable addresses.
|
||||
It can contain any map needing another address than default one.
|
||||
|
||||
Binding may contain optional "interrupts" property, describing interrupts
|
||||
used by the device. I2C core will assign "irq" interrupt (or the very first
|
||||
interrupt if not using interrupt names) as primary interrupt for the slave.
|
||||
|
|
|
@ -56,12 +56,77 @@ maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
|
|||
maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
|
||||
maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
|
||||
mc,rv3029c2 Real Time Clock Module with I2C-Bus
|
||||
microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
|
||||
microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
|
||||
microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)
|
||||
microchip,mcp4531-104 Microchip 7-bit Single I2C Digital Potentiometer (100k)
|
||||
microchip,mcp4532-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
|
||||
microchip,mcp4532-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
|
||||
microchip,mcp4532-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)
|
||||
microchip,mcp4532-104 Microchip 7-bit Single I2C Digital Potentiometer (100k)
|
||||
microchip,mcp4541-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
|
||||
microchip,mcp4541-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
|
||||
microchip,mcp4541-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
|
||||
microchip,mcp4541-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
|
||||
microchip,mcp4542-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
|
||||
microchip,mcp4542-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
|
||||
microchip,mcp4542-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
|
||||
microchip,mcp4542-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
|
||||
microchip,mcp4551-502 Microchip 8-bit Single I2C Digital Potentiometer (5k)
|
||||
microchip,mcp4551-103 Microchip 8-bit Single I2C Digital Potentiometer (10k)
|
||||
microchip,mcp4551-503 Microchip 8-bit Single I2C Digital Potentiometer (50k)
|
||||
microchip,mcp4551-104 Microchip 8-bit Single I2C Digital Potentiometer (100k)
|
||||
microchip,mcp4552-502 Microchip 8-bit Single I2C Digital Potentiometer (5k)
|
||||
microchip,mcp4552-103 Microchip 8-bit Single I2C Digital Potentiometer (10k)
|
||||
microchip,mcp4552-503 Microchip 8-bit Single I2C Digital Potentiometer (50k)
|
||||
microchip,mcp4552-104 Microchip 8-bit Single I2C Digital Potentiometer (100k)
|
||||
microchip,mcp4561-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
|
||||
microchip,mcp4561-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
|
||||
microchip,mcp4561-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
|
||||
microchip,mcp4561-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
|
||||
microchip,mcp4562-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
|
||||
microchip,mcp4562-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
|
||||
microchip,mcp4562-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
|
||||
microchip,mcp4562-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
|
||||
microchip,mcp4631-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k)
|
||||
microchip,mcp4631-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k)
|
||||
microchip,mcp4631-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k)
|
||||
microchip,mcp4631-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k)
|
||||
microchip,mcp4632-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k)
|
||||
microchip,mcp4632-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k)
|
||||
microchip,mcp4632-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k)
|
||||
microchip,mcp4632-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k)
|
||||
microchip,mcp4641-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
|
||||
microchip,mcp4641-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
|
||||
microchip,mcp4641-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
|
||||
microchip,mcp4641-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
|
||||
microchip,mcp4642-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
|
||||
microchip,mcp4642-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
|
||||
microchip,mcp4642-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
|
||||
microchip,mcp4642-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
|
||||
microchip,mcp4651-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k)
|
||||
microchip,mcp4651-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k)
|
||||
microchip,mcp4651-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k)
|
||||
microchip,mcp4651-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k)
|
||||
microchip,mcp4652-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k)
|
||||
microchip,mcp4652-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k)
|
||||
microchip,mcp4652-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k)
|
||||
microchip,mcp4652-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k)
|
||||
microchip,mcp4661-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
|
||||
microchip,mcp4661-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
|
||||
microchip,mcp4661-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
|
||||
microchip,mcp4661-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
|
||||
microchip,mcp4662-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
|
||||
microchip,mcp4662-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
|
||||
microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
|
||||
microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
|
||||
national,lm63 Temperature sensor with integrated fan control
|
||||
national,lm75 I2C TEMP SENSOR
|
||||
national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
|
||||
national,lm85 Temperature sensor with integrated fan control
|
||||
national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
|
||||
nuvoton,npct501 i2c trusted platform module (TPM)
|
||||
nuvoton,npct601 i2c trusted platform module (TPM2)
|
||||
nxp,pca9556 Octal SMBus and I2C registered interface
|
||||
nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
|
||||
nxp,pcf8563 Real-time clock/calendar
|
||||
|
@ -81,10 +146,10 @@ samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
|
|||
sgx,vz89x SGX Sensortech VZ89X Sensors
|
||||
sii,s35390a 2-wire CMOS real-time clock
|
||||
skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
|
||||
st-micro,24c256 i2c serial eeprom (24cxx)
|
||||
stm,m41t00 Serial Access TIMEKEEPER
|
||||
stm,m41t62 Serial real-time clock (RTC) with alarm
|
||||
stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
|
||||
st,24c256 i2c serial eeprom (24cxx)
|
||||
st,m41t00 Serial real-time clock (RTC)
|
||||
st,m41t62 Serial real-time clock (RTC) with alarm
|
||||
st,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
|
||||
taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
|
||||
ti,ads7828 8-Channels, 12-bit ADC
|
||||
ti,ads7830 8-Channels, 8-bit ADC
|
||||
|
|
|
@ -59,28 +59,24 @@ adc0: adc@fffb0000 {
|
|||
atmel,adc-res-names = "lowres", "highres";
|
||||
atmel,adc-use-res = "lowres";
|
||||
|
||||
trigger@0 {
|
||||
reg = <0>;
|
||||
trigger0 {
|
||||
trigger-name = "external-rising";
|
||||
trigger-value = <0x1>;
|
||||
trigger-external;
|
||||
};
|
||||
trigger@1 {
|
||||
reg = <1>;
|
||||
trigger1 {
|
||||
trigger-name = "external-falling";
|
||||
trigger-value = <0x2>;
|
||||
trigger-external;
|
||||
};
|
||||
|
||||
trigger@2 {
|
||||
reg = <2>;
|
||||
trigger2 {
|
||||
trigger-name = "external-any";
|
||||
trigger-value = <0x3>;
|
||||
trigger-external;
|
||||
};
|
||||
|
||||
trigger@3 {
|
||||
reg = <3>;
|
||||
trigger3 {
|
||||
trigger-name = "continuous";
|
||||
trigger-value = <0x6>;
|
||||
};
|
||||
|
|
|
@ -0,0 +1,41 @@
|
|||
* Broadcom's IPROC Static ADC controller
|
||||
|
||||
Broadcom iProc ADC controller has 8 channels 10bit ADC.
|
||||
Allows user to convert analog input voltage values to digital.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be "brcm,iproc-static-adc"
|
||||
|
||||
- adc-syscon: Handler of syscon node defining physical base address of the
|
||||
controller and length of memory mapped region.
|
||||
|
||||
- #io-channel-cells = <1>; As ADC has multiple outputs
|
||||
refer to Documentation/devicetree/bindings/iio/iio-bindings.txt for details.
|
||||
|
||||
- io-channel-ranges:
|
||||
refer to Documentation/devicetree/bindings/iio/iio-bindings.txt for details.
|
||||
|
||||
- clocks: Clock used for this block.
|
||||
|
||||
- clock-names: Clock name should be given as tsc_clk.
|
||||
|
||||
- interrupts: interrupt line number.
|
||||
|
||||
For example:
|
||||
|
||||
ts_adc_syscon: ts_adc_syscon@180a6000 {
|
||||
compatible = "brcm,iproc-ts-adc-syscon","syscon";
|
||||
reg = <0x180a6000 0xc30>;
|
||||
};
|
||||
|
||||
adc: adc@180a6000 {
|
||||
compatible = "brcm,iproc-static-adc";
|
||||
adc-syscon = <&ts_adc_syscon>;
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
|
||||
clock-names = "tsc_clk";
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
|
@ -0,0 +1,63 @@
|
|||
* Maxim 1x3x/136x/116xx Analog to Digital Converter (ADC)
|
||||
|
||||
The node for this driver must be a child node of a I2C controller, hence
|
||||
all mandatory properties for your controller must be specified. See directory:
|
||||
|
||||
Documentation/devicetree/bindings/i2c
|
||||
|
||||
for more details.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of
|
||||
"maxim,max1361"
|
||||
"maxim,max1362"
|
||||
"maxim,max1363"
|
||||
"maxim,max1364"
|
||||
"maxim,max1036"
|
||||
"maxim,max1037"
|
||||
"maxim,max1038"
|
||||
"maxim,max1039"
|
||||
"maxim,max1136"
|
||||
"maxim,max1137"
|
||||
"maxim,max1138"
|
||||
"maxim,max1139"
|
||||
"maxim,max1236"
|
||||
"maxim,max1237"
|
||||
"maxim,max1238"
|
||||
"maxim,max1239"
|
||||
"maxim,max11600"
|
||||
"maxim,max11601"
|
||||
"maxim,max11602"
|
||||
"maxim,max11603"
|
||||
"maxim,max11604"
|
||||
"maxim,max11605"
|
||||
"maxim,max11606"
|
||||
"maxim,max11607"
|
||||
"maxim,max11608"
|
||||
"maxim,max11609"
|
||||
"maxim,max11610"
|
||||
"maxim,max11611"
|
||||
"maxim,max11612"
|
||||
"maxim,max11613"
|
||||
"maxim,max11614"
|
||||
"maxim,max11615"
|
||||
"maxim,max11616"
|
||||
"maxim,max11617"
|
||||
"maxim,max11644"
|
||||
"maxim,max11645"
|
||||
"maxim,max11646"
|
||||
"maxim,max11647"
|
||||
- reg: Should contain the ADC I2C address
|
||||
|
||||
Optional properties:
|
||||
- vcc-supply: phandle to the regulator that provides power to the ADC.
|
||||
- vref-supply: phandle to the regulator for ADC reference voltage.
|
||||
- interrupts: IRQ line for the ADC. If not used the driver will use
|
||||
polling.
|
||||
|
||||
Example:
|
||||
adc: max11644@36 {
|
||||
compatible = "maxim,max11644";
|
||||
reg = <0x36>;
|
||||
vref-supply = <&adc_vref>;
|
||||
};
|
|
@ -0,0 +1,22 @@
|
|||
* Atlas Scientific EC-SM OEM sensor
|
||||
|
||||
http://www.atlas-scientific.com/_files/_datasheets/_oem/EC_oem_datasheet.pdf
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be "atlas,ec-sm"
|
||||
- reg: the I2C address of the sensor
|
||||
- interrupt-parent: should be the phandle for the interrupt controller
|
||||
- interrupts: the sole interrupt generated by the device
|
||||
|
||||
Refer to interrupt-controller/interrupts.txt for generic interrupt client
|
||||
node bindings.
|
||||
|
||||
Example:
|
||||
|
||||
atlas@64 {
|
||||
compatible = "atlas,ec-sm";
|
||||
reg = <0x64>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <16 2>;
|
||||
};
|
|
@ -0,0 +1,124 @@
|
|||
* Analog Device AD5755 IIO Multi-Channel DAC Linux Driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Has to contain one of the following:
|
||||
adi,ad5755
|
||||
adi,ad5755-1
|
||||
adi,ad5757
|
||||
adi,ad5735
|
||||
adi,ad5737
|
||||
|
||||
- reg: spi chip select number for the device
|
||||
- spi-cpha or spi-cpol: is the only modes that is supported
|
||||
|
||||
Recommended properties:
|
||||
- spi-max-frequency: Definition as per
|
||||
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
|
||||
Optional properties:
|
||||
See include/dt-bindings/iio/ad5755.h
|
||||
- adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
|
||||
external resistor and thereby bypasses
|
||||
the internal compensation resistor.
|
||||
- adi,dc-dc-phase:
|
||||
Valid values for DC DC Phase control is:
|
||||
0: All dc-to-dc converters clock on the same edge.
|
||||
1: Channel A and Channel B clock on the same edge,
|
||||
Channel C and Channel D clock on opposite edges.
|
||||
2: Channel A and Channel C clock on the same edge,
|
||||
Channel B and Channel D clock on opposite edges.
|
||||
3: Channel A, Channel B, Channel C, and Channel D
|
||||
clock 90 degrees out of phase from each other.
|
||||
- adi,dc-dc-freq-hz:
|
||||
Valid values for DC DC frequency is [Hz]:
|
||||
250000
|
||||
410000
|
||||
650000
|
||||
- adi,dc-dc-max-microvolt:
|
||||
Valid values for the maximum allowed Vboost voltage supplied by
|
||||
the dc-to-dc converter is:
|
||||
23000000
|
||||
24500000
|
||||
27000000
|
||||
29500000
|
||||
|
||||
Optional for every channel:
|
||||
- adi,mode:
|
||||
Valid values for DAC modes is:
|
||||
0: 0 V to 5 V voltage range.
|
||||
1: 0 V to 10 V voltage range.
|
||||
2: Plus minus 5 V voltage range.
|
||||
3: Plus minus 10 V voltage range.
|
||||
4: 4 mA to 20 mA current range.
|
||||
5: 0 mA to 20 mA current range.
|
||||
6: 0 mA to 24 mA current range.
|
||||
- adi,ext-current-sense-resistor: boolean set if the hardware a external
|
||||
current sense resistor.
|
||||
- adi,enable-voltage-overrange: boolean enable voltage overrange
|
||||
- adi,slew: Array of slewrate settings should contain 3 fields:
|
||||
1: Should be either 0 or 1 in order to enable or disable slewrate.
|
||||
2: Slew rate settings:
|
||||
Valid values for the slew rate update frequency:
|
||||
64000
|
||||
32000
|
||||
16000
|
||||
8000
|
||||
4000
|
||||
2000
|
||||
1000
|
||||
500
|
||||
250
|
||||
125
|
||||
64
|
||||
32
|
||||
16
|
||||
8
|
||||
4
|
||||
0
|
||||
3: Slew step size:
|
||||
Valid values for the step size LSBs:
|
||||
1
|
||||
2
|
||||
4
|
||||
16
|
||||
32
|
||||
64
|
||||
128
|
||||
256
|
||||
|
||||
Example:
|
||||
dac@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "adi,ad5755";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-cpha;
|
||||
adi,dc-dc-phase = <0>;
|
||||
adi,dc-dc-freq-hz = <410000>;
|
||||
adi,dc-dc-max-microvolt = <23000000>;
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
adi,mode = <4>;
|
||||
adi,ext-current-sense-resistor;
|
||||
adi,slew = <0 64000 1>;
|
||||
};
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
adi,mode = <4>;
|
||||
adi,ext-current-sense-resistor;
|
||||
adi,slew = <0 64000 1>;
|
||||
};
|
||||
channel@2 {
|
||||
reg = <2>;
|
||||
adi,mode = <4>;
|
||||
adi,ext-current-sense-resistor;
|
||||
adi,slew = <0 64000 1>;
|
||||
};
|
||||
channel@3 {
|
||||
reg = <3>;
|
||||
adi,mode = <4>;
|
||||
adi,ext-current-sense-resistor;
|
||||
adi,slew = <0 64000 1>;
|
||||
};
|
||||
};
|
|
@ -1,7 +1,11 @@
|
|||
BMP085/BMP18x digital pressure sensors
|
||||
BMP085/BMP18x/BMP28x digital pressure sensors
|
||||
|
||||
Required properties:
|
||||
- compatible: bosch,bmp085
|
||||
- compatible: must be one of:
|
||||
"bosch,bmp085"
|
||||
"bosch,bmp180"
|
||||
"bosch,bmp280"
|
||||
"bosch,bme280"
|
||||
|
||||
Optional properties:
|
||||
- chip-id: configurable chip id for non-default chip revisions
|
||||
|
@ -10,6 +14,10 @@ Optional properties:
|
|||
value range is 0-3 with rising sensitivity.
|
||||
- interrupt-parent: should be the phandle for the interrupt controller
|
||||
- interrupts: interrupt mapping for IRQ
|
||||
- reset-gpios: a GPIO line handling reset of the sensor: as the line is
|
||||
active low, it should be marked GPIO_ACTIVE_LOW (see gpio/gpio.txt)
|
||||
- vddd-supply: digital voltage regulator (see regulator/regulator.txt)
|
||||
- vdda-supply: analog voltage regulator (see regulator/regulator.txt)
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -21,4 +29,7 @@ pressure@77 {
|
|||
default-oversampling = <2>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
|
||||
reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
|
||||
vddd-supply = <&foo>;
|
||||
vdda-supply = <&bar>;
|
||||
};
|
||||
|
|
Before Width: | Height: | Size: 701 B After Width: | Height: | Size: 1.1 KiB |
|
@ -64,3 +64,4 @@ Pressure sensors:
|
|||
- st,lps001wp-press
|
||||
- st,lps25h-press
|
||||
- st,lps331ap-press
|
||||
- st,lps22hb-press
|
||||
|
|
|
@ -0,0 +1,36 @@
|
|||
Device tree bindings for Atmel capacitive touch device, typically
|
||||
an Atmel touch sensor connected to AtmegaXX MCU running firmware
|
||||
based on Qtouch library.
|
||||
|
||||
The node for this device must be a child of a I2C controller node, as the
|
||||
device communicates via I2C.
|
||||
|
||||
Required properties:
|
||||
|
||||
compatible: Must be "atmel,captouch".
|
||||
reg: The I2C slave address of the device.
|
||||
interrupts: Property describing the interrupt line the device
|
||||
is connected to. The device only has one interrupt
|
||||
source.
|
||||
linux,keycodes: Specifies an array of numeric keycode values to
|
||||
be used for reporting button presses. The array can
|
||||
contain up to 8 entries.
|
||||
|
||||
Optional properties:
|
||||
|
||||
autorepeat: Enables the Linux input system's autorepeat
|
||||
feature on the input device.
|
||||
|
||||
Example:
|
||||
|
||||
atmel-captouch@51 {
|
||||
compatible = "atmel,captouch";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
|
||||
linux,keycodes = <BTN_0>, <BTN_1>,
|
||||
<BTN_2>, <BTN_3>,
|
||||
<BTN_4>, <BTN_5>,
|
||||
<BTN_6>, <BTN_7>;
|
||||
autorepeat;
|
||||
};
|
|
@ -1,7 +1,7 @@
|
|||
* Cirrus Logic CLPS711X matrix keypad device tree bindings
|
||||
|
||||
Required Properties:
|
||||
- compatible: Shall contain "cirrus,clps711x-keypad".
|
||||
- compatible: Shall contain "cirrus,ep7209-keypad".
|
||||
- row-gpios: List of GPIOs used as row lines.
|
||||
- poll-interval: Poll interval time in milliseconds.
|
||||
- linux,keymap: The definition can be found at
|
||||
|
@ -12,7 +12,7 @@ Optional Properties:
|
|||
|
||||
Example:
|
||||
keypad {
|
||||
compatible = "cirrus,ep7312-keypad", "cirrus,clps711x-keypad";
|
||||
compatible = "cirrus,ep7312-keypad", "cirrus,ep7209-keypad";
|
||||
autorepeat;
|
||||
poll-interval = <120>;
|
||||
row-gpios = <&porta 0 0>,
|
||||
|
|
|
@ -0,0 +1,20 @@
|
|||
Raydium I2C touchscreen
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "raydium,rm32380"
|
||||
- reg: The I2C address of the device
|
||||
- interrupt-parent: the phandle for the interrupt controller
|
||||
- interrupts: interrupt to which the chip is connected
|
||||
See ../interrupt-controller/interrupts.txt
|
||||
Optional properties:
|
||||
- avdd-supply: analog power supply needed to power device
|
||||
- vccio-supply: IO Power source
|
||||
- reset-gpios: reset gpio the chip is connected to.
|
||||
|
||||
Example:
|
||||
touchscreen@39 {
|
||||
compatible = "raydium,rm32380";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
|
@ -22,6 +22,15 @@ See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
|||
- syna,reset-delay-ms: The number of milliseconds to wait after resetting the
|
||||
device.
|
||||
|
||||
- syna,startup-delay-ms: The number of milliseconds to wait after powering on
|
||||
the device.
|
||||
|
||||
- vdd-supply: VDD power supply.
|
||||
See ../regulator/regulator.txt
|
||||
|
||||
- vio-supply: VIO power supply
|
||||
See ../regulator/regulator.txt
|
||||
|
||||
Function Parameters:
|
||||
Parameters specific to RMI functions are contained in child nodes of the rmi device
|
||||
node. Documentation for the parameters of each function can be found in:
|
||||
|
|
|
@ -20,6 +20,8 @@ Optional properties:
|
|||
2: Half-period mode
|
||||
4: Quarter-period mode
|
||||
- wakeup-source: Boolean, rotary encoder can wake up the system.
|
||||
- rotary-encoder,encoding: String, the method used to encode steps.
|
||||
Supported are "gray" (the default and more common) and "binary".
|
||||
|
||||
Deprecated properties:
|
||||
- rotary-encoder,half-period: Makes the driver work on half-period mode.
|
||||
|
@ -34,6 +36,7 @@ Example:
|
|||
compatible = "rotary-encoder";
|
||||
gpios = <&gpio 19 1>, <&gpio 20 0>; /* GPIO19 is inverted */
|
||||
linux,axis = <0>; /* REL_X */
|
||||
rotary-encoder,encoding = "gray";
|
||||
rotary-encoder,relative-axis;
|
||||
};
|
||||
|
||||
|
@ -42,5 +45,6 @@ Example:
|
|||
gpios = <&gpio 21 0>, <&gpio 22 0>;
|
||||
linux,axis = <1>; /* ABS_Y */
|
||||
rotary-encoder,steps = <24>;
|
||||
rotary-encoder,encoding = "binary";
|
||||
rotary-encoder,rollover;
|
||||
};
|
||||
|
|
|
@ -0,0 +1,36 @@
|
|||
* GSL 1680 touchscreen controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "silead,gsl1680"
|
||||
- reg : I2C slave address of the chip (0x40)
|
||||
- interrupt-parent : a phandle pointing to the interrupt controller
|
||||
serving the interrupt for this chip
|
||||
- interrupts : interrupt specification for the gsl1680 interrupt
|
||||
- power-gpios : Specification for the pin connected to the gsl1680's
|
||||
shutdown input. This needs to be driven high to take the
|
||||
gsl1680 out of its low power state
|
||||
- touchscreen-size-x : See touchscreen.txt
|
||||
- touchscreen-size-y : See touchscreen.txt
|
||||
|
||||
Optional properties:
|
||||
- touchscreen-inverted-x : See touchscreen.txt
|
||||
- touchscreen-inverted-y : See touchscreen.txt
|
||||
- touchscreen-swapped-x-y : See touchscreen.txt
|
||||
- silead,max-fingers : maximum number of fingers the touchscreen can detect
|
||||
|
||||
Example:
|
||||
|
||||
i2c@00000000 {
|
||||
gsl1680: touchscreen@40 {
|
||||
compatible = "silead,gsl1680";
|
||||
reg = <0x40>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>;
|
||||
power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
|
||||
touchscreen-size-x = <480>;
|
||||
touchscreen-size-y = <800>;
|
||||
touchscreen-inverted-x;
|
||||
touchscreen-swapped-x-y;
|
||||
silead,max-fingers = <5>;
|
||||
};
|
||||
};
|
|
@ -0,0 +1,33 @@
|
|||
* SiS I2C Multiple Touch Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "sis,9200-ts"
|
||||
- reg: i2c slave address
|
||||
- interrupt-parent: the phandle for the interrupt controller
|
||||
(see interrupt binding [0])
|
||||
- interrupts: touch controller interrupt (see interrupt
|
||||
binding [0])
|
||||
|
||||
Optional properties:
|
||||
- pinctrl-names: should be "default" (see pinctrl binding [1]).
|
||||
- pinctrl-0: a phandle pointing to the pin settings for the
|
||||
device (see pinctrl binding [1]).
|
||||
- attn-gpios: the gpio pin used as attention line
|
||||
- reset-gpios: the gpio pin used to reset the controller
|
||||
- wakeup-source: touchscreen can be used as a wakeup source
|
||||
|
||||
[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
Example:
|
||||
|
||||
sis9255@5c {
|
||||
compatible = "sis,9200-ts";
|
||||
reg = <0x5c>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sis>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
|
||||
irq-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
|
||||
};
|
|
@ -21,6 +21,7 @@ Main node required properties:
|
|||
"arm,pl390"
|
||||
"arm,tc11mp-gic"
|
||||
"brcm,brahma-b15-gic"
|
||||
"nvidia,tegra210-agic"
|
||||
"qcom,msm-8660-qgic"
|
||||
"qcom,msm-qgic2"
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
|
@ -68,7 +69,7 @@ Optional
|
|||
"ic_clk" (for "arm,arm11mp-gic")
|
||||
"PERIPHCLKEN" (for "arm,cortex-a15-gic")
|
||||
"PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
|
||||
"clk" (for "arm,gic-400")
|
||||
"clk" (for "arm,gic-400" and "nvidia,tegra210")
|
||||
"gclk" (for "arm,pl390")
|
||||
|
||||
- power-domains : A phandle and PM domain specifier as defined by bindings of
|
||||
|
|
|
@ -0,0 +1,22 @@
|
|||
Aspeed Vectored Interrupt Controller
|
||||
|
||||
These bindings are for the Aspeed AST2400 interrupt controller register layout.
|
||||
The SoC has an legacy register layout, but this driver does not support that
|
||||
mode of operation.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "aspeed,ast2400-vic".
|
||||
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1.
|
||||
|
||||
Example:
|
||||
|
||||
vic: interrupt-controller@1e6c0080 {
|
||||
compatible = "aspeed,ast2400-vic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x1e6c0080 0x80>;
|
||||
};
|
|
@ -2,7 +2,7 @@ Cirrus Logic CLPS711X Interrupt Controller
|
|||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "cirrus,clps711x-intc".
|
||||
- compatible: Should be "cirrus,ep7209-intc".
|
||||
- reg: Specifies base physical address of the registers set.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
|
@ -34,7 +34,7 @@ ID Name Description
|
|||
|
||||
Example:
|
||||
intc: interrupt-controller {
|
||||
compatible = "cirrus,clps711x-intc";
|
||||
compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
|
||||
reg = <0x80000000 0x4000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
|
|
@ -9,6 +9,7 @@ Required properties:
|
|||
"mediatek,mt8135-sysirq"
|
||||
"mediatek,mt8127-sysirq"
|
||||
"mediatek,mt6795-sysirq"
|
||||
"mediatek,mt6755-sysirq"
|
||||
"mediatek,mt6592-sysirq"
|
||||
"mediatek,mt6589-sysirq"
|
||||
"mediatek,mt6582-sysirq"
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
* ARM SMMUv3 Architecture Implementation
|
||||
|
||||
The SMMUv3 architecture is a significant deparature from previous
|
||||
The SMMUv3 architecture is a significant departure from previous
|
||||
revisions, replacing the MMIO register interface with in-memory command
|
||||
and event queues and adding support for the ATS and PRI components of
|
||||
the PCIe specification.
|
||||
|
|
|
@ -1,7 +1,9 @@
|
|||
* Mediatek IOMMU Architecture Implementation
|
||||
|
||||
Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U) which
|
||||
uses the ARM Short-Descriptor translation table format for address translation.
|
||||
Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
|
||||
this M4U have two generations of HW architecture. Generation one uses flat
|
||||
pagetable, and only supports 4K size page mapping. Generation two uses the
|
||||
ARM Short-Descriptor translation table format for address translation.
|
||||
|
||||
About the M4U Hardware Block Diagram, please check below:
|
||||
|
||||
|
@ -36,7 +38,9 @@ in each larb. Take a example, There are many ports like MC, PP, VLD in the
|
|||
video decode local arbiter, all these ports are according to the video HW.
|
||||
|
||||
Required properties:
|
||||
- compatible : must be "mediatek,mt8173-m4u".
|
||||
- compatible : must be one of the following string:
|
||||
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
|
||||
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
|
||||
- reg : m4u register base and size.
|
||||
- interrupts : the interrupt of m4u.
|
||||
- clocks : must contain one entry for each clock-names.
|
||||
|
@ -46,7 +50,8 @@ Required properties:
|
|||
according to the local arbiter index, like larb0, larb1, larb2...
|
||||
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
|
||||
Specifies the mtk_m4u_id as defined in
|
||||
dt-binding/memory/mt8173-larb-port.h.
|
||||
dt-binding/memory/mt2701-larb-port.h for mt2701 and
|
||||
dt-binding/memory/mt8173-larb-port.h for mt8173
|
||||
|
||||
Example:
|
||||
iommu: iommu@10205000 {
|
||||
|
|
|
@ -0,0 +1,64 @@
|
|||
* QCOM IOMMU
|
||||
|
||||
The MSM IOMMU is an implementation compatible with the ARM VMSA short
|
||||
descriptor page tables. It provides address translation for bus masters outside
|
||||
of the CPU, each connected to the IOMMU through a port called micro-TLB.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must contain "qcom,apq8064-iommu".
|
||||
- reg: Base address and size of the IOMMU registers.
|
||||
- interrupts: Specifiers for the MMU fault interrupts. For instances that
|
||||
support secure mode two interrupts must be specified, for non-secure and
|
||||
secure mode, in that order. For instances that don't support secure mode a
|
||||
single interrupt must be specified.
|
||||
- #iommu-cells: The number of cells needed to specify the stream id. This
|
||||
is always 1.
|
||||
- qcom,ncb: The total number of context banks in the IOMMU.
|
||||
- clocks : List of clocks to be used during SMMU register access. See
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
for information about the format. For each clock specified
|
||||
here, there must be a corresponding entry in clock-names
|
||||
(see below).
|
||||
|
||||
- clock-names : List of clock names corresponding to the clocks specified in
|
||||
the "clocks" property (above).
|
||||
Should be "smmu_pclk" for specifying the interface clock
|
||||
required for iommu's register accesses.
|
||||
Should be "smmu_clk" for specifying the functional clock
|
||||
required by iommu for bus accesses.
|
||||
|
||||
Each bus master connected to an IOMMU must reference the IOMMU in its device
|
||||
node with the following property:
|
||||
|
||||
- iommus: A reference to the IOMMU in multiple cells. The first cell is a
|
||||
phandle to the IOMMU and the second cell is the stream id.
|
||||
A single master device can be connected to more than one iommu
|
||||
and multiple contexts in each of the iommu. So multiple entries
|
||||
are required to list all the iommus and the stream ids that the
|
||||
master is connected to.
|
||||
|
||||
Example: mdp iommu and its bus master
|
||||
|
||||
mdp_port0: iommu@7500000 {
|
||||
compatible = "qcom,apq8064-iommu";
|
||||
#iommu-cells = <1>;
|
||||
clock-names =
|
||||
"smmu_pclk",
|
||||
"smmu_clk";
|
||||
clocks =
|
||||
<&mmcc SMMU_AHB_CLK>,
|
||||
<&mmcc MDP_AXI_CLK>;
|
||||
reg = <0x07500000 0x100000>;
|
||||
interrupts =
|
||||
<GIC_SPI 63 0>,
|
||||
<GIC_SPI 64 0>;
|
||||
qcom,ncb = <2>;
|
||||
};
|
||||
|
||||
mdp: qcom,mdp@5100000 {
|
||||
compatible = "qcom,mdp";
|
||||
...
|
||||
iommus = <&mdp_port0 0
|
||||
&mdp_port0 2>;
|
||||
};
|
|
@ -13,6 +13,7 @@ Optional properties:
|
|||
- rom-addr: Register address of ROM area to be updated (u8)
|
||||
- rom-val: Register value to be updated (u8)
|
||||
- power-supply: Regulator which controls the 3V rail
|
||||
- enable-supply: Regulator which controls the EN/VDDIO input
|
||||
|
||||
Example:
|
||||
|
||||
|
@ -57,6 +58,7 @@ Example:
|
|||
backlight@2c {
|
||||
compatible = "ti,lp8557";
|
||||
reg = <0x2c>;
|
||||
enable-supply = <&backlight_vddio>;
|
||||
power-supply = <&backlight_vdd>;
|
||||
|
||||
dev-ctrl = /bits/ 8 <0x41>;
|
||||
|
|
|
@ -26,7 +26,9 @@ Optional properties for child nodes:
|
|||
"default-on" - LED will turn on (but for leds-gpio see "default-state"
|
||||
property in Documentation/devicetree/bindings/gpio/led.txt)
|
||||
"heartbeat" - LED "double" flashes at a load average based rate
|
||||
"ide-disk" - LED indicates disk activity
|
||||
"disk-activity" - LED indicates disk activity
|
||||
"ide-disk" - LED indicates IDE disk activity (deprecated),
|
||||
in new implementations use "disk-activity"
|
||||
"timer" - LED flashes at a fixed, configurable rate
|
||||
|
||||
- led-max-microamp : Maximum LED supply current in microamperes. This property
|
||||
|
|
|
@ -33,9 +33,9 @@ Examples:
|
|||
leds {
|
||||
compatible = "gpio-leds";
|
||||
hdd {
|
||||
label = "IDE Activity";
|
||||
label = "Disk Activity";
|
||||
gpios = <&mcu_pio 0 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "ide-disk";
|
||||
linux,default-trigger = "disk-activity";
|
||||
};
|
||||
|
||||
fault {
|
||||
|
|
|
@ -0,0 +1,39 @@
|
|||
*NXP - pca9532 PWM LED Driver
|
||||
|
||||
The PCA9532 family is SMBus I/O expander optimized for dimming LEDs.
|
||||
The PWM support 256 steps.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
"nxp,pca9530"
|
||||
"nxp,pca9531"
|
||||
"nxp,pca9532"
|
||||
"nxp,pca9533"
|
||||
- reg - I2C slave address
|
||||
|
||||
Each led is represented as a sub-node of the nxp,pca9530.
|
||||
|
||||
Optional sub-node properties:
|
||||
- label: see Documentation/devicetree/bindings/leds/common.txt
|
||||
- type: Output configuration, see dt-bindings/leds/leds-pca9532.h (default NONE)
|
||||
- linux,default-trigger: see Documentation/devicetree/bindings/leds/common.txt
|
||||
|
||||
Example:
|
||||
#include <dt-bindings/leds/leds-pca9532.h>
|
||||
|
||||
leds: pca9530@60 {
|
||||
compatible = "nxp,pca9530";
|
||||
reg = <0x60>;
|
||||
|
||||
red-power {
|
||||
label = "pca:red:power";
|
||||
type = <PCA9532_TYPE_LED>;
|
||||
};
|
||||
green-power {
|
||||
label = "pca:green:power";
|
||||
type = <PCA9532_TYPE_LED>;
|
||||
};
|
||||
};
|
||||
|
||||
For more product information please see the link below:
|
||||
http://nxp.com/documents/data_sheet/PCA9532.pdf
|
|
@ -0,0 +1,23 @@
|
|||
The PDC driver manages data transfer to and from various offload engines
|
||||
on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is
|
||||
one device tree entry per block.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "brcm,iproc-pdc-mbox".
|
||||
- reg: Should contain PDC registers location and length.
|
||||
- interrupts: Should contain the IRQ line for the PDC.
|
||||
- #mbox-cells: 1
|
||||
- brcm,rx-status-len: Length of metadata preceding received frames, in bytes.
|
||||
|
||||
Optional properties:
|
||||
- brcm,use-bcm-hdr: present if a BCM header precedes each frame.
|
||||
|
||||
Example:
|
||||
pdc0: iproc-pdc0@0x612c0000 {
|
||||
compatible = "brcm,iproc-pdc-mbox";
|
||||
reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>; /* one cell per mailbox channel */
|
||||
brcm,rx-status-len = <32>;
|
||||
brcm,use-bcm-hdr;
|
||||
};
|
|
@ -0,0 +1,59 @@
|
|||
Mediatek Video Codec
|
||||
|
||||
Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
|
||||
supports high resolution encoding functionalities.
|
||||
|
||||
Required properties:
|
||||
- compatible : "mediatek,mt8173-vcodec-enc" for encoder
|
||||
- reg : Physical base address of the video codec registers and length of
|
||||
memory mapped region.
|
||||
- interrupts : interrupt number to the cpu.
|
||||
- mediatek,larb : must contain the local arbiters in the current Socs.
|
||||
- clocks : list of clock specifiers, corresponding to entries in
|
||||
the clock-names property.
|
||||
- clock-names: encoder must contain "venc_sel_src", "venc_sel",
|
||||
- "venc_lt_sel_src", "venc_lt_sel".
|
||||
- iommus : should point to the respective IOMMU block with master port as
|
||||
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
|
||||
for details.
|
||||
- mediatek,vpu : the node of video processor unit
|
||||
|
||||
Example:
|
||||
vcodec_enc: vcodec@0x18002000 {
|
||||
compatible = "mediatek,mt8173-vcodec-enc";
|
||||
reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
|
||||
<0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
|
||||
mediatek,larb = <&larb3>,
|
||||
<&larb5>;
|
||||
iommus = <&iommu M4U_PORT_VENC_RCPU>,
|
||||
<&iommu M4U_PORT_VENC_REC>,
|
||||
<&iommu M4U_PORT_VENC_BSDMA>,
|
||||
<&iommu M4U_PORT_VENC_SV_COMV>,
|
||||
<&iommu M4U_PORT_VENC_RD_COMV>,
|
||||
<&iommu M4U_PORT_VENC_CUR_LUMA>,
|
||||
<&iommu M4U_PORT_VENC_CUR_CHROMA>,
|
||||
<&iommu M4U_PORT_VENC_REF_LUMA>,
|
||||
<&iommu M4U_PORT_VENC_REF_CHROMA>,
|
||||
<&iommu M4U_PORT_VENC_NBM_RDMA>,
|
||||
<&iommu M4U_PORT_VENC_NBM_WDMA>,
|
||||
<&iommu M4U_PORT_VENC_RCPU_SET2>,
|
||||
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
|
||||
<&iommu M4U_PORT_VENC_BSDMA_SET2>,
|
||||
<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
|
||||
<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
|
||||
<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
|
||||
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
|
||||
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
|
||||
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
|
||||
mediatek,vpu = <&vpu>;
|
||||
clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
|
||||
<&topckgen CLK_TOP_VENC_SEL>,
|
||||
<&topckgen CLK_TOP_UNIVPLL1_D2>,
|
||||
<&topckgen CLK_TOP_VENC_LT_SEL>;
|
||||
clock-names = "venc_sel_src",
|
||||
"venc_sel",
|
||||
"venc_lt_sel_src",
|
||||
"venc_lt_sel";
|
||||
};
|
|
@ -0,0 +1,31 @@
|
|||
* Mediatek Video Processor Unit
|
||||
|
||||
Video Processor Unit is a HW video controller. It controls HW Codec including
|
||||
H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,mt8173-vpu"
|
||||
- reg: Must contain an entry for each entry in reg-names.
|
||||
- reg-names: Must include the following entries:
|
||||
"tcm": tcm base
|
||||
"cfg_reg": Main configuration registers base
|
||||
- interrupts: interrupt number to the cpu.
|
||||
- clocks : clock name from clock manager
|
||||
- clock-names: must be main. It is the main clock of VPU
|
||||
|
||||
Optional properties:
|
||||
- memory-region: phandle to a node describing memory (see
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
|
||||
to be used for VPU extended memory; if not present, VPU may be located
|
||||
anywhere in the memory
|
||||
|
||||
Example:
|
||||
vpu: vpu@10020000 {
|
||||
compatible = "mediatek,mt8173-vpu";
|
||||
reg = <0 0x10020000 0 0x30000>,
|
||||
<0 0x10050000 0 0x100>;
|
||||
reg-names = "tcm", "cfg_reg";
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen TOP_SCP_SEL>;
|
||||
clock-names = "main";
|
||||
};
|
|
@ -0,0 +1,20 @@
|
|||
Device-Tree bindings for LIRC TX driver for Nokia N900(RX51)
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nokia,n900-ir".
|
||||
- pwms: specifies PWM used for IR signal transmission.
|
||||
|
||||
Example node:
|
||||
|
||||
pwm9: dmtimer-pwm@9 {
|
||||
compatible = "ti,omap-dmtimer-pwm";
|
||||
ti,timers = <&timer9>;
|
||||
ti,clock-source = <0x00>; /* timer_sys_ck */
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
ir: n900-ir {
|
||||
compatible = "nokia,n900-ir";
|
||||
|
||||
pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
|
||||
};
|
|
@ -0,0 +1,32 @@
|
|||
Renesas R-Car Frame Compression Processor (FCP)
|
||||
-----------------------------------------------
|
||||
|
||||
The FCP is a companion module of video processing modules in the Renesas R-Car
|
||||
Gen3 SoCs. It provides data compression and decompression, data caching, and
|
||||
conversion of AXI transactions in order to reduce the memory bandwidth.
|
||||
|
||||
There are three types of FCP: FCP for Codec (FCPC), FCP for VSP (FCPV) and FCP
|
||||
for FDP (FCPF). Their configuration and behaviour depend on the module they
|
||||
are paired with. These DT bindings currently support the FCPV only.
|
||||
|
||||
- compatible: Must be one or more of the following
|
||||
|
||||
- "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP'
|
||||
- "renesas,fcpv" for generic compatible 'FCP for VSP'
|
||||
|
||||
When compatible with the generic version, nodes must list the
|
||||
SoC-specific version corresponding to the platform first, followed by the
|
||||
family-specific and/or generic versions.
|
||||
|
||||
- reg: the register base and size for the device registers
|
||||
- clocks: Reference to the functional clock
|
||||
|
||||
|
||||
Device node example
|
||||
-------------------
|
||||
|
||||
fcpvd1: fcp@fea2f000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfea2f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 602>;
|
||||
};
|
|
@ -14,6 +14,11 @@ Required properties:
|
|||
- interrupts: VSP interrupt specifier.
|
||||
- clocks: A phandle + clock-specifier pair for the VSP functional clock.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- renesas,fcp: A phandle referencing the FCP that handles memory accesses
|
||||
for the VSP. Not needed on Gen2, mandatory on Gen3.
|
||||
|
||||
|
||||
Example: R8A7790 (R-Car H2) VSP1-S node
|
||||
|
||||
|
|
|
@ -0,0 +1,31 @@
|
|||
* Samsung HDMI CEC driver
|
||||
|
||||
The HDMI CEC module is present is Samsung SoCs and its purpose is to
|
||||
handle communication between HDMI connected devices over the CEC bus.
|
||||
|
||||
Required properties:
|
||||
- compatible : value should be following
|
||||
"samsung,s5p-cec"
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
||||
- interrupts : HDMI CEC interrupt number to the CPU.
|
||||
- clocks : from common clock binding: handle to HDMI CEC clock.
|
||||
- clock-names : from common clock binding: must contain "hdmicec",
|
||||
corresponding to entry in the clocks property.
|
||||
- samsung,syscon-phandle - phandle to the PMU system controller
|
||||
|
||||
Example:
|
||||
|
||||
hdmicec: cec@100B0000 {
|
||||
compatible = "samsung,s5p-cec";
|
||||
reg = <0x100B0000 0x200>;
|
||||
interrupts = <0 114 0>;
|
||||
clocks = <&clock CLK_HDMI_CEC>;
|
||||
clock-names = "hdmicec";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_cec>;
|
||||
status = "okay";
|
||||
};
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue