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Merge branch 'for-next/omap'

This commit is contained in:
Sascha Hauer 2013-01-09 10:29:08 +01:00
parent fca2d79470 04cb446c9a
commit db31ccf293
65 changed files with 2868 additions and 553 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Makefile
View File

@ -103,6 +103,7 @@ board-$(CONFIG_MACH_NOMADIK_8815NHK) := nhk8815
board-$(CONFIG_MACH_NXDB500) := netx
board-$(CONFIG_MACH_OMAP343xSDP) := omap343xdsp
board-$(CONFIG_MACH_BEAGLE) := beagle
board-$(CONFIG_MACH_BEAGLEBONE) := beaglebone
board-$(CONFIG_MACH_OMAP3EVM) := omap3evm
board-$(CONFIG_MACH_PANDA) := panda
board-$(CONFIG_MACH_ARCHOSG9) := archosg9
@ -114,6 +115,7 @@ board-$(CONFIG_MACH_PCM027) := pcm027
board-$(CONFIG_MACH_PCM037) := pcm037
board-$(CONFIG_MACH_PCM038) := pcm038
board-$(CONFIG_MACH_PCM043) := pcm043
board-$(CONFIG_MACH_PCM051) := pcm051
board-$(CONFIG_MACH_PM9261) := pm9261
board-$(CONFIG_MACH_PM9263) := pm9263
board-$(CONFIG_MACH_PM9G45) := pm9g45

21
arch/arm/boards/archosg9/board.c
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@ -15,15 +15,12 @@
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/silicon.h>
#include <mach/omap4-silicon.h>
#include <mach/omap4-devices.h>
#include <sizes.h>
#include <i2c/i2c.h>
#include <gpio.h>
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
static int archosg9_console_init(void){
if (IS_ENABLED(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT))
add_generic_device("serial_omap4_usbboot", DEVICE_ID_DYNAMIC
@ -31,15 +28,14 @@ static int archosg9_console_init(void){
if (IS_ENABLED(CONFIG_DRIVER_SERIAL_NS16550)) {
gpio_direction_output(41, 0); /* gps_disable */
gpio_direction_output(34, 1); /* 1v8_pwron */
add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP44XX_UART1_BASE, 1024,
IORESOURCE_MEM_8BIT, &serial_plat);
omap44xx_add_uart1();
}
return 0;
}
console_initcall(archosg9_console_init);
static int archosg9_mem_init(void){
arm_add_mem_device("ram0", 0x80000000, SZ_1G);
omap_add_ram0(SZ_1G);
return 0;
}
mem_initcall(archosg9_mem_init);
@ -50,12 +46,9 @@ static struct i2c_board_info i2c_devices[] = {
static int archosg9_devices_init(void){
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
add_generic_device("i2c-omap" , DEVICE_ID_DYNAMIC, NULL,
OMAP44XX_I2C1_BASE, 0x100, IORESOURCE_MEM, NULL);
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL,
OMAP44XX_MMC1_BASE, SZ_4K, IORESOURCE_MEM, NULL);
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL,
OMAP44XX_MMC2_BASE, SZ_4K, IORESOURCE_MEM, NULL);
omap44xx_add_i2c1(NULL);
omap44xx_add_mmc1(NULL);
omap44xx_add_mmc2(NULL);
armlinux_set_bootparams((void *)0x80000100);
/*

51
arch/arm/boards/beagle/board.c
View File

@ -55,7 +55,7 @@
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@ -64,6 +64,7 @@
#include <mach/gpmc.h>
#include <mach/gpmc_nand.h>
#include <mach/ehci.h>
#include <mach/omap3-devices.h>
#include <i2c/i2c.h>
#include <linux/err.h>
#include <usb/ehci.h>
@ -80,47 +81,47 @@ static void sdrc_init(void)
{
/* SDRAM software reset */
/* No idle ack and RESET enable */
writel(0x1A, SDRC_REG(SYSCONFIG));
writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
sdelay(100);
/* No idle ack and RESET disable */
writel(0x18, SDRC_REG(SYSCONFIG));
writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
/* SDRC Sharing register */
/* 32-bit SDRAM on data lane [31:0] - CS0 */
/* pin tri-stated = 1 */
writel(0x00000100, SDRC_REG(SHARING));
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
/* ----- SDRC Registers Configuration --------- */
/* SDRC_MCFG0 register */
writel(0x02584099, SDRC_REG(MCFG_0));
writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
/* SDRC_RFR_CTRL0 register */
writel(0x54601, SDRC_REG(RFR_CTRL_0));
writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
/* SDRC_ACTIM_CTRLA0 register */
writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
/* SDRC_ACTIM_CTRLB0 register */
writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
/* Disble Power Down of CKE due to 1 CKE on combo part */
writel(0x00000081, SDRC_REG(POWER));
writel(0x00000081, OMAP3_SDRC_REG(POWER));
/* SDRC_MANUAL command register */
/* NOP command */
writel(0x00000000, SDRC_REG(MANUAL_0));
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
/* Precharge command */
writel(0x00000001, SDRC_REG(MANUAL_0));
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, SDRC_REG(MANUAL_0));
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, SDRC_REG(MANUAL_0));
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* SDRC MR0 register Burst length=4 */
writel(0x00000032, SDRC_REG(MR_0));
writel(0x00000032, OMAP3_SDRC_REG(MR_0));
/* SDRC DLLA control register */
writel(0x0000000A, SDRC_REG(DLLA_CTRL));
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
return;
}
@ -234,11 +235,6 @@ pure_initcall(beagle_board_init);
#ifdef CONFIG_DRIVER_SERIAL_NS16550
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
/**
* @brief UART serial port initialization - remember to enable COM clocks in
* arch
@ -247,9 +243,7 @@ static struct NS16550_plat serial_plat = {
*/
static int beagle_console_init(void)
{
/* Register the serial port */
add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
&serial_plat);
omap3_add_uart3();
return 0;
}
@ -286,7 +280,7 @@ static struct gpmc_nand_platform_data nand_plat = {
static int beagle_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
omap_add_ram0(SZ_128M);
return 0;
}
@ -295,13 +289,11 @@ mem_initcall(beagle_mem_init);
static int beagle_devices_init(void)
{
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC, NULL, OMAP_I2C1_BASE, SZ_4K,
IORESOURCE_MEM, NULL);
omap3_add_i2c1(NULL);
#ifdef CONFIG_USB_EHCI_OMAP
if (ehci_omap_init(&omap_ehci_pdata) >= 0)
add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP_EHCI_BASE,
OMAP_EHCI_BASE + 0x10, &ehci_pdata);
omap3_add_ehci(&ehci_pdata);
#endif /* CONFIG_USB_EHCI_OMAP */
#ifdef CONFIG_OMAP_GPMC
/* WP is made high and WAIT1 active Low */
@ -309,8 +301,7 @@ static int beagle_devices_init(void)
#endif
omap_add_gpmc_nand_device(&nand_plat);
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K,
IORESOURCE_MEM, NULL);
omap3_add_mmc1(NULL);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP3_BEAGLE);

1
arch/arm/boards/beaglebone/Makefile Normal file
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@ -0,0 +1 @@
obj-y += board.o

357
arch/arm/boards/beaglebone/board.c Normal file
View File

@ -0,0 +1,357 @@
/*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
* Raghavendra KH <r-khandenahally@ti.com>
*
* Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/**
* @file
* @brief BeagleBone Specific Board Initialization routines
*/
#include <common.h>
#include <console.h>
#include <init.h>
#include <driver.h>
#include <fs.h>
#include <linux/stat.h>
#include <environment.h>
#include <sizes.h>
#include <io.h>
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/am33xx-silicon.h>
#include <mach/am33xx-clock.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
#include <mach/gpmc.h>
#include <mach/ehci.h>
#include <i2c/i2c.h>
#include <linux/err.h>
#include <usb/ehci.h>
#include <mach/xload.h>
#include <mach/am33xx-devices.h>
#include <mach/am33xx-mux.h>
#include <mach/wdt.h>
/* UART Defines */
#define UART_SYSCFG_OFFSET (0x54)
#define UART_SYSSTS_OFFSET (0x58)
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
/* AM335X EMIF Register values */
#define EMIF_SDMGT 0x80000000
#define EMIF_SDRAM 0x00004650
#define EMIF_PHYCFG 0x2
#define DDR_PHY_RESET (0x1 << 10)
#define DDR_FUNCTIONAL_MODE_EN 0x1
#define DDR_PHY_READY (0x1 << 2)
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_LOCK_EN (0x1 << 4)
#define VTP_CTRL_START_EN (0x1)
#define DDR2_RATIO 0x80 /* for mDDR */
#define CMD_FORCE 0x00 /* common #def */
#define CMD_DELAY 0x00
#define EMIF_READ_LATENCY 0x05
#define EMIF_TIM1 0x0666B3D6
#define EMIF_TIM2 0x143731DA
#define EMIF_TIM3 0x00000347
#define EMIF_SDCFG 0x43805332
#define EMIF_SDREF 0x0000081a
#define DDR2_DLL_LOCK_DIFF 0x0
#define DDR2_RD_DQS 0x12
#define DDR2_PHY_FIFO_WE 0x80
#define DDR2_INVERT_CLKOUT 0x00
#define DDR2_WR_DQS 0x00
#define DDR2_PHY_WRLVL 0x00
#define DDR2_PHY_GATELVL 0x00
#define DDR2_PHY_WR_DATA 0x40
#define PHY_RANK0_DELAY 0x01
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_IOCTRL_VALUE 0x18B
static void beaglebone_data_macro_config(int dataMacroNum)
{
u32 BaseAddrOffset = 0x00;;
if (dataMacroNum == 1)
BaseAddrOffset = 0xA4;
__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
__raw_writel(DDR2_RD_DQS>>2,
(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
__raw_writel(DDR2_WR_DQS>>2,
(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
__raw_writel(DDR2_PHY_WRLVL>>2,
(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
__raw_writel(DDR2_PHY_GATELVL>>2,
(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
__raw_writel(DDR2_PHY_FIFO_WE>>2,
(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
__raw_writel(DDR2_PHY_WR_DATA>>2,
(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
__raw_writel(PHY_DLL_LOCK_DIFF,
(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
}
static void beaglebone_cmd_macro_config(void)
{
__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
}
static void beaglebone_config_vtp(void)
{
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
AM33XX_VTP0_CTRL_REG);
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
AM33XX_VTP0_CTRL_REG);
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
AM33XX_VTP0_CTRL_REG);
/* Poll for READY */
while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
}
static void beaglebone_config_emif_ddr2(void)
{
u32 i;
/*Program EMIF0 CFG Registers*/
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
for (i = 0; i < 5000; i++) {
}
/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
}
static void beaglebone_config_ddr(void)
{
enable_ddr_clocks();
beaglebone_config_vtp();
beaglebone_cmd_macro_config();
beaglebone_data_macro_config(0);
beaglebone_data_macro_config(1);
__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
beaglebone_config_emif_ddr2();
}
/*
* early system init of muxing and clocks.
*/
void beaglebone_sram_init(void)
{
u32 regVal, uart_base;
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
beaglebone_config_ddr();
/* UART softreset */
uart_base = AM33XX_UART0_BASE;
regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
regVal |= UART_RESET;
__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
/* Disable smart idle */
regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
regVal |= UART_SMART_IDLE_EN;
__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
}
/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
static int beaglebone_board_init(void)
{
int in_sdram = running_in_sdram();
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
/* Dont reconfigure SDRAM while running in SDRAM! */
if (!in_sdram)
beaglebone_sram_init();
/* Enable pin mux */
enable_uart0_pin_mux();
return 0;
}
pure_initcall(beaglebone_board_init);
/******************** Board Run Time *******************/
#ifdef CONFIG_DRIVER_SERIAL_NS16550
/**
* @brief UART serial port initialization - remember to enable COM clocks in
* arch
*
* @return result of device registration
*/
static int beaglebone_console_init(void)
{
am33xx_add_uart0();
return 0;
}
console_initcall(beaglebone_console_init);
#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
static int beaglebone_mem_init(void)
{
omap_add_ram0(256 * 1024 * 1024);
return 0;
}
mem_initcall(beaglebone_mem_init);
static int beaglebone_devices_init(void)
{
am33xx_add_mmc0(NULL);
enable_i2c0_pin_mux();
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_BEAGLEBONE);
return 0;
}
device_initcall(beaglebone_devices_init);
#ifdef CONFIG_DEFAULT_ENVIRONMENT
static int beaglebone_env_init(void)
{
struct stat s;
char *diskdev = "/dev/disk0.0";
int ret;
ret = stat(diskdev, &s);
if (ret) {
printf("device %s not found. Using default environment\n", diskdev);
return 0;
}
mkdir ("/boot", 0666);
ret = mount(diskdev, "fat", "/boot");
if (ret) {
printf("failed to mount %s\n", diskdev);
return 0;
}
if (IS_ENABLED(CONFIG_OMAP_BUILD_IFT))
default_environment_path = "/dev/defaultenv";
else
default_environment_path = "/boot/barebox.env";
return 0;
}
late_initcall(beaglebone_env_init);
#endif

17
arch/arm/boards/beaglebone/config.h Normal file
View File

@ -0,0 +1,17 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _CONFIG_H_
# define _CONFIG_H_
#endif /* _CONFIG_H_ */

11
arch/arm/boards/beaglebone/env/boot/sd vendored Normal file
View File

@ -0,0 +1,11 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "kernel & rootfs on SD card"
exit
fi
global.bootm.image=/boot/uImage
global.bootm.oftree=/boot/oftree
#global.bootm.initrd=<path to initrd>
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"

21
arch/arm/boards/beaglebone/env/config vendored Normal file
View File

@ -0,0 +1,21 @@
#!/bin/sh
# change network settings in /env/network/eth0
# change mtd partition settings and automountpoints in /env/init/*
global.hostname=beaglebone
# set to false if you do not want to have colors
global.allow_color=true
# user (used for network filenames)
global.user=none
# timeout in seconds before the default boot entry is started
global.autoboot_timeout=3
# default boot entry (one of /env/boot/*)
global.boot.default=sd
# base bootargs
global.linux.bootargs.base="console=ttyO0,115200n8"

47
arch/arm/boards/omap343xdsp/board.c
View File

@ -48,7 +48,8 @@
#include <io.h>
#include <ns16550.h>
#include <asm/armlinux.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/omap3-devices.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@ -93,54 +94,54 @@ pure_initcall(sdp343x_board_init);
static void sdrc_init(void)
{
/* Issue SDRC Soft reset */
writel(0x12, SDRC_REG(SYSCONFIG));
writel(0x12, OMAP3_SDRC_REG(SYSCONFIG));
/* Wait until Reset complete */
while ((readl(SDRC_REG(STATUS)) & 0x1) == 0);
while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0);
/* SDRC to normal mode */
writel(0x10, SDRC_REG(SYSCONFIG));
writel(0x10, OMAP3_SDRC_REG(SYSCONFIG));
/* SDRC Sharing register */
/* 32-bit SDRAM on data lane [31:0] - CS0 */
/* pin tri-stated = 1 */
writel(0x00000100, SDRC_REG(SHARING));
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
/* ----- SDRC_REG(CS0 Configuration --------- */
/* SDRC_REG(MCFG0 register */
writel(0x02584019, SDRC_REG(MCFG_0));
writel(0x02584019, OMAP3_SDRC_REG(MCFG_0));
/* SDRC_REG(RFR_CTRL0 register */
writel(0x0003DE01, SDRC_REG(RFR_CTRL_0));
writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0));
/* SDRC_REG(ACTIM_CTRLA0 register */
writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0));
writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
/* SDRC_REG(ACTIM_CTRLB0 register */
writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0));
writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
/* Disble Power Down of CKE cuz of 1 CKE on combo part */
writel(0x00000081, SDRC_REG(POWER));
writel(0x00000081, OMAP3_SDRC_REG(POWER));
/* SDRC_REG(Manual command register */
/* NOP command */
writel(0x00000000, SDRC_REG(MANUAL_0));
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
/* Precharge command */
writel(0x00000001, SDRC_REG(MANUAL_0));
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, SDRC_REG(MANUAL_0));
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, SDRC_REG(MANUAL_0));
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* SDRC MR0 register */
/* CAS latency = 3 */
/* Write Burst = Read Burst */
/* Serial Mode */
writel(0x00000032, SDRC_REG(MR_0)); /* Burst length =4 */
writel(0x00000032, OMAP3_SDRC_REG(MR_0)); /* Burst length =4 */
/* SDRC DLLA control register */
/* Enable DLL A */
writel(0x0000000A, SDRC_REG(DLLA_CTRL));
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
/* wait until DLL is locked */
while ((readl(SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
return;
}
@ -602,12 +603,6 @@ static void mux_config(void)
/*-----------------------CONSOLE Devices -----------------------------------*/
#ifdef CONFIG_DRIVER_SERIAL_NS16550
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
/**
* @brief UART serial port initialization - remember to enable COM clocks in arch
*
@ -615,9 +610,7 @@ static struct NS16550_plat serial_plat = {
*/
static int sdp3430_console_init(void)
{
/* Register the serial port */
add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
&serial_plat);
omap3_add_uart3();
return 0;
}
@ -627,7 +620,7 @@ console_initcall(sdp3430_console_init);
static int sdp3430_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
omap_add_ram0(128 * 1024 * 1024);
return 0;
}

55
arch/arm/boards/omap3evm/board.c
View File

@ -46,7 +46,7 @@
#include <sizes.h>
#include <ns16550.h>
#include <asm/armlinux.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@ -55,6 +55,7 @@
#include <mach/gpmc.h>
#include <errno.h>
#include <generated/mach-types.h>
#include <mach/omap3-devices.h>
/*
@ -70,47 +71,47 @@ static void sdrc_init(void)
{
/* SDRAM software reset */
/* No idle ack and RESET enable */
writel(0x1A, SDRC_REG(SYSCONFIG));
writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
sdelay(100);
/* No idle ack and RESET disable */
writel(0x18, SDRC_REG(SYSCONFIG));
writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
/* SDRC Sharing register */
/* 32-bit SDRAM on data lane [31:0] - CS0 */
/* pin tri-stated = 1 */
writel(0x00000100, SDRC_REG(SHARING));
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
/* ----- SDRC Registers Configuration --------- */
/* SDRC_MCFG0 register */
writel(0x02584099, SDRC_REG(MCFG_0));
writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
/* SDRC_RFR_CTRL0 register */
writel(0x54601, SDRC_REG(RFR_CTRL_0));
writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
/* SDRC_ACTIM_CTRLA0 register */
writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
/* SDRC_ACTIM_CTRLB0 register */
writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
/* Disble Power Down of CKE due to 1 CKE on combo part */
writel(0x00000081, SDRC_REG(POWER));
writel(0x00000081, OMAP3_SDRC_REG(POWER));
/* SDRC_MANUAL command register */
/* NOP command */
writel(0x00000000, SDRC_REG(MANUAL_0));
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
/* Precharge command */
writel(0x00000001, SDRC_REG(MANUAL_0));
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, SDRC_REG(MANUAL_0));
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* Auto-refresh command */
writel(0x00000002, SDRC_REG(MANUAL_0));
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
/* SDRC MR0 register Burst length=4 */
writel(0x00000032, SDRC_REG(MR_0));
writel(0x00000032, OMAP3_SDRC_REG(MR_0));
/* SDRC DLLA control register */
writel(0x0000000A, SDRC_REG(DLLA_CTRL));
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
return;
}
@ -212,11 +213,6 @@ pure_initcall(omap3_evm_board_init);
#ifdef CONFIG_DRIVER_SERIAL_NS16550
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
/**
* @brief Initialize the serial port to be used as console.
*
@ -224,13 +220,10 @@ static struct NS16550_plat serial_plat = {
*/
static int omap3evm_init_console(void)
{
add_ns16550_device(DEVICE_ID_DYNAMIC,
#if defined(CONFIG_OMAP3EVM_UART1)
OMAP_UART1_BASE,
#elif defined(CONFIG_OMAP3EVM_UART3)
OMAP_UART3_BASE,
#endif
1024, IORESOURCE_MEM_8BIT, &serial_plat);
if (IS_ENABLED(CONFIG_OMAP3EVM_UART1))
omap3_add_uart1();
if (IS_ENABLED(CONFIG_OMAP3EVM_UART3))
omap3_add_uart3();
return 0;
}
@ -239,7 +232,7 @@ console_initcall(omap3evm_init_console);
static int omap3evm_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
omap_add_ram0(SZ_128M);
return 0;
}
@ -253,10 +246,8 @@ static int omap3evm_init_devices(void)
*/
gpmc_generic_init(0x10);
#endif
#ifdef CONFIG_MCI_OMAP_HSMMC
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K,
IORESOURCE_MEM, NULL);
#endif
omap3_add_mmc1(NULL);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP3EVM);

25
arch/arm/boards/panda/board.c
View File

@ -8,7 +8,8 @@
#include <asm/armlinux.h>
#include <linux/stat.h>
#include <generated/mach-types.h>
#include <mach/silicon.h>
#include <mach/omap4-silicon.h>
#include <mach/omap4-devices.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@ -33,16 +34,9 @@ static int board_revision;
#define GPIO_BOARD_ID1 101
#define GPIO_BOARD_ID2 171
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
static int panda_console_init(void)
{
/* Register the serial port */
add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP44XX_UART3_BASE, 1024,
IORESOURCE_MEM_8BIT, &serial_plat);
omap44xx_add_uart3();
return 0;
}
@ -50,7 +44,7 @@ console_initcall(panda_console_init);
static int panda_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, SZ_1G);
omap_add_ram0(SZ_1G);
return 0;
}
@ -92,8 +86,7 @@ static void panda_ehci_init(void)
/* enable power to hub */
gpio_set_value(GPIO_HUB_POWER, 1);
add_usb_ehci_device(DEVICE_ID_DYNAMIC, 0x4a064c00,
0x4a064c00 + 0x10, &ehci_pdata);
omap44xx_add_ehci(&ehci_pdata);
}
#else
static void panda_ehci_init(void)
@ -160,13 +153,9 @@ static int panda_devices_init(void)
}
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC,
NULL, 0x48070000, 0x1000,
IORESOURCE_MEM, NULL);
omap44xx_add_i2c1(NULL);
omap44xx_add_mmc1(NULL);
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x4809C100, SZ_4K,
IORESOURCE_MEM, NULL);
panda_ehci_init();
panda_led_init();

24
arch/arm/boards/pcm049/board.c
View File

@ -22,7 +22,8 @@
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/silicon.h>
#include <mach/omap4-silicon.h>
#include <mach/omap4-devices.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@ -38,16 +39,9 @@
#include <mach/xload.h>
#include <i2c/i2c.h>
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
static int pcm049_console_init(void)
{
/* Register the serial port */
add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP44XX_UART3_BASE, 1024,
IORESOURCE_MEM_8BIT, &serial_plat);
omap44xx_add_uart3();
return 0;
}
@ -55,10 +49,9 @@ console_initcall(pcm049_console_init);
static int pcm049_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, SZ_512M);
omap_add_ram0(SZ_512M);
add_mem_device("sram0", 0x40300000, 48 * 1024,
IORESOURCE_MEM_WRITEABLE);
omap44xx_add_sram0();
return 0;
}
mem_initcall(pcm049_mem_init);
@ -99,11 +92,8 @@ static struct gpmc_nand_platform_data nand_plat = {
static int pcm049_devices_init(void)
{
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC, NULL, 0x48070000, 0x1000,
IORESOURCE_MEM, NULL);
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x4809C100, SZ_4K,
IORESOURCE_MEM, NULL);
omap44xx_add_i2c1(NULL);
omap44xx_add_mmc1(NULL);
gpmc_generic_init(0x10);

1
arch/arm/boards/pcm051/Makefile Normal file
View File

@ -0,0 +1 @@
obj-y += board.o

64
arch/arm/boards/pcm051/board.c Normal file
View File

@ -0,0 +1,64 @@
/*
* pcm051 - phyCORE-AM335x Board Initalization Code
*
* Copyright (C) 2012 Teresa Gámez, Phytec Messtechnik GmbH
*
* Based on arch/arm/boards/omap/board-beagle.c
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <init.h>
#include <sizes.h>
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/am33xx-devices.h>
#include <mach/am33xx-mux.h>
#include <mach/am33xx-silicon.h>
/**
* @brief UART serial port initialization
* arch
*
* @return result of device registration
*/
static int pcm051_console_init(void)
{
/* Register the serial port */
am33xx_add_uart0();
return 0;
}
console_initcall(pcm051_console_init);
static int pcm051_mem_init(void)
{
omap_add_ram0(SZ_512M);
return 0;
}
mem_initcall(pcm051_mem_init);
static int pcm051_devices_init(void)
{
enable_mmc0_pin_mux();
am33xx_add_mmc0(NULL);
armlinux_set_bootparams((void *)(AM33XX_DRAM_ADDR_SPACE_START + 0x100));
armlinux_set_architecture(MACH_TYPE_PCM051);
return 0;
}
device_initcall(pcm051_devices_init);

21
arch/arm/boards/pcm051/config.h Normal file
View File

@ -0,0 +1,21 @@
/**
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#endif /* __CONFIG_H */

10
arch/arm/boards/pcm051/env/boot/sd vendored Normal file
View File

@ -0,0 +1,10 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "kernel & rootfs on SD card"
exit
fi
global.bootm.image=/boot/uImage
global.bootm.oftree=/boot/oftree
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"

22
arch/arm/boards/pcm051/env/config vendored Normal file
View File

@ -0,0 +1,22 @@
#!/bin/sh
# change network settings in /env/network/eth0
# change mtd partition settings and automountpoints in /env/init/*
global.hostname=pcm051
# set to false if you do not want to have colors
global.allow_color=true
# user (used for network filenames)
global.user=none
# timeout in seconds before the default boot entry is started
global.autoboot_timeout=3
# default boot entry (one of /env/boot/*)
global.boot.default=sd
# base bootargs
global.linux.bootargs.base="console=ttyO0,115200n8"

59
arch/arm/boards/phycard-a-l1/pca-a-l1.c
View File

@ -58,9 +58,10 @@
#include <mach/xload.h>
#include <mach/omap3-mux.h>
#include <mach/sdrc.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
#include <mach/omap3-devices.h>
#define SMC911X_BASE 0x2c000000
@ -102,16 +103,16 @@ struct sdrc_config {
void init_sdram_ddr(void)
{
/* reset sdrc controller */
writel(SOFTRESET, SDRC_REG(SYSCONFIG));
wait_on_value(1<<0, 1<<0, SDRC_REG(STATUS), 12000000);
writel(0, SDRC_REG(SYSCONFIG));
writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG));
wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000);
writel(0, OMAP3_SDRC_REG(SYSCONFIG));
/* setup sdrc to ball mux */
writel(SDP_SDRC_SHARING, SDRC_REG(SHARING));
writel(SDP_SDRC_POWER_POP, SDRC_REG(POWER));
writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING));
writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER));
/* set up dll */
writel(SDP_SDRC_DLLAB_CTRL, SDRC_REG(DLLA_CTRL));
writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL));
sdelay(0x2000); /* give time to lock */
}
@ -121,21 +122,21 @@ void init_sdram_ddr(void)
void config_sdram_ddr(u8 cs, u8 cfg)
{
writel(sdrc_config[cfg].mcfg, SDRC_REG(MCFG_0) + (0x30 * cs));
writel(sdrc_config[cfg].actim_ctrla, SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
writel(sdrc_config[cfg].actim_ctrlb, SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
writel(sdrc_config[cfg].rfr_ctrl, SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs));
writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
writel(CMD_NOP, SDRC_REG(MANUAL_0) + (0x30 * cs));
writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
sdelay(5000);
writel(CMD_PRECHARGE, SDRC_REG(MANUAL_0) + (0x30 * cs));
writel(CMD_AUTOREFRESH, SDRC_REG(MANUAL_0) + (0x30 * cs));
writel(CMD_AUTOREFRESH, SDRC_REG(MANUAL_0) + (0x30 * cs));
writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
/* set mr0 */
writel(sdrc_config[cfg].mr, SDRC_REG(MR_0) + (0x30 * cs));
writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs));
sdelay(2000);
}
@ -170,7 +171,7 @@ static void pcaal1_sdrc_init(void)
if (test1 == 0) {
init_sdram_ddr();
writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), SDRC_REG(MCFG_1));
writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1));
/* 1 x 256MByte */
if (test0 == SZ_256M)
@ -178,7 +179,7 @@ static void pcaal1_sdrc_init(void)
if (cfg != -1) {
config_sdram_ddr(0, cfg);
writel(sdrc_config[(uchar) cfg].cs_cfg, SDRC_REG(CS_CFG));
writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
}
return;
}
@ -193,7 +194,7 @@ static void pcaal1_sdrc_init(void)
if (cfg != -1) {
init_sdram_ddr();
writel(sdrc_config[(uchar) cfg].cs_cfg, SDRC_REG(CS_CFG));
writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
config_sdram_ddr(0, cfg);
config_sdram_ddr(1, cfg);
}
@ -307,10 +308,6 @@ pure_initcall(pcaal1_board_init);
/*
* Run-time initialization(s)
*/
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
/**
* @brief Initialize the serial port to be used as console.
@ -319,8 +316,7 @@ static struct NS16550_plat serial_plat = {
*/
static int pcaal1_init_console(void)
{
add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
&serial_plat);
omap3_add_uart3();
return 0;
}
@ -362,10 +358,10 @@ static int pcaal1_mem_init(void)
*/
gpmc_generic_init(0x10);
#endif
add_mem_device("sram0", OMAP_SRAM_BASE, 60 * SZ_1K,
IORESOURCE_MEM_WRITEABLE);
omap3_add_sram0();
arm_add_mem_device("ram0", OMAP_SDRC_CS0, get_sdr_cs_size(SDRC_CS0_OSET));
omap_add_ram0(get_sdr_cs_size(SDRC_CS0_OSET));
printf("found %s at SDCS0\n", size_human_readable(get_sdr_cs_size(SDRC_CS0_OSET)));
if ((get_sdr_cs_size(SDRC_CS1_OSET) != 0) && (get_sdr_cs1_base() != OMAP_SDRC_CS0)) {
@ -377,11 +373,9 @@ static int pcaal1_mem_init(void)
}
mem_initcall(pcaal1_mem_init);
#ifdef CONFIG_MCI_OMAP_HSMMC
struct omap_hsmmc_platform_data pcaal1_hsmmc_plat = {
.f_max = 26000000,
};
#endif
static struct gpmc_nand_platform_data nand_plat = {
.device_width = 16,
@ -393,10 +387,7 @@ static int pcaal1_init_devices(void)
{
omap_add_gpmc_nand_device(&nand_plat);
#ifdef CONFIG_MCI_OMAP_HSMMC
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K,
IORESOURCE_MEM, &pcaal1_hsmmc_plat);
#endif
omap3_add_mmc1(&pcaal1_hsmmc_plat);
#ifdef CONFIG_DRIVER_NET_SMC911X
pcaal1_setup_net_chip();

24
arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
View File

@ -22,7 +22,7 @@
#include <ns16550.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/silicon.h>
#include <mach/omap4-silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@ -37,18 +37,12 @@
#include <mach/gpmc_nand.h>
#include <mach/xload.h>
#include <mach/omap_hsmmc.h>
#include <mach/omap4-devices.h>
#include <i2c/i2c.h>
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
static int pcaaxl2_console_init(void)
{
/* Register the serial port */
add_ns16550_device(DEVICE_ID_DYNAMIC, OMAP44XX_UART3_BASE, 1024,
IORESOURCE_MEM_8BIT, &serial_plat);
omap44xx_add_uart3();
return 0;
}
@ -56,10 +50,10 @@ console_initcall(pcaaxl2_console_init);
static int pcaaxl2_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, SZ_512M);
omap_add_ram0(SZ_512M);
omap44xx_add_sram0();
add_mem_device("sram0", 0x40300000, 48 * 1024,
IORESOURCE_MEM_WRITEABLE);
return 0;
}
mem_initcall(pcaaxl2_mem_init);
@ -111,16 +105,14 @@ static int pcaaxl2_devices_init(void)
u32 value;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC, NULL, 0x48070000, 0x1000,
IORESOURCE_MEM, NULL);
omap44xx_add_i2c1(NULL);
value = readl(OMAP4_CONTROL_PBIASLITE);
value &= ~OMAP4_MMC1_PBIASLITE_VMODE;
value |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ);
writel(value, OMAP4_CONTROL_PBIASLITE);
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x4809C100, SZ_4K,
IORESOURCE_MEM, &mmc_device);
omap44xx_add_mmc1(&mmc_device);
gpmc_generic_init(0x10);

54
arch/arm/configs/am335x_beaglebone_defconfig Normal file
View File

@ -0,0 +1,54 @@
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_AM33XX=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x81000000
CONFIG_KALLSYMS=y
CONFIG_PROMPT="barebox> "
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
# CONFIG_TIMESTAMP is not set
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/beaglebone/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
# CONFIG_SPI is not set
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_OMAP_HSMMC=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y

55
arch/arm/configs/am335x_beaglebone_mlo_large_defconfig Normal file
View File

@ -0,0 +1,55 @@
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_AM33XX=y
# CONFIG_OMAP_GPMC is not set
CONFIG_OMAP_BUILD_IFT=y
CONFIG_THUMB2_BAREBOX=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x402F0400
CONFIG_MEMORY_LAYOUT_FIXED=y
CONFIG_STACK_BASE=0x4030B800
CONFIG_STACK_SIZE=0x1600
CONFIG_MALLOC_BASE=0x8F000000
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_PROMPT="barebox> "
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
# CONFIG_TIMESTAMP is not set
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/beaglebone/env"
CONFIG_BAREBOXENV_TARGET=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
# CONFIG_CMD_UMOUNT is not set
# CONFIG_CMD_CLEAR is not set
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_TIMEOUT=y
# CONFIG_CMD_VERSION is not set
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
# CONFIG_SPI is not set
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
# CONFIG_MCI_INFO is not set
# CONFIG_MCI_WRITE is not set
CONFIG_MCI_OMAP_HSMMC=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_LFN=y

31
arch/arm/configs/am335x_beaglebone_mlo_small_defconfig Normal file
View File

@ -0,0 +1,31 @@
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_AM33XX=y
# CONFIG_OMAP_GPMC is not set
CONFIG_OMAP_BUILD_IFT=y
CONFIG_THUMB2_BAREBOX=y
# CONFIG_CMD_ARM_CPUINFO is not set
# CONFIG_BANNER is not set
# CONFIG_MEMINFO is not set
CONFIG_ENVIRONMENT_VARIABLES=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x402F0400
CONFIG_MEMORY_LAYOUT_FIXED=y
CONFIG_STACK_BASE=0x4030B800
CONFIG_STACK_SIZE=0x1600
CONFIG_MALLOC_BASE=0x8F000000
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_PROMPT="MLO>"
CONFIG_SHELL_NONE=y
# CONFIG_ERRNO_MESSAGES is not set
# CONFIG_TIMESTAMP is not set
# CONFIG_DEFAULT_ENVIRONMENT is not set
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
# CONFIG_SPI is not set
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_OMAP_HSMMC=y
# CONFIG_FS_RAMFS is not set
# CONFIG_FS_DEVFS is not set
CONFIG_FS_FAT=y
CONFIG_FS_FAT_LFN=y

56
arch/arm/configs/pcm051_defconfig Normal file
View File

@ -0,0 +1,56 @@
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_AM33XX=y
CONFIG_OMAP_BUILD_IFT=y
CONFIG_MACH_PCM051=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_TEXT_BASE=0x81000000
CONFIG_PROMPT="barebox@pcm051>"
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
# CONFIG_TIMESTAMP is not set
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm051/env"
CONFIG_DEBUG_INFO=y
CONFIG_ENABLE_FLASH_NOISE=y
CONFIG_ENABLE_PARTITION_NOISE=y
CONFIG_ENABLE_DEVICE_NOISE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_UIMAGE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
# CONFIG_SPI is not set
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_USB=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_OMAP_HSMMC=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y

32
arch/arm/mach-omap/Kconfig
View File

@ -42,12 +42,23 @@ config ARCH_OMAP4
help
Say Y here if you are using Texas Instrument's OMAP4 based platform
config ARCH_AM33XX
bool "AM33xx"
select CPU_V7
select GENERIC_GPIO
select OMAP_CLOCK_SOURCE_DMTIMER0
help
Say Y here if you are using Texas Instrument's AM33xx based platform
endchoice
# Blind enable all possible clocks.. think twice before you do this.
config OMAP_CLOCK_SOURCE_S32K
bool
config OMAP_CLOCK_SOURCE_DMTIMER0
bool
config OMAP3_CLOCK_CONFIG
prompt "Clock Configuration"
bool
@ -97,12 +108,14 @@ config OMAP4_USBBOOT
config BOARDINFO
default "Archos G9" if MACH_ARCHOSG9
default "Texas Instrument's SDP343x" if MACH_OMAP343xSDP
default "Texas Instrument's Beagle" if MACH_BEAGLE
default "Texas Instrument's Beagle Board" if MACH_BEAGLE
default "Texas Instrument's Beagle Bone" if MACH_BEAGLEBONE
default "Texas Instrument's OMAP3EVM" if MACH_OMAP3EVM
default "Texas Instrument's Panda" if MACH_PANDA
default "Phytec phyCORE pcm049" if MACH_PCM049
default "Phytec phyCARD-A-L1" if MACH_PCAAL1
default "Phytec phyCARD-A-XL2" if MACH_PCAAXL2
default "Phytec phyCORE-AM335x" if MACH_PCM051
choice
prompt "Select OMAP board"
@ -121,6 +134,14 @@ config MACH_BEAGLE
help
Say Y here if you are using Beagle Board
config MACH_BEAGLEBONE
bool "Texas Instrument's Beagle Bone"
select OMAP_CLOCK_ALL
select HAVE_NOSHELL
depends on ARCH_AM33XX
help
Say Y here if you are using Beagle Bone
config MACH_OMAP3EVM
bool "Texas Instrument's OMAP3 EVM"
select HAVE_NOSHELL
@ -169,6 +190,15 @@ config MACH_PCAAXL2
help
Say Y here if you are using a phyCARD-A-XL1 PCA-A-XL1
config MACH_PCM051
bool "Phytec phyCORE pcm051"
select OMAP_CLOCK_ALL
select HAVE_NOSHELL
select HAVE_DEFAULT_ENVIRONMENT_NEW
depends on ARCH_AM33XX
help
Say Y here if you are using Phytecs phyCORE pcm051 board
endchoice
if MACH_OMAP3EVM

4
arch/arm/mach-omap/Makefile
View File

@ -15,13 +15,15 @@
# GNU General Public License for more details.
#
#
obj-$(CONFIG_ARCH_OMAP) += syslib.o
obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o
pbl-$(CONFIG_ARCH_OMAP) += syslib.o
obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o
obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
pbl-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
obj-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o

289
arch/arm/mach-omap/am33xx_clock.c Normal file
View File

@ -0,0 +1,289 @@
/*
* pll.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/io.h>
#include <mach/am33xx-clock.h>
#define PRCM_MOD_EN 0x2
#define PRCM_FORCE_WAKEUP 0x2
#define PRCM_EMIF_CLK_ACTIVITY (0x1 << 2)
#define PRCM_L3_GCLK_ACTIVITY (0x1 << 4)
#define PLL_BYPASS_MODE 0x4
#define PLL_LOCK_MODE 0x7
#define PLL_MULTIPLIER_SHIFT 8
static void interface_clocks_enable(void)
{
/* Enable all the Interconnect Modules */
__raw_writel(PRCM_MOD_EN, CM_PER_L3_CLKCTRL);
while (__raw_readl(CM_PER_L3_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_PER_L4LS_CLKCTRL);
while (__raw_readl(CM_PER_L4LS_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_PER_L4FW_CLKCTRL);
while (__raw_readl(CM_PER_L4FW_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_WKUP_L4WKUP_CLKCTRL);
while (__raw_readl(CM_WKUP_L4WKUP_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_PER_L3_INSTR_CLKCTRL);
while (__raw_readl(CM_PER_L3_INSTR_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_PER_L4HS_CLKCTRL);
while (__raw_readl(CM_PER_L4HS_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_PER_SPI1_CLKCTRL);
while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
/* GPIO0 */
__raw_writel(PRCM_MOD_EN, CM_WKUP_GPIO0_CLKCTRL);
while (__raw_readl(CM_WKUP_GPIO0_CLKCTRL) != PRCM_MOD_EN);
}
static void power_domain_transition_enable(void)
{
/*
* Force power domain wake up transition
* Ensure that the corresponding interface clock is active before
* using the peripheral
*/
__raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L3_CLKSTCTRL);
__raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L4LS_CLKSTCTRL);
__raw_writel(PRCM_FORCE_WAKEUP, CM_WKUP_CLKSTCTRL);
__raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L4FW_CLKSTCTRL);
__raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L3S_CLKSTCTRL);
}
/*
* Enable the module clock and the power domain for required peripherals
*/
static void per_clocks_enable(void)
{
/* Enable the module clock */
__raw_writel(PRCM_MOD_EN, CM_PER_TIMER2_CLKCTRL);
while (__raw_readl(CM_PER_TIMER2_CLKCTRL) != PRCM_MOD_EN);
/* Select the Master osc 24 MHZ as Timer2 clock source */
__raw_writel(0x1, CLKSEL_TIMER2_CLK);
/* UART0 */
__raw_writel(PRCM_MOD_EN, CM_WKUP_UART0_CLKCTRL);
while (__raw_readl(CM_WKUP_UART0_CLKCTRL) != PRCM_MOD_EN);
/* UART3 */
__raw_writel(PRCM_MOD_EN, CM_PER_UART3_CLKCTRL);
while (__raw_readl(CM_PER_UART3_CLKCTRL) != PRCM_MOD_EN);
/* GPMC */
__raw_writel(PRCM_MOD_EN, CM_PER_GPMC_CLKCTRL);
while (__raw_readl(CM_PER_GPMC_CLKCTRL) != PRCM_MOD_EN);
/* ELM */
__raw_writel(PRCM_MOD_EN, CM_PER_ELM_CLKCTRL);
while (__raw_readl(CM_PER_ELM_CLKCTRL) != PRCM_MOD_EN);
/* i2c0 */
__raw_writel(PRCM_MOD_EN, CM_WKUP_I2C0_CLKCTRL);
while (__raw_readl(CM_WKUP_I2C0_CLKCTRL) != PRCM_MOD_EN);
/* i2c1 */
__raw_writel(PRCM_MOD_EN, CM_PER_I2C1_CLKCTRL);
while (__raw_readl(CM_PER_I2C1_CLKCTRL) != PRCM_MOD_EN);
/* i2c2 */
__raw_writel(PRCM_MOD_EN, CM_PER_I2C2_CLKCTRL);
while (__raw_readl(CM_PER_I2C2_CLKCTRL) != PRCM_MOD_EN);
/* Ethernet */
__raw_writel(PRCM_MOD_EN, CM_PER_CPGMAC0_CLKCTRL);
__raw_writel(PRCM_MOD_EN, CM_PER_CPSW_CLKSTCTRL);
while ((__raw_readl(CM_PER_CPGMAC0_CLKCTRL) & 0x30000) != 0x0);
/* MMC 0 & 1 */
__raw_writel(PRCM_MOD_EN, CM_PER_MMC0_CLKCTRL);
while (__raw_readl(CM_PER_MMC0_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_PER_MMC1_CLKCTRL);
while (__raw_readl(CM_PER_MMC1_CLKCTRL) != PRCM_MOD_EN);
/* Enable the control module though RBL would have done it*/
__raw_writel(PRCM_MOD_EN, CM_WKUP_CONTROL_CLKCTRL);
while (__raw_readl(CM_WKUP_CONTROL_CLKCTRL) != PRCM_MOD_EN);
/* SPI 0 & 1 */
__raw_writel(PRCM_MOD_EN, CM_PER_SPI0_CLKCTRL);
while (__raw_readl(CM_PER_SPI0_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_PER_SPI1_CLKCTRL);
while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
}
static void mpu_pll_config(int mpupll_M)
{
u32 clkmode, clksel, div_m2;
clkmode = __raw_readl(CM_CLKMODE_DPLL_MPU);
clksel = __raw_readl(CM_CLKSEL_DPLL_MPU);
div_m2 = __raw_readl(CM_DIV_M2_DPLL_MPU);
/* Set the PLL to bypass Mode */
__raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_MPU);
while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x00000100);
clksel = clksel & (~0x7ffff);
clksel = clksel | ((mpupll_M << 0x8) | MPUPLL_N);
__raw_writel(clksel, CM_CLKSEL_DPLL_MPU);
div_m2 = div_m2 & ~0x1f;
div_m2 = div_m2 | MPUPLL_M2;
__raw_writel(div_m2, CM_DIV_M2_DPLL_MPU);
clkmode = clkmode | 0x7;
__raw_writel(clkmode, CM_CLKMODE_DPLL_MPU);
while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x1);
}
static void core_pll_config(void)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
clkmode = __raw_readl(CM_CLKMODE_DPLL_CORE);
clksel = __raw_readl(CM_CLKSEL_DPLL_CORE);
div_m4 = __raw_readl(CM_DIV_M4_DPLL_CORE);
div_m5 = __raw_readl(CM_DIV_M5_DPLL_CORE);
div_m6 = __raw_readl(CM_DIV_M6_DPLL_CORE);
/* Set the PLL to bypass Mode */
__raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_CORE);
while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x00000100);
clksel = clksel & (~0x7ffff);
clksel = clksel | ((COREPLL_M << 0x8) | COREPLL_N);
__raw_writel(clksel, CM_CLKSEL_DPLL_CORE);
div_m4 = div_m4 & ~0x1f;
div_m4 = div_m4 | COREPLL_M4;
__raw_writel(div_m4, CM_DIV_M4_DPLL_CORE);
div_m5 = div_m5 & ~0x1f;
div_m5 = div_m5 | COREPLL_M5;
__raw_writel(div_m5, CM_DIV_M5_DPLL_CORE);
div_m6 = div_m6 & ~0x1f;
div_m6 = div_m6 | COREPLL_M6;
__raw_writel(div_m6, CM_DIV_M6_DPLL_CORE);
clkmode = clkmode | 0x7;
__raw_writel(clkmode, CM_CLKMODE_DPLL_CORE);
while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x1);
}
static void per_pll_config(void)
{
u32 clkmode, clksel, div_m2;
clkmode = __raw_readl(CM_CLKMODE_DPLL_PER);
clksel = __raw_readl(CM_CLKSEL_DPLL_PER);
div_m2 = __raw_readl(CM_DIV_M2_DPLL_PER);
/* Set the PLL to bypass Mode */
__raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_PER);
while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x00000100);
clksel = clksel & (~0x7ffff);
clksel = clksel | ((PERPLL_M << 0x8) | PERPLL_N);
__raw_writel(clksel, CM_CLKSEL_DPLL_PER);
div_m2 = div_m2 & ~0x7f;
div_m2 = div_m2 | PERPLL_M2;
__raw_writel(div_m2, CM_DIV_M2_DPLL_PER);
clkmode = clkmode | 0x7;
__raw_writel(clkmode, CM_CLKMODE_DPLL_PER);
while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
}
static void ddr_pll_config(void)
{
u32 clkmode, clksel, div_m2;
clkmode = __raw_readl(CM_CLKMODE_DPLL_DDR);
clksel = __raw_readl(CM_CLKSEL_DPLL_DDR);
div_m2 = __raw_readl(CM_DIV_M2_DPLL_DDR);
/* Set the PLL to bypass Mode */
clkmode = (clkmode & 0xfffffff8) | 0x00000004;
__raw_writel(clkmode, CM_CLKMODE_DPLL_DDR);
while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
clksel = clksel & (~0x7ffff);
clksel = clksel | ((DDRPLL_M << 0x8) | DDRPLL_N);
__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
div_m2 = div_m2 & 0xFFFFFFE0;
div_m2 = div_m2 | DDRPLL_M2;
__raw_writel(div_m2, CM_DIV_M2_DPLL_DDR);
clkmode = (clkmode & 0xfffffff8) | 0x7;
__raw_writel(clkmode, CM_CLKMODE_DPLL_DDR);
while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x1);
}
void enable_ddr_clocks(void)
{
/* Enable the EMIF_FW Functional clock */
__raw_writel(PRCM_MOD_EN, CM_PER_EMIF_FW_CLKCTRL);
/* Enable EMIF0 Clock */
__raw_writel(PRCM_MOD_EN, CM_PER_EMIF_CLKCTRL);
/* Poll for emif_gclk & L3_G clock are active */
while ((__raw_readl(CM_PER_L3_CLKSTCTRL) & (PRCM_EMIF_CLK_ACTIVITY |
PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
PRCM_L3_GCLK_ACTIVITY));
/* Poll if module is functional */
while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
}
/*
* Configure the PLL/PRCM for necessary peripherals
*/
void pll_init()
{
mpu_pll_config(MPUPLL_M_500);
core_pll_config();
per_pll_config();
ddr_pll_config();
/* Enable the required interconnect clocks */
interface_clocks_enable();
/* Enable power domain transition */
power_domain_transition_enable();
/* Enable the required peripherals */
per_clocks_enable();
}

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/*
* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
* (C) Copyright 2012 Jan Luebbe <j.luebbe@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <io.h>
#include <mach/am33xx-silicon.h>
#include <mach/am33xx-clock.h>
#include <mach/sys_info.h>
#include <mach/xload.h>
void __noreturn reset_cpu(unsigned long addr)
{
writel(AM33XX_PRM_RSTCTRL_RESET, AM33XX_PRM_RSTCTRL);
while (1);
}
/**
* @brief Get the upper address of current execution
*
* we can use this to figure out if we are running in SRAM /
* XIP Flash or in SDRAM
*
* @return base address
*/
u32 get_base(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
val &= 0xF0000000;
val >>= 28;
return val;
}
/**
* @brief Are we running in Flash XIP?
*
* If the base is in GPMC address space, we probably are!
*
* @return 1 if we are running in XIP mode, else return 0
*/
u32 running_in_flash(void)
{
if (get_base() < 4)
return 1; /* in flash */
return 0; /* running in SRAM or SDRAM */
}
/**
* @brief Are we running in OMAP internal SRAM?
*
* If in SRAM address, then yes!
*
* @return 1 if we are running in SRAM, else return 0
*/
u32 running_in_sram(void)
{
if (get_base() == 4)
return 1; /* in SRAM */
return 0; /* running in FLASH or SDRAM */
}
/**
* @brief Are we running in SDRAM?
*
* if we are not in GPMC nor in SRAM address space,
* we are in SDRAM execution area
*
* @return 1 if we are running from SDRAM, else return 0
*/
u32 running_in_sdram(void)
{
if (get_base() > 4)
return 1; /* in sdram */
return 0; /* running in SRAM or FLASH */
}
enum omap_boot_src am33xx_bootsrc(void)
{
return OMAP_BOOTSRC_MMC1; /* only MMC for now */
}

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/*
* mux.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <mach/am33xx-silicon.h>
#define MUX_CFG(value, offset) \
__raw_writel(value, (AM33XX_CTRL_BASE + offset));
/* PAD Control Fields */
#define SLEWCTRL (0x1 << 6)
#define RXACTIVE (0x1 << 5)
#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
#define MODE(val) val
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
*/
/* TODO replace with defines */
struct pad_signals {
int gpmc_ad0;
int gpmc_ad1;
int gpmc_ad2;
int gpmc_ad3;
int gpmc_ad4;
int gpmc_ad5;
int gpmc_ad6;
int gpmc_ad7;
int gpmc_ad8;
int gpmc_ad9;
int gpmc_ad10;
int gpmc_ad11;
int gpmc_ad12;
int gpmc_ad13;
int gpmc_ad14;
int gpmc_ad15;
int gpmc_a0;
int gpmc_a1;
int gpmc_a2;
int gpmc_a3;
int gpmc_a4;
int gpmc_a5;
int gpmc_a6;
int gpmc_a7;
int gpmc_a8;
int gpmc_a9;
int gpmc_a10;
int gpmc_a11;
int gpmc_wait0;
int gpmc_wpn;
int gpmc_be1n;
int gpmc_csn0;
int gpmc_csn1;
int gpmc_csn2;
int gpmc_csn3;
int gpmc_clk;
int gpmc_advn_ale;
int gpmc_oen_ren;
int gpmc_wen;
int gpmc_be0n_cle;
int lcd_data0;
int lcd_data1;
int lcd_data2;
int lcd_data3;
int lcd_data4;
int lcd_data5;
int lcd_data6;
int lcd_data7;
int lcd_data8;
int lcd_data9;
int lcd_data10;
int lcd_data11;
int lcd_data12;
int lcd_data13;
int lcd_data14;
int lcd_data15;
int lcd_vsync;
int lcd_hsync;
int lcd_pclk;
int lcd_ac_bias_en;
int mmc0_dat3;
int mmc0_dat2;
int mmc0_dat1;
int mmc0_dat0;
int mmc0_clk;
int mmc0_cmd;
int mii1_col;
int mii1_crs;
int mii1_rxerr;
int mii1_txen;
int mii1_rxdv;
int mii1_txd3;
int mii1_txd2;
int mii1_txd1;
int mii1_txd0;
int mii1_txclk;
int mii1_rxclk;
int mii1_rxd3;
int mii1_rxd2;
int mii1_rxd1;
int mii1_rxd0;
int rmii1_refclk;
int mdio_data;
int mdio_clk;
int spi0_sclk;
int spi0_d0;
int spi0_d1;
int spi0_cs0;
int spi0_cs1;
int ecap0_in_pwm0_out;
int uart0_ctsn;
int uart0_rtsn;
int uart0_rxd;
int uart0_txd;
int uart1_ctsn;
int uart1_rtsn;
int uart1_rxd;
int uart1_txd;
int i2c0_sda;
int i2c0_scl;
int mcasp0_aclkx;
int mcasp0_fsx;
int mcasp0_axr0;
int mcasp0_ahclkr;
int mcasp0_aclkr;
int mcasp0_fsr;
int mcasp0_axr1;
int mcasp0_ahclkx;
int xdma_event_intr0;
int xdma_event_intr1;
int nresetin_out;
int porz;
int nnmi;
int osc0_in;
int osc0_out;
int rsvd1;
int tms;
int tdi;
int tdo;
int tck;
int ntrst;
int emu0;
int emu1;
int osc1_in;
int osc1_out;
int pmic_power_en;
int rtc_porz;
int rsvd2;
int ext_wakeup;
int enz_kaldo_1p8v;
int usb0_dm;
int usb0_dp;
int usb0_ce;
int usb0_id;
int usb0_vbus;
int usb0_drvvbus;
int usb1_dm;
int usb1_dp;
int usb1_ce;
int usb1_id;
int usb1_vbus;
int usb1_drvvbus;
int ddr_resetn;
int ddr_csn0;
int ddr_cke;
int ddr_ck;
int ddr_nck;
int ddr_casn;
int ddr_rasn;
int ddr_wen;
int ddr_ba0;
int ddr_ba1;
int ddr_ba2;
int ddr_a0;
int ddr_a1;
int ddr_a2;
int ddr_a3;
int ddr_a4;
int ddr_a5;
int ddr_a6;
int ddr_a7;
int ddr_a8;
int ddr_a9;
int ddr_a10;
int ddr_a11;
int ddr_a12;
int ddr_a13;
int ddr_a14;
int ddr_a15;
int ddr_odt;
int ddr_d0;
int ddr_d1;
int ddr_d2;
int ddr_d3;
int ddr_d4;
int ddr_d5;
int ddr_d6;
int ddr_d7;
int ddr_d8;
int ddr_d9;
int ddr_d10;
int ddr_d11;
int ddr_d12;
int ddr_d13;
int ddr_d14;
int ddr_d15;
int ddr_dqm0;
int ddr_dqm1;
int ddr_dqs0;
int ddr_dqsn0;
int ddr_dqs1;
int ddr_dqsn1;
int ddr_vref;
int ddr_vtp;
int ddr_strben0;
int ddr_strben1;
int ain7;
int ain6;
int ain5;
int ain4;
int ain3;
int ain2;
int ain1;
int ain0;
int vrefp;
int vrefn;
};
struct module_pin_mux {
short reg_offset;
unsigned char val;
};
#define PAD_CTRL_BASE 0x800
#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
(PAD_CTRL_BASE))->x)
static const __maybe_unused struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
static const __maybe_unused struct module_pin_mux uart3_pin_mux[] = {
{OFFSET(spi0_cs1), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART3_RXD */
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
{-1},
};
#ifdef CONFIG_NAND
static const __maybe_unused struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
#endif
static const __maybe_unused struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static const __maybe_unused struct module_pin_mux i2c1_pin_mux[] = {
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static const __maybe_unused struct module_pin_mux i2c2_pin_mux[] = {
{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static const __maybe_unused struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static const __maybe_unused struct module_pin_mux rgmii2_pin_mux[] = {
{OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
{OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
{OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
{OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
{OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
{OFFSET(gpmc_a6), MODE(2)}, /* RGMII2_TCLK */
{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
{OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII2_RD2 */
{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
{OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII2_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static const __maybe_unused struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static const __maybe_unused struct module_pin_mux rmii1_pin_mux[] = {
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
{-1},
};
#ifdef CONFIG_NOR
static const __maybe_unused struct module_pin_mux nor_pin_mux[] = {
{OFFSET(lcd_data0), MODE(1) | PULLUDEN}, /* NOR_A0 */
{OFFSET(lcd_data1), MODE(1) | PULLUDEN}, /* NOR_A1 */
{OFFSET(lcd_data2), MODE(1) | PULLUDEN}, /* NOR_A2 */
{OFFSET(lcd_data3), MODE(1) | PULLUDEN}, /* NOR_A3 */
{OFFSET(lcd_data4), MODE(1) | PULLUDEN}, /* NOR_A4 */
{OFFSET(lcd_data5), MODE(1) | PULLUDEN}, /* NOR_A5 */
{OFFSET(lcd_data6), MODE(1) | PULLUDEN}, /* NOR_A6 */
{OFFSET(lcd_data7), MODE(1) | PULLUDEN}, /* NOR_A7 */
{OFFSET(gpmc_a8), MODE(0)}, /* NOR_A8 */
{OFFSET(gpmc_a9), MODE(0)}, /* NOR_A9 */
{OFFSET(gpmc_a10), MODE(0)}, /* NOR_A10 */
{OFFSET(gpmc_a11), MODE(0)}, /* NOR_A11 */
{OFFSET(lcd_data8), MODE(1) | PULLUDEN}, /* NOR_A12 */
{OFFSET(lcd_data9), MODE(1) | PULLUDEN}, /* NOR_A13 */
{OFFSET(lcd_data10), MODE(1) | PULLUDEN}, /* NOR_A14 */
{OFFSET(lcd_data11), MODE(1) | PULLUDEN}, /* NOR_A15 */
{OFFSET(lcd_data12), MODE(1) | PULLUDEN}, /* NOR_A16 */
{OFFSET(lcd_data13), MODE(1) | PULLUDEN}, /* NOR_A17 */
{OFFSET(lcd_data14), MODE(1) | PULLUDEN}, /* NOR_A18 */
{OFFSET(lcd_data15), MODE(1) | PULLUDEN}, /* NOR_A19 */
{OFFSET(gpmc_a4), MODE(4)}, /* NOR_A20 */
{OFFSET(gpmc_a5), MODE(4)}, /* NOR_A21 */
{OFFSET(gpmc_a6), MODE(4)}, /* NOR_A22 */
{OFFSET(gpmc_ad0), MODE(0) | RXACTIVE}, /* NOR_AD0 */
{OFFSET(gpmc_ad1), MODE(0) | RXACTIVE}, /* NOR_AD1 */
{OFFSET(gpmc_ad2), MODE(0) | RXACTIVE}, /* NOR_AD2 */
{OFFSET(gpmc_ad3), MODE(0) | RXACTIVE}, /* NOR_AD3 */
{OFFSET(gpmc_ad4), MODE(0) | RXACTIVE}, /* NOR_AD4 */
{OFFSET(gpmc_ad5), MODE(0) | RXACTIVE}, /* NOR_AD5 */
{OFFSET(gpmc_ad6), MODE(0) | RXACTIVE}, /* NOR_AD6 */
{OFFSET(gpmc_ad7), MODE(0) | RXACTIVE}, /* NOR_AD7 */
{OFFSET(gpmc_ad8), MODE(0) | RXACTIVE}, /* NOR_AD8 */
{OFFSET(gpmc_ad9), MODE(0) | RXACTIVE}, /* NOR_AD9 */
{OFFSET(gpmc_ad10), MODE(0) | RXACTIVE}, /* NOR_AD10 */
{OFFSET(gpmc_ad11), MODE(0) | RXACTIVE}, /* NOR_AD11 */
{OFFSET(gpmc_ad12), MODE(0) | RXACTIVE}, /* NOR_AD12 */
{OFFSET(gpmc_ad13), MODE(0) | RXACTIVE}, /* NOR_AD13 */
{OFFSET(gpmc_ad14), MODE(0) | RXACTIVE}, /* NOR_AD14 */
{OFFSET(gpmc_ad15), MODE(0) | RXACTIVE}, /* NOR_AD15 */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* NOR_CE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, /* NOR_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, /* NOR_WEN */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NOR WAIT */
{OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDEN}, /* NOR RESET */
{-1},
};
#endif
static const __maybe_unused struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
static const __maybe_unused struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{OFFSET(uart1_rxd), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
{OFFSET(mcasp0_fsx), (MODE(4) | RXACTIVE)}, /* MMC1_CD */
{-1},
};
static const __maybe_unused struct module_pin_mux spi0_pin_mux[] = {
{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, /*SPI0_SCLK */
{OFFSET(spi0_d0), MODE(0) | PULLUDEN | PULLUP_EN |
RXACTIVE}, /*SPI0_D0 */
{OFFSET(spi0_d1), MODE(0) | PULLUDEN |
RXACTIVE}, /*SPI0_D1 */
{OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, /*SPI0_CS0 */
{-1},
};
static const __maybe_unused struct module_pin_mux spi1_pin_mux[] = {
{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, /*SPI0_SCLK */
{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | PULLUP_EN |
RXACTIVE}, /*SPI0_D0 */
{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, /*SPI0_D1 */
{OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN |
RXACTIVE}, /*SPI0_CS0 */
{-1},
};
/*
* Configure the pin mux for the module
*/
static void configure_module_pin_mux(const struct module_pin_mux *mod_pin_mux)
{
int i;
if (!mod_pin_mux)
return;
for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
}
void enable_mii1_pin_mux(void)
{
configure_module_pin_mux(mii1_pin_mux);
}
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
void enable_i2c1_pin_mux(void)
{
configure_module_pin_mux(i2c1_pin_mux);
}
void enable_i2c2_pin_mux(void)
{
configure_module_pin_mux(i2c2_pin_mux);
}
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_mmc0_pin_mux(void)
{
configure_module_pin_mux(mmc0_pin_mux);
}

3
arch/arm/mach-omap/devices-gpmc-nand.c
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@ -24,7 +24,6 @@
#include <clock.h>
#include <io.h>
#include <mach/silicon.h>
#include <mach/gpmc.h>
#include <mach/gpmc_nand.h>
@ -46,7 +45,7 @@ int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata)
/* Configure GPMC CS before register */
gpmc_cs_config(pdata->cs, pdata->nand_cfg);
add_generic_device("gpmc_nand", DEVICE_ID_DYNAMIC, NULL, OMAP_GPMC_BASE,
add_generic_device("gpmc_nand", DEVICE_ID_DYNAMIC, NULL, (resource_size_t)omap_gpmc_base,
1024 * 4, IORESOURCE_MEM, pdata);
return 0;

89
arch/arm/mach-omap/dmtimer0.c Normal file
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@ -0,0 +1,89 @@
/**
* @file
* @brief Support DMTimer0 counter
*
* FileName: arch/arm/mach-omap/dmtimer0.c
*/
/*
* This File is based on arch/arm/mach-omap/s32k_clksource.c
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
* Nishanth Menon <x0nishan@ti.com>
*
* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <clock.h>
#include <init.h>
#include <io.h>
#include <mach/am33xx-silicon.h>
#define CLK_RC32K 32768
#define TIDR 0x0
#define TIOCP_CFG 0x10
#define IRQ_EOI 0x20
#define IRQSTATUS_RAW 0x24
#define IRQSTATUS 0x28
#define IRQSTATUS_SET 0x2c
#define IRQSTATUS_CLR 0x30
#define IRQWAKEEN 0x34
#define TCLR 0x38
#define TCRR 0x3C
#define TLDR 0x40
#define TTGR 0x44
#define TWPS 0x48
#define TMAR 0x4C
#define TCAR1 0x50
#define TSICR 0x54
#define TCAR2 0x58
/**
* @brief Provide a simple counter read
*
* @return DMTimer0 counter
*/
static uint64_t dmtimer0_read(void)
{
return readl(AM33XX_DMTIMER0_BASE + TCRR);
}
static struct clocksource dmtimer0_cs = {
.read = dmtimer0_read,
.mask = CLOCKSOURCE_MASK(32),
.shift = 10,
};
/**
* @brief Initialize the Clock
*
* Enable dmtimer0.
*
* @return result of @ref init_clock
*/
static int dmtimer0_init(void)
{
dmtimer0_cs.mult = clocksource_hz2mult(CLK_RC32K, dmtimer0_cs.shift);
/* Enable counter */
writel(0x3, AM33XX_DMTIMER0_BASE + TCLR);
return init_clock(&dmtimer0_cs);
}
/* Run me at boot time */
core_initcall(dmtimer0_init);

26
arch/arm/mach-omap/gpmc.c
View File

@ -24,11 +24,31 @@
#include <init.h>
#include <io.h>
#include <errno.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/omap4-silicon.h>
#include <mach/am33xx-silicon.h>
#include <mach/gpmc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
void __iomem *omap_gpmc_base;
static int gpmc_init(void)
{
#if defined(CONFIG_ARCH_OMAP3)
omap_gpmc_base = (void *)OMAP3_GPMC_BASE;
#elif defined(CONFIG_ARCH_OMAP4)
omap_gpmc_base = (void *)OMAP44XX_GPMC_BASE;
#elif defined(CONFIG_ARCH_AM33XX)
omap_gpmc_base = (void *)AM33XX_GPMC_BASE;
#else
#error "Unknown ARCH"
#endif
return 0;
}
pure_initcall(gpmc_init);
/**
* @brief Do a Generic initialization of GPMC. if you choose otherwise,
* Use gpmc registers to modify the values. The defaults configured are:
@ -43,7 +63,7 @@
void gpmc_generic_init(unsigned int cfg)
{
uint64_t start;
unsigned int reg = GPMC_REG(CONFIG7_0);
void __iomem *reg = GPMC_REG(CONFIG7_0);
char x = 0;
debug("gpmccfg=0x%x\n", cfg);
@ -89,7 +109,7 @@ EXPORT_SYMBOL(gpmc_generic_init);
*/
void gpmc_cs_config(char cs, struct gpmc_config *config)
{
unsigned int reg = GPMC_REG(CONFIG1_0) + (cs * GPMC_CONFIG_CS_SIZE);
void __iomem *reg = GPMC_REG(CONFIG1_0) + (cs * GPMC_CONFIG_CS_SIZE);
unsigned char x = 0;
debug("gpmccs=0x%x cfg=0x%p\n", cs, config);

194
arch/arm/mach-omap/include/mach/am33xx-clock.h Normal file
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@ -0,0 +1,194 @@
/*
* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _AM33XX_CLOCKS_H_
#define _AM33XX_CLOCKS_H_
#include "am33xx-silicon.h"
/* Put the pll config values over here */
#define OSC 24
/* MAIN PLL Fdll = 1 GHZ, */
#define MPUPLL_M_500 500 /* 125 * n */
#define MPUPLL_M_550 550 /* 125 * n */
#define MPUPLL_M_600 600 /* 125 * n */
#define MPUPLL_M_720 720 /* 125 * n */
#define MPUPLL_N 23 /* (n -1 ) */
#define MPUPLL_M2 1
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000 /* 125 * n */
#define COREPLL_N 23 /* (n -1 ) */
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
/*
* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
* frequency needs to be set to 960 MHZ. Hence,
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/
#define PERPLL_M 960
#define PERPLL_N 23
#define PERPLL_M2 5
/* DDR Freq is 166 MHZ for now*/
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
//#if (CONFIG_AM335X_EVM_IS_13x13 == 1)
#if 0
#define DDRPLL_M 166 /* M/N + 1 = 25/3 */
#else
#define DDRPLL_M 266
#endif
#define DDRPLL_N 23
#define DDRPLL_M2 1
/* PRCM */
/* Module Offsets */
#define CM_PER (AM33XX_PRM_BASE + 0x0)
#define CM_WKUP (AM33XX_PRM_BASE + 0x400)
#define CM_DPLL (AM33XX_PRM_BASE + 0x500)
#define CM_DEVICE (AM33XX_PRM_BASE + 0x0700)
#define CM_CEFUSE (AM33XX_PRM_BASE + 0x0A00)
#define PRM_DEVICE (AM33XX_PRM_BASE + 0x0F00)
/* Register Offsets */
/* Core PLL ADPLLS */
#define CM_CLKSEL_DPLL_CORE (CM_WKUP + 0x68)
#define CM_CLKMODE_DPLL_CORE (CM_WKUP + 0x90)
/* Core HSDIV */
#define CM_DIV_M4_DPLL_CORE (CM_WKUP + 0x80)
#define CM_DIV_M5_DPLL_CORE (CM_WKUP + 0x84)
#define CM_DIV_M6_DPLL_CORE (CM_WKUP + 0xD8)
#define CM_IDLEST_DPLL_CORE (CM_WKUP + 0x5c)
/* Peripheral PLL */
#define CM_CLKSEL_DPLL_PER (CM_WKUP + 0x9c)
#define CM_CLKMODE_DPLL_PER (CM_WKUP + 0x8c)
#define CM_DIV_M2_DPLL_PER (CM_WKUP + 0xAC)
#define CM_IDLEST_DPLL_PER (CM_WKUP + 0x70)
/* Display PLL */
#define CM_CLKSEL_DPLL_DISP (CM_WKUP + 0x54)
#define CM_CLKMODE_DPLL_DISP (CM_WKUP + 0x98)
#define CM_DIV_M2_DPLL_DISP (CM_WKUP + 0xA4)
/* DDR PLL */
#define CM_CLKSEL_DPLL_DDR (CM_WKUP + 0x40)
#define CM_CLKMODE_DPLL_DDR (CM_WKUP + 0x94)
#define CM_DIV_M2_DPLL_DDR (CM_WKUP + 0xA0)
#define CM_IDLEST_DPLL_DDR (CM_WKUP + 0x34)
/* MPU PLL */
#define CM_CLKSEL_DPLL_MPU (CM_WKUP + 0x2c)
#define CM_CLKMODE_DPLL_MPU (CM_WKUP + 0x88)
#define CM_DIV_M2_DPLL_MPU (CM_WKUP + 0xA8)
#define CM_IDLEST_DPLL_MPU (CM_WKUP + 0x20)
/* TIMER Clock Source Select */
#define CLKSEL_TIMER2_CLK (CM_DPLL + 0x8)
/* Interconnect clocks */
#define CM_PER_L4LS_CLKCTRL (CM_PER + 0x60) /* EMIF */
#define CM_PER_L4FW_CLKCTRL (CM_PER + 0x64) /* EMIF FW */
#define CM_PER_L3_CLKCTRL (CM_PER + 0xE0) /* OCMC RAM */
#define CM_PER_L3_INSTR_CLKCTRL (CM_PER + 0xDC)
#define CM_PER_L4HS_CLKCTRL (CM_PER + 0x120)
#define CM_WKUP_L4WKUP_CLKCTRL (CM_WKUP + 0x0c)/* UART0 */
/* Domain Wake UP */
#define CM_WKUP_CLKSTCTRL (CM_WKUP + 0) /* UART0 */
#define CM_PER_L4LS_CLKSTCTRL (CM_PER + 0x0) /* TIMER2 */
#define CM_PER_L3_CLKSTCTRL (CM_PER + 0x0c) /* EMIF */
#define CM_PER_L4FW_CLKSTCTRL (CM_PER + 0x08) /* EMIF FW */
#define CM_PER_L3S_CLKSTCTRL (CM_PER + 0x4)
#define CM_PER_L4HS_CLKSTCTRL (CM_PER + 0x011c)
#define CM_CEFUSE_CLKSTCTRL (CM_CEFUSE + 0x0)
/* Module Enable Registers */
#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x80) /* Timer2 */
#define CM_WKUP_UART0_CLKCTRL (CM_WKUP + 0xB4)/* UART0 */
#define CM_WKUP_CONTROL_CLKCTRL (CM_WKUP + 0x4) /* Control Module */
#define CM_PER_EMIF_CLKCTRL (CM_PER + 0x28) /* EMIF */
#define CM_PER_EMIF_FW_CLKCTRL (CM_PER + 0xD0) /* EMIF FW */
#define CM_PER_GPMC_CLKCTRL (CM_PER + 0x30) /* GPMC */
#define CM_PER_ELM_CLKCTRL (CM_PER + 0x40) /* ELM */
#define CM_PER_SPI0_CLKCTRL (CM_PER + 0x4c) /* SPI0 */
#define CM_PER_SPI1_CLKCTRL (CM_PER + 0x50) /* SPI1 */
#define CM_WKUP_I2C0_CLKCTRL (CM_WKUP + 0xB8) /* I2C0 */
#define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x14) /* Ethernet */
#define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144)/* Ethernet */
#define CM_PER_OCMCRAM_CLKCTRL (CM_PER + 0x2C) /* OCMC RAM */
#define CM_PER_GPIO2_CLKCTRL (CM_PER + 0xB0) /* GPIO2 */
#define CM_PER_UART3_CLKCTRL (CM_PER + 0x74) /* UART3 */
#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */
#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */
#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */
#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x3C)
#define CM_PER_MMC1_CLKCTRL (CM_PER + 0xF4)
#define CM_PER_MMC2_CLKCTRL (CM_PER + 0xF8)
/* PRCM */
#define CM_DPLL_OFFSET (AM33XX_PRM_BASE + 0x0300)
#define CM_ALWON_WDTIMER_CLKCTRL (AM33XX_PRM_BASE + 0x158C)
#define CM_ALWON_SPI_CLKCTRL (AM33XX_PRM_BASE + 0x1590)
#define CM_ALWON_CONTROL_CLKCTRL (AM33XX_PRM_BASE + 0x15C4)
#define CM_ALWON_L3_SLOW_CLKSTCTRL (AM33XX_PRM_BASE + 0x1400)
#define CM_ALWON_GPIO_0_CLKCTRL (AM33XX_PRM_BASE + 0x155c)
#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (AM33XX_PRM_BASE + 0x155c)
/* Ethernet */
#define CM_ETHERNET_CLKSTCTRL (AM33XX_PRM_BASE + 0x1404)
#define CM_ALWON_ETHERNET_0_CLKCTRL (AM33XX_PRM_BASE + 0x15D4)
#define CM_ALWON_ETHERNET_1_CLKCTRL (AM33XX_PRM_BASE + 0x15D8)
/* UARTs */
#define CM_ALWON_UART_0_CLKCTRL (AM33XX_PRM_BASE + 0x1550)
#define CM_ALWON_UART_1_CLKCTRL (AM33XX_PRM_BASE + 0x1554)
#define CM_ALWON_UART_2_CLKCTRL (AM33XX_PRM_BASE + 0x1558)
/* I2C */
/* Note: In ti814x I2C0 and I2C2 have common clk control */
#define CM_ALWON_I2C_0_CLKCTRL (AM33XX_PRM_BASE + 0x1564)
/* EMIF4 PRCM Defintion */
#define CM_DEFAULT_L3_FAST_CLKSTCTRL (AM33XX_PRM_BASE + 0x0508)
#define CM_DEFAULT_EMIF_0_CLKCTRL (AM33XX_PRM_BASE + 0x0520)
#define CM_DEFAULT_EMIF_1_CLKCTRL (AM33XX_PRM_BASE + 0x0524)
#define CM_DEFAULT_DMM_CLKCTRL (AM33XX_PRM_BASE + 0x0528)
#define CM_DEFAULT_FW_CLKCTRL (AM33XX_PRM_BASE + 0x052C)
/* ALWON PRCM */
#define CM_ALWON_OCMC_0_CLKSTCTRL CM_PER_L3_CLKSTCTRL
#define CM_ALWON_OCMC_0_CLKCTRL CM_PER_OCMCRAM_CLKCTRL
#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
extern void pll_init(void);
extern void enable_ddr_clocks(void);
#endif /* endif _AM33XX_CLOCKS_H_ */

33
arch/arm/mach-omap/include/mach/am33xx-devices.h Normal file
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@ -0,0 +1,33 @@
#ifndef __MACH_OMAP3_DEVICES_H
#define __MACH_OMAP3_DEVICES_H
#include <driver.h>
#include <sizes.h>
#include <mach/am33xx-silicon.h>
#include <mach/devices.h>
#include <mach/omap_hsmmc.h>
/* the device numbering is the same as in the TRM memory map (SPRUH73G) */
static inline struct device_d *am33xx_add_uart0(void)
{
return omap_add_uart(0, AM33XX_UART0_BASE);
}
static inline struct device_d *am33xx_add_uart1(void)
{
return omap_add_uart(1, AM33XX_UART1_BASE);
}
static inline struct device_d *am33xx_add_uart2(void)
{
return omap_add_uart(2, AM33XX_UART2_BASE);
}
static inline struct device_d *am33xx_add_mmc0(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap3-hsmmc", 0, NULL,
AM33XX_MMCHS0_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
#endif /* __MACH_OMAP3_DEVICES_H */

23
arch/arm/mach-omap/include/mach/am33xx-mux.h Normal file
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@ -0,0 +1,23 @@
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __AM33XX_MUX_H__
#define __AM33XX_MUX_H__
extern void enable_mii1_pin_mux(void);
extern void enable_i2c0_pin_mux(void);
extern void enable_i2c1_pin_mux(void);
extern void enable_i2c2_pin_mux(void);
extern void enable_uart0_pin_mux(void);
extern void enable_mmc0_pin_mux(void);
#endif /*__AM33XX_MUX_H__ */

166
arch/arm/mach-omap/include/mach/am33xx-silicon.h Normal file
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@ -0,0 +1,166 @@
/*
* This file contains the address info for various AM33XX modules.
*
* Copyright (C) 2012 Teresa Gámez <t.gamez@phytec.de>,
* Phytec Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_AM33XX_H
#define __ASM_ARCH_AM33XX_H
/** AM335x Internal Bus Base addresses */
#define AM33XX_L4_WKUP_BASE 0x44C00000
#define AM33XX_L4_PER_BASE 0x48000000
#define AM33XX_L4_FAST_BASE 0x4A000000
/* the device numbering is the same as in the TRM memory map (SPRUH73G) */
/* UART */
#define AM33XX_UART0_BASE (AM33XX_L4_WKUP_BASE + 0x209000)
#define AM33XX_UART1_BASE (AM33XX_L4_PER_BASE + 0x22000)
#define AM33XX_UART2_BASE (AM33XX_L4_PER_BASE + 0x24000)
/* EMFI Registers */
#define AM33XX_EMFI0_BASE 0x4C000000
#define AM33XX_DRAM_ADDR_SPACE_START 0x80000000
#define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000
/* GPMC */
#define AM33XX_GPMC_BASE 0x50000000
/* MMC */
#define AM33XX_MMCHS0_BASE (AM33XX_L4_PER_BASE + 0x60000)
#define AM33XX_MMC1_BASE (AM33XX_L4_PER_BASE + 0x1D8000)
#define AM33XX_MMCHS2_BASE 0x47810000
/* DTMTimer0 */
#define AM33XX_DMTIMER0_BASE (AM33XX_L4_WKUP_BASE + 0x205000)
/* PRM */
#define AM33XX_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000)
#define AM33XX_PRM_RSTCTRL (AM33XX_PRM_BASE + 0x0f00)
#define AM33XX_PRM_RSTCTRL_RESET 0x1
/* CTRL */
#define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000)
/* Watchdog Timer */
#define AM33XX_WDT_BASE 0x44E35000
/* EMIF Base address */
#define AM33XX_EMIF4_0_CFG_BASE 0x4C000000
#define AM33XX_EMIF4_1_CFG_BASE 0x4D000000
#define AM33XX_DMM_BASE 0x4E000000
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000
/*DMM & EMIF4 MMR Declaration*/
#define AM33XX_DMM_LISA_MAP__0 (AM33XX_DMM_BASE + 0x40)
#define AM33XX_DMM_LISA_MAP__1 (AM33XX_DMM_BASE + 0x44)
#define AM33XX_DMM_LISA_MAP__2 (AM33XX_DMM_BASE + 0x48)
#define AM33XX_DMM_LISA_MAP__3 (AM33XX_DMM_BASE + 0x4C)
#define AM33XX_DMM_PAT_BASE_ADDR (AM33XX_DMM_BASE + 0x460)
#define AM33XX_EMIF4_0_REG(REGNAME) (AM33XX_EMIF4_0_CFG_BASE + EMIF4_##REGNAME)
#define AM33XX_EMIF4_1_REG(REGNAME) (AM33XX_EMIF4_1_CFG_BASE + EMIF4_##REGNAME)
#define EMIF4_MOD_ID_REV 0x0
#define EMIF4_SDRAM_STATUS 0x04
#define EMIF4_SDRAM_CONFIG 0x08
#define EMIF4_SDRAM_CONFIG2 0x0C
#define EMIF4_SDRAM_REF_CTRL 0x10
#define EMIF4_SDRAM_REF_CTRL_SHADOW 0x14
#define EMIF4_SDRAM_TIM_1 0x18
#define EMIF4_SDRAM_TIM_1_SHADOW 0x1C
#define EMIF4_SDRAM_TIM_2 0x20
#define EMIF4_SDRAM_TIM_2_SHADOW 0x24
#define EMIF4_SDRAM_TIM_3 0x28
#define EMIF4_SDRAM_TIM_3_SHADOW 0x2C
#define EMIF0_SDRAM_MGMT_CTRL 0x38
#define EMIF0_SDRAM_MGMT_CTRL_SHD 0x3C
#define EMIF4_DDR_PHY_CTRL_1 0xE4
#define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xE8
#define EMIF4_DDR_PHY_CTRL_2 0xEC
#define EMIF4_IODFT_TLGC 0x60
#define AM33XX_VTP0_CTRL_REG 0x44E10E0C
#define AM33XX_VTP1_CTRL_REG 0x48140E10
/* OCMC */
#define AM33XX_SRAM0_SIZE (0x1B400) /* 109 KB */
#define AM33XX_SRAM_GPMC_STACK_SIZE (0x40)
#define AM33XX_LOW_LEVEL_SRAM_STACK (AM33XX_SRAM0_START + AM33XX_SRAM0_SIZE - 4)
/* DDR offsets */
#define AM33XX_DDR_PHY_BASE_ADDR 0x44E12000
#define AM33XX_DDR_IO_CTRL 0x44E10E04
#define AM33XX_DDR_CKE_CTRL 0x44E1131C
#define AM33XX_CONTROL_BASE_ADDR 0x44E10000
#define AM33XX_DDR_CMD0_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1404)
#define AM33XX_DDR_CMD1_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1408)
#define AM33XX_DDR_CMD2_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x140C)
#define AM33XX_DDR_DATA0_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1440)
#define AM33XX_DDR_DATA1_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1444)
#define AM33XX_CMD0_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x01C)
#define AM33XX_CMD0_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x020)
#define AM33XX_CMD0_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x024)
#define AM33XX_CMD0_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x028)
#define AM33XX_CMD0_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x02C)
#define AM33XX_CMD1_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x050)
#define AM33XX_CMD1_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x054)
#define AM33XX_CMD1_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x058)
#define AM33XX_CMD1_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x05C)
#define AM33XX_CMD1_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x060)
#define AM33XX_CMD2_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x084)
#define AM33XX_CMD2_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x088)
#define AM33XX_CMD2_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x08C)
#define AM33XX_CMD2_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x090)
#define AM33XX_CMD2_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x094)
#define AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0C8)
#define AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0CC)
#define AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0DC)
#define AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0E0)
#define AM33XX_DATA0_WRLVL_INIT_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F0)
#define AM33XX_DATA0_WRLVL_INIT_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F4)
#define AM33XX_DATA0_GATELVL_INIT_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0FC)
#define AM33XX_DATA0_GATELVL_INIT_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x100)
#define AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x108)
#define AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x10C)
#define AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x120)
#define AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x124)
#define AM33XX_DATA0_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x138)
#define AM33XX_DATA0_RANK0_DELAYS_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x134)
#define AM33XX_DATA1_RANK0_DELAYS_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1D8)
/* Ethernet MAC ID from EFuse */
#define AM33XX_MAC_ID0_LO (AM33XX_CTRL_BASE + 0x630)
#define AM33XX_MAC_ID0_HI (AM33XX_CTRL_BASE + 0x634)
#define AM33XX_MAC_ID1_LO (AM33XX_CTRL_BASE + 0x638)
#define AM33XX_MAC_ID1_HI (AM33XX_CTRL_BASE + 0x63c)
#define AM33XX_MAC_MII_SEL (AM33XX_CTRL_BASE + 0x650)
#endif

7
arch/arm/mach-omap/include/mach/clocks.h
View File

@ -34,11 +34,4 @@
#define S26M 26000000
#define S38_4M 38400000
#ifdef CONFIG_ARCH_OMAP3
#include <mach/omap3-clock.h>
#endif
#ifdef CONFIG_ARCH_OMAP4
#include <mach/omap4-clock.h>
#endif
#endif /* __OMAP_CLOCKS_H_ */

4
arch/arm/mach-omap/include/mach/control.h
View File

@ -31,7 +31,7 @@
* Control register defintion which unwraps to the real register
* offset + base address
*/
#define CONTROL_REG(REGNAME) (OMAP_CTRL_BASE + CONTROL_##REGNAME)
#define OMAP3_CONTROL_REG(REGNAME) (OMAP3_CTRL_BASE + CONTROL_##REGNAME)
#define CONTROL_SCALABLE_OMAP_STATUS (0x44C)
#define CONTROL_SCALABLE_OMAP_OCP (0x534)
@ -79,7 +79,7 @@
/** Provide the Regoffset, Value */
#define MUX_VAL(OFFSET,VALUE)\
writew((VALUE), OMAP_CTRL_BASE + (OFFSET))
writew((VALUE), OMAP3_CTRL_BASE + (OFFSET))
/**
* macro for Padconfig Registers @see

5
arch/arm/mach-omap/include/mach/debug_ll.h
View File

@ -35,6 +35,11 @@
#define UART_BASE OMAP44XX_UART3_BASE
#endif
#ifdef CONFIG_ARCH_AM33XX
#include <mach/am33xx-silicon.h>
#define UART_BASE AM33XX_UART0_BASE
#endif
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR (5 << 2)
#define THR (0 << 2)

14
arch/arm/mach-omap/include/mach/devices.h Normal file
View File

@ -0,0 +1,14 @@
#ifndef __MACH_OMAP_DEVICES_H
#define __MACH_OMAP_DEVICES_H
#include <mach/omap_hsmmc.h>
void omap_add_ram0(resource_size_t size);
void omap_add_sram0(resource_size_t base, resource_size_t size);
struct device_d *omap_add_uart(int id, unsigned long base);
struct device_d *omap_add_i2c(int id, unsigned long base, void *pdata);
#endif /* __MACH_OMAP_DEVICES_H */

4
arch/arm/mach-omap/include/mach/gpmc.h
View File

@ -32,8 +32,10 @@
#ifndef __ASM_ARCH_OMAP_GPMC_H
#define __ASM_ARCH_OMAP_GPMC_H
extern void __iomem *omap_gpmc_base;
/** GPMC Reg Wrapper */
#define GPMC_REG(REGNAME) (OMAP_GPMC_BASE + GPMC_##REGNAME)
#define GPMC_REG(REGNAME) (omap_gpmc_base + GPMC_##REGNAME)
#define GPMC_SYS_CONFIG (0x10)
#define GPMC_SYS_STATUS (0x14)

4
arch/arm/mach-omap/include/mach/omap3-clock.h
View File

@ -23,7 +23,7 @@
#define _OMAP343X_CLOCKS_H_
/** CM Clock Regs Wrapper */
#define CM_REG(REGNAME) (OMAP_CM_BASE + CM_##REGNAME)
#define OMAP3_CM_REG(REGNAME) (OMAP3_CM_BASE + CM_##REGNAME)
#define CM_FCLKEN_IVA2 0X0000
#define CM_CLKEN_PLL_IVA2 0X0004
@ -73,7 +73,7 @@
#define CM_CLKSTCTRL_USBH 0x1448
/** PRM Clock Regs */
#define PRM_REG(REGNAME) (OMAP_PRM_BASE + PRM_##REGNAME)
#define OMAP3_PRM_REG(REGNAME) (OMAP3_PRM_BASE + PRM_##REGNAME)
#define PRM_CLKSEL 0x0D40
#define PRM_RSTCTRL 0x1250
#define PRM_CLKSRC_CTRL 0x1270

69
arch/arm/mach-omap/include/mach/omap3-devices.h
View File

@ -1,7 +1,18 @@
#ifndef __MACH_OMAP3_DEVICES_H
#define __MACH_OMAP3_DEVICES_H
#include <driver.h>
#include <sizes.h>
#include <mach/omap3-silicon.h>
#include <mach/devices.h>
#include <mach/mcspi.h>
#include <mach/omap_hsmmc.h>
static inline void omap3_add_sram0(void)
{
return omap_add_sram0(OMAP3_SRAM_BASE, 64 * SZ_1K);
}
/* the device numbering is the same as in the device tree */
@ -30,3 +41,59 @@ static inline struct device_d *omap3_add_spi4(void)
{
return omap3_add_spi(4, OMAP3_MCSPI4_BASE);
}
static inline struct device_d *omap3_add_uart1(void)
{
return omap_add_uart(0, OMAP3_UART1_BASE);
}
static inline struct device_d *omap3_add_uart2(void)
{
return omap_add_uart(1, OMAP3_UART2_BASE);
}
static inline struct device_d *omap3_add_uart3(void)
{
return omap_add_uart(2, OMAP3_UART3_BASE);
}
static inline struct device_d *omap3_add_mmc1(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap3-hsmmc", 0, NULL,
OMAP3_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
static inline struct device_d *omap3_add_mmc2(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap3-hsmmc", 1, NULL,
OMAP3_MMC2_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
static inline struct device_d *omap3_add_mmc3(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap3-hsmmc", 2, NULL,
OMAP3_MMC3_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
static inline struct device_d *omap3_add_i2c1(void *pdata)
{
return omap_add_i2c(0, OMAP3_I2C1_BASE, pdata);
}
static inline struct device_d *omap3_add_i2c2(void *pdata)
{
return omap_add_i2c(1, OMAP3_I2C2_BASE, pdata);
}
static inline struct device_d *omap3_add_i2c3(void *pdata)
{
return omap_add_i2c(2, OMAP3_I2C3_BASE, pdata);
}
static inline struct device_d *omap3_add_ehci(void *pdata)
{
return add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP3_EHCI_BASE,
OMAP3_EHCI_BASE + 0x10, pdata);
}
#endif /* __MACH_OMAP3_DEVICES_H */

126
arch/arm/mach-omap/include/mach/omap3-silicon.h
View File

@ -34,82 +34,82 @@
/* PLEASE PLACE ONLY BASE DEFINES HERE */
/** OMAP Internal Bus Base addresses */
#define OMAP_L4_CORE_BASE 0x48000000
#define OMAP_INTC_BASE 0x48200000
#define OMAP_L4_WKUP_BASE 0x48300000
#define OMAP_L4_PER_BASE 0x49000000
#define OMAP_L4_EMU_BASE 0x54000000
#define OMAP_SGX_BASE 0x50000000
#define OMAP_IVA_BASE 0x5C000000
#define OMAP_SMX_APE_BASE 0x68000000
#define OMAP_SMS_BASE 0x6C000000
#define OMAP_SDRC_BASE 0x6D000000
#define OMAP_GPMC_BASE 0x6E000000
#define OMAP3_L4_CORE_BASE 0x48000000
#define OMAP3_INTC_BASE 0x48200000
#define OMAP3_L4_WKUP_BASE 0x48300000
#define OMAP3_L4_PER_BASE 0x49000000
#define OMAP3_L4_EMU_BASE 0x54000000
#define OMAP3_SGX_BASE 0x50000000
#define OMAP3_IVA_BASE 0x5C000000
#define OMAP3_SMX_APE_BASE 0x68000000
#define OMAP3_SMS_BASE 0x6C000000
#define OMAP3_SDRC_BASE 0x6D000000
#define OMAP3_GPMC_BASE 0x6E000000
/** Peripheral Base Addresses */
#define OMAP_CTRL_BASE (OMAP_L4_CORE_BASE + 0x02000)
#define OMAP_CM_BASE (OMAP_L4_CORE_BASE + 0x04000)
#define OMAP_PRM_BASE (OMAP_L4_WKUP_BASE + 0x06000)
#define OMAP3_CTRL_BASE (OMAP3_L4_CORE_BASE + 0x02000)
#define OMAP3_CM_BASE (OMAP3_L4_CORE_BASE + 0x04000)
#define OMAP3_PRM_BASE (OMAP3_L4_WKUP_BASE + 0x06000)
#define OMAP_UART1_BASE (OMAP_L4_CORE_BASE + 0x6A000)
#define OMAP_UART2_BASE (OMAP_L4_CORE_BASE + 0x6C000)
#define OMAP_UART3_BASE (OMAP_L4_PER_BASE + 0x20000)
#define OMAP3_UART1_BASE (OMAP3_L4_CORE_BASE + 0x6A000)
#define OMAP3_UART2_BASE (OMAP3_L4_CORE_BASE + 0x6C000)
#define OMAP3_UART3_BASE (OMAP3_L4_PER_BASE + 0x20000)
#define OMAP_I2C1_BASE (OMAP_L4_CORE_BASE + 0x70000)
#define OMAP_I2C2_BASE (OMAP_L4_CORE_BASE + 0x72000)
#define OMAP_I2C3_BASE (OMAP_L4_CORE_BASE + 0x60000)
#define OMAP3_I2C1_BASE (OMAP3_L4_CORE_BASE + 0x70000)
#define OMAP3_I2C2_BASE (OMAP3_L4_CORE_BASE + 0x72000)
#define OMAP3_I2C3_BASE (OMAP3_L4_CORE_BASE + 0x60000)
#define OMAP_GPTIMER1_BASE (OMAP_L4_WKUP_BASE + 0x18000)
#define OMAP_GPTIMER2_BASE (OMAP_L4_PER_BASE + 0x32000)
#define OMAP_GPTIMER3_BASE (OMAP_L4_PER_BASE + 0x34000)
#define OMAP_GPTIMER4_BASE (OMAP_L4_PER_BASE + 0x36000)
#define OMAP_GPTIMER5_BASE (OMAP_L4_PER_BASE + 0x38000)
#define OMAP_GPTIMER6_BASE (OMAP_L4_PER_BASE + 0x3A000)
#define OMAP_GPTIMER7_BASE (OMAP_L4_PER_BASE + 0x3C000)
#define OMAP_GPTIMER8_BASE (OMAP_L4_PER_BASE + 0x3E000)
#define OMAP_GPTIMER9_BASE (OMAP_L4_PER_BASE + 0x40000)
#define OMAP_GPTIMER10_BASE (OMAP_L4_CORE_BASE + 0x86000)
#define OMAP_GPTIMER11_BASE (OMAP_L4_CORE_BASE + 0x88000)
#define OMAP3_GPTIMER1_BASE (OMAP3_L4_WKUP_BASE + 0x18000)
#define OMAP3_GPTIMER2_BASE (OMAP3_L4_PER_BASE + 0x32000)
#define OMAP3_GPTIMER3_BASE (OMAP3_L4_PER_BASE + 0x34000)
#define OMAP3_GPTIMER4_BASE (OMAP3_L4_PER_BASE + 0x36000)
#define OMAP3_GPTIMER5_BASE (OMAP3_L4_PER_BASE + 0x38000)
#define OMAP3_GPTIMER6_BASE (OMAP3_L4_PER_BASE + 0x3A000)
#define OMAP3_GPTIMER7_BASE (OMAP3_L4_PER_BASE + 0x3C000)
#define OMAP3_GPTIMER8_BASE (OMAP3_L4_PER_BASE + 0x3E000)
#define OMAP3_GPTIMER9_BASE (OMAP3_L4_PER_BASE + 0x40000)
#define OMAP3_GPTIMER10_BASE (OMAP3_L4_CORE_BASE + 0x86000)
#define OMAP3_GPTIMER11_BASE (OMAP3_L4_CORE_BASE + 0x88000)
#define OMAP_WDTIMER2_BASE (OMAP_L4_WKUP_BASE + 0x14000)
#define OMAP_WDTIMER3_BASE (OMAP_L4_PER_BASE + 0x30000)
#define OMAP3_WDTIMER2_BASE (OMAP3_L4_WKUP_BASE + 0x14000)
#define OMAP3_WDTIMER3_BASE (OMAP3_L4_PER_BASE + 0x30000)
#define OMAP_32KTIMER_BASE (OMAP_L4_WKUP_BASE + 0x20000)
#define OMAP3_32KTIMER_BASE (OMAP3_L4_WKUP_BASE + 0x20000)
#define OMAP_MMC1_BASE (OMAP_L4_CORE_BASE + 0x9C000)
#define OMAP_MMC2_BASE (OMAP_L4_CORE_BASE + 0xB4000)
#define OMAP_MMC3_BASE (OMAP_L4_CORE_BASE + 0xAD000)
#define OMAP3_MMC1_BASE (OMAP3_L4_CORE_BASE + 0x9C000)
#define OMAP3_MMC2_BASE (OMAP3_L4_CORE_BASE + 0xB4000)
#define OMAP3_MMC3_BASE (OMAP3_L4_CORE_BASE + 0xAD000)
#define OMAP_MUSB0_BASE (OMAP_L4_CORE_BASE + 0xAB000)
#define OMAP3_MUSB0_BASE (OMAP3_L4_CORE_BASE + 0xAB000)
#define OMAP_GPIO1_BASE (OMAP_L4_WKUP_BASE + 0x10000)
#define OMAP_GPIO2_BASE (OMAP_L4_PER_BASE + 0x50000)
#define OMAP_GPIO3_BASE (OMAP_L4_PER_BASE + 0x52000)
#define OMAP_GPIO4_BASE (OMAP_L4_PER_BASE + 0x54000)
#define OMAP_GPIO5_BASE (OMAP_L4_PER_BASE + 0x56000)
#define OMAP_GPIO6_BASE (OMAP_L4_PER_BASE + 0x58000)
#define OMAP3_GPIO1_BASE (OMAP3_L4_WKUP_BASE + 0x10000)
#define OMAP3_GPIO2_BASE (OMAP3_L4_PER_BASE + 0x50000)
#define OMAP3_GPIO3_BASE (OMAP3_L4_PER_BASE + 0x52000)
#define OMAP3_GPIO4_BASE (OMAP3_L4_PER_BASE + 0x54000)
#define OMAP3_GPIO5_BASE (OMAP3_L4_PER_BASE + 0x56000)
#define OMAP3_GPIO6_BASE (OMAP3_L4_PER_BASE + 0x58000)
/** MPU WDT Definition */
#define OMAP_MPU_WDTIMER_BASE OMAP_WDTIMER2_BASE
#define OMAP3_MPU_WDTIMER_BASE OMAP3_WDTIMER2_BASE
#define OMAP_HSUSB_OTG_BASE (OMAP_L4_CORE_BASE + 0xAB000)
#define OMAP_USBTLL_BASE (OMAP_L4_CORE_BASE + 0x62000)
#define OMAP_UHH_CONFIG_BASE (OMAP_L4_CORE_BASE + 0x64000)
#define OMAP_OHCI_BASE (OMAP_L4_CORE_BASE + 0x64400)
#define OMAP_EHCI_BASE (OMAP_L4_CORE_BASE + 0x64800)
#define OMAP3_HSUSB_OTG_BASE (OMAP3_L4_CORE_BASE + 0xAB000)
#define OMAP3_USBTLL_BASE (OMAP3_L4_CORE_BASE + 0x62000)
#define OMAP3_UHH_CONFIG_BASE (OMAP3_L4_CORE_BASE + 0x64000)
#define OMAP3_OHCI_BASE (OMAP3_L4_CORE_BASE + 0x64400)
#define OMAP3_EHCI_BASE (OMAP3_L4_CORE_BASE + 0x64800)
/** Interrupt Vector base address */
#define OMAP_SRAM_BASE 0x40200000
#define OMAP_SRAM_INTVECT 0x4020F800
#define OMAP_SRAM_INTVECT_COPYSIZE 0x64
#define OMAP3_SRAM_BASE 0x40200000
#define OMAP3_SRAM_INTVECT 0x4020F800
#define OMAP3_SRAM_INTVECT_COPYSIZE 0x64
/** Gives the silicon revision */
#define OMAP_TAP_BASE (OMAP_L4_WKUP_BASE + 0xA000)
#define IDCODE_REG (OMAP_TAP_BASE + 0x204)
#define DIE_ID_0 (OMAP_TAP_BASE + 0x218)
#define DIE_ID_1 (OMAP_TAP_BASE + 0x21c)
#define DIE_ID_2 (OMAP_TAP_BASE + 0x220)
#define DIE_ID_3 (OMAP_TAP_BASE + 0x224)
#define OMAP3_TAP_BASE (OMAP3_L4_WKUP_BASE + 0xA000)
#define OMAP3_IDCODE_REG (OMAP3_TAP_BASE + 0x204)
#define OMAP3_DIE_ID_0 (OMAP3_TAP_BASE + 0x218)
#define OMAP3_DIE_ID_1 (OMAP3_TAP_BASE + 0x21c)
#define OMAP3_DIE_ID_2 (OMAP3_TAP_BASE + 0x220)
#define OMAP3_DIE_ID_3 (OMAP3_TAP_BASE + 0x224)
/** Masks to extract information from ID code register */
#define IDCODE_HAWKEYE_MASK 0x0FFFF000
@ -128,7 +128,11 @@
#define OMAP_SDRC_CS1 0xA0000000
/* PRM */
#define PRM_RSTCTRL_RESET 0x04
#define OMAP3_PRM_RSTCTRL_RESET 0x04
/* If Architecture specific init functions are present */
#ifndef __ASSEMBLY__
void omap3_core_init(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_OMAP3_H */

16
arch/arm/mach-omap/include/mach/omap3-smx.h
View File

@ -28,11 +28,11 @@
#define __ASM_ARCH_OMAP_SMX_H
/* SMX-APE */
#define PM_RT_APE_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x10000)
#define PM_GPMC_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12400)
#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12800)
#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12C00)
#define PM_IVA2_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x14000)
#define PM_RT_APE_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x10000)
#define PM_GPMC_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x12400)
#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x12800)
#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x12C00)
#define PM_IVA2_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x14000)
#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68)
#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50)
@ -54,9 +54,9 @@
#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58)
/* SMS */
#define SMS_SYSCONFIG (OMAP_SMS_BASE + 0x10)
#define SMS_RG_ATT0 (OMAP_SMS_BASE + 0x48)
#define SMS_CLASS_ARB0 (OMAP_SMS_BASE + 0xD0)
#define SMS_SYSCONFIG (OMAP3_SMS_BASE + 0x10)
#define SMS_RG_ATT0 (OMAP3_SMS_BASE + 0x48)
#define SMS_CLASS_ARB0 (OMAP3_SMS_BASE + 0xD0)
#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
#endif /* __ASM_ARCH_OMAP_SMX_H */

6
arch/arm/mach-omap/include/mach/omap4-clock.h
View File

@ -1,4 +1,7 @@
/* PRCM */
#ifndef __MACH_OMAP4_CLOCK_H
#define __MACH_OMAP4_CLOCK_H
/* PRCM */
#define CM_SYS_CLKSEL 0x4a306110
#define CM_SYS_CLKSEL_19M2 0x4
@ -337,3 +340,4 @@ void omap4_enable_gpio_clocks(void);
void omap4_enable_all_clocks(void);
void omap4_do_scale_tps62361(u32 reg, u32 volt_mv);
#endif /* __MACH_OMAP4_CLOCK_H */

87
arch/arm/mach-omap/include/mach/omap4-devices.h Normal file
View File

@ -0,0 +1,87 @@
#ifndef __MACH_OMAP4_DEVICES_H
#define __MACH_OMAP4_DEVICES_H
#include <driver.h>
#include <sizes.h>
#include <mach/devices.h>
#include <mach/omap4-silicon.h>
#include <mach/mcspi.h>
#include <mach/omap_hsmmc.h>
static inline void omap44xx_add_sram0(void)
{
return omap_add_sram0(OMAP44XX_SRAM_BASE, 48 * SZ_1K);
}
static inline struct device_d *omap44xx_add_uart1(void)
{
return omap_add_uart(0, OMAP44XX_UART1_BASE);
}
static inline struct device_d *omap44xx_add_uart2(void)
{
return omap_add_uart(1, OMAP44XX_UART2_BASE);
}
static inline struct device_d *omap44xx_add_uart3(void)
{
return omap_add_uart(2, OMAP44XX_UART3_BASE);
}
static inline struct device_d *omap44xx_add_mmc1(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap4-hsmmc", 0, NULL,
OMAP44XX_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
static inline struct device_d *omap44xx_add_mmc2(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap4-hsmmc", 1, NULL,
OMAP44XX_MMC2_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
static inline struct device_d *omap44xx_add_mmc3(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap4-hsmmc", 2, NULL,
OMAP44XX_MMC3_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
static inline struct device_d *omap44xx_add_mmc4(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap4-hsmmc", 3, NULL,
OMAP44XX_MMC4_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
static inline struct device_d *omap44xx_add_mmc5(struct omap_hsmmc_platform_data *pdata)
{
return add_generic_device("omap4-hsmmc", 4, NULL,
OMAP44XX_MMC5_BASE, SZ_4K, IORESOURCE_MEM, pdata);
}
static inline struct device_d *omap44xx_add_i2c1(void *pdata)
{
return omap_add_i2c(0, OMAP44XX_I2C1_BASE, pdata);
}
static inline struct device_d *omap44xx_add_i2c2(void *pdata)
{
return omap_add_i2c(1, OMAP44XX_I2C2_BASE, pdata);
}
static inline struct device_d *omap44xx_add_i2c3(void *pdata)
{
return omap_add_i2c(2, OMAP44XX_I2C3_BASE, pdata);
}
static inline struct device_d *omap44xx_add_i2c4(void *pdata)
{
return omap_add_i2c(3, OMAP44XX_I2C4_BASE, pdata);
}
static inline struct device_d *omap44xx_add_ehci(void *pdata)
{
return add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP44XX_EHCI_BASE,
OMAP44XX_EHCI_BASE + 0x10, pdata);
}
#endif /* __MACH_OMAP4_DEVICES_H */

42
arch/arm/mach-omap/include/mach/omap4-silicon.h
View File

@ -39,6 +39,10 @@
#define OMAP44XX_L4_WKUP_BASE 0x4A300000
#define OMAP44XX_L4_PER_BASE 0x48000000
#define OMAP44XX_SRAM_BASE 0x40300000
#define OMAP44XX_SRAM_BASE 0x40300000
/* EMIF and DMM registers */
#define OMAP44XX_EMIF1_BASE 0x4c000000
#define OMAP44XX_EMIF2_BASE 0x4d000000
@ -92,14 +96,14 @@
#define OMAP44XX_SCRM_AUXCLK3 (OMAP44XX_SCRM_BASE + 0x31c)
/* 32KTIMER */
#define OMAP_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
#define OMAP44XX_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
/* MMC */
#define OMAP44XX_MMC1_BASE (OMAP44XX_L4_PER_BASE + 0x09C100)
#define OMAP44XX_MMC2_BASE (OMAP44XX_L4_PER_BASE + 0x0B4100)
#define OMAP44XX_MMC3_BASE (OMAP44XX_L4_PER_BASE + 0x0AD100)
#define OMAP44XX_MMC4_BASE (OMAP44XX_L4_PER_BASE + 0x0D1100)
#define OMAP44XX_MMC5_BASE (OMAP44XX_L4_PER_BASE + 0x0D5100)
#define OMAP44XX_MMC1_BASE (OMAP44XX_L4_PER_BASE + 0x09C000)
#define OMAP44XX_MMC2_BASE (OMAP44XX_L4_PER_BASE + 0x0B4000)
#define OMAP44XX_MMC3_BASE (OMAP44XX_L4_PER_BASE + 0x0AD000)
#define OMAP44XX_MMC4_BASE (OMAP44XX_L4_PER_BASE + 0x0D1000)
#define OMAP44XX_MMC5_BASE (OMAP44XX_L4_PER_BASE + 0x0D5000)
/* GPIO
*
@ -117,7 +121,10 @@
#define OMAP44XX_GPIO6_BASE (OMAP44XX_L4_PER_BASE + 0x5D100)
/* GPMC */
#define OMAP_GPMC_BASE 0x50000000
#define OMAP44XX_GPMC_BASE 0x50000000
/* EHCI */
#define OMAP44XX_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00)
/* DMM */
#define OMAP44XX_DMM_BASE 0x4E000000
@ -147,20 +154,11 @@
*/
/* PRM */
#define PRM_BASE 0x4A306000
#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
#define OMAP44XX_PRM_BASE 0x4A306000
#define OMAP44XX_PRM_DEVICE_BASE (OMAP44XX_PRM_BASE + 0x1B00)
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
#ifndef __ASSEMBLY__
struct s32ktimer {
unsigned char res[0x10];
unsigned int s32k_cr; /* 0x10 */
};
#endif /* __ASSEMBLY__ */
#define OMAP44XX_PRM_RSTCTRL OMAP44XX_PRM_DEVICE_BASE
#define OMAP44XX_PRM_RSTCTRL_RESET 0x01
/*
* Non-secure SRAM Addresses
@ -193,6 +191,8 @@ struct s32ktimer {
#define OMAP4460_ES1_0 6
#define OMAP4460_ES1_1 7
#ifndef __ASSEMBLY__
struct ddr_regs {
u32 tim1;
u32 tim2;
@ -214,3 +214,5 @@ unsigned int omap4_revision(void);
noinline int omap4_scale_vcores(unsigned vsel0_pin);
#endif
#endif

2
arch/arm/mach-omap/include/mach/sdrc.h
View File

@ -24,7 +24,7 @@
#ifndef _ASM_ARCH_SDRC_H
#define _ASM_ARCH_SDRC_H
#define SDRC_REG(REGNAME) (OMAP_SDRC_BASE + OMAP_SDRC_##REGNAME)
#define OMAP3_SDRC_REG(REGNAME) (OMAP3_SDRC_BASE + OMAP_SDRC_##REGNAME)
#define OMAP_SDRC_SYSCONFIG (0x10)
#define OMAP_SDRC_STATUS (0x14)
#define OMAP_SDRC_CS_CFG (0x40)

33
arch/arm/mach-omap/include/mach/silicon.h
View File

@ -1,33 +0,0 @@
/*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
* Nishanth Menon <x0nishan@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_OMAP_SILICON_H
#define __ASM_ARCH_OMAP_SILICON_H
/* Each platform silicon header comes here */
#ifdef CONFIG_ARCH_OMAP3
#include <mach/omap3-silicon.h>
#endif
#ifdef CONFIG_ARCH_OMAP4
#include <mach/omap4-silicon.h>
#endif
/* If Architecture specific init functions are present */
#ifndef __ASSEMBLY__
void omap3_core_init(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_OMAP_SILICON_H */

1
arch/arm/mach-omap/include/mach/sys_info.h
View File

@ -85,7 +85,6 @@ u32 get_cpu_rev(void);
u32 get_sdr_cs_size(u32 offset);
u32 get_sdr_cs1_base(void);
inline u32 get_sysboot_value(void);
u32 get_gpmc0_base(void);
u32 get_base(void);
u32 running_in_flash(void);
u32 running_in_sram(void);

4
arch/arm/mach-omap/include/mach/timers.h
View File

@ -47,8 +47,4 @@
/* Enable sys_clk NO-prescale /1 */
#define GPT_EN ((0 << 2) | (0x1 << 1) | (0x1 << 0))
/** Sync 32Khz Timer registers */
#define S32K_CR (OMAP_32KTIMER_BASE + 0x10)
#define S32K_FREQUENCY 32768
#endif /*__ASM_ARCH_GPT_H */

4
arch/arm/mach-omap/include/mach/wdt.h
View File

@ -21,7 +21,9 @@
#define __ASM_ARCH_OMAP_WDT_H
/** Watchdog Register defines */
#define WDT_REG(REGNAME) (OMAP_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME)
#define OMAP3_WDT_REG(REGNAME) (OMAP3_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME)
#define AM33XX_WDT_REG(REGNAME) (AM33XX_WDT_BASE + OMAP_WDT_##REGNAME)
#define OMAP_WDT_WIDR (0x000)
#define OMAP_WDT_SYSCONFIG (0x010)
#define OMAP_WDT_WD_SYSSTATUS (0x014)

1
arch/arm/mach-omap/include/mach/xload.h
View File

@ -9,6 +9,7 @@ enum omap_boot_src {
OMAP_BOOTSRC_USB1,
};
enum omap_boot_src am33xx_bootsrc(void);
enum omap_boot_src omap3_bootsrc(void);
enum omap_boot_src omap4_bootsrc(void);

249
arch/arm/mach-omap/omap3_clock.c
View File

@ -32,12 +32,15 @@
#include <common.h>
#include <io.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/clocks.h>
#include <mach/omap3-clock.h>
#include <mach/timers.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
#define S32K_CR (OMAP3_32KTIMER_BASE + 0x10)
/* Following functions are exported from omap3_clock_core.S */
/* Helper functions */
static u32 get_osc_clk_speed(void);
@ -55,7 +58,7 @@ static u32 get_osc_clk_speed(void)
{
u32 start, cstart, cend, cdiff, cdiv, val;
val = readl(PRM_REG(CLKSRC_CTRL));
val = readl(OMAP3_PRM_REG(CLKSRC_CTRL));
if (val & SYSCLK_DIV_2)
cdiv = 2;
@ -69,28 +72,28 @@ static u32 get_osc_clk_speed(void)
cdiv = 1;
/* enable timer2 */
val = readl(CM_REG(CLKSEL_WKUP)) | (0x1 << 0);
writel(val, CM_REG(CLKSEL_WKUP)); /* select sys_clk for GPT1 */
val = readl(OMAP3_CM_REG(CLKSEL_WKUP)) | (0x1 << 0);
writel(val, OMAP3_CM_REG(CLKSEL_WKUP)); /* select sys_clk for GPT1 */
/* Enable I and F Clocks for GPT1 */
val = readl(CM_REG(ICLKEN_WKUP)) | (0x1 << 0) | (0x1 << 2);
writel(val, CM_REG(ICLKEN_WKUP));
val = readl(CM_REG(FCLKEN_WKUP)) | (0x1 << 0);
writel(val, CM_REG(FCLKEN_WKUP));
val = readl(OMAP3_CM_REG(ICLKEN_WKUP)) | (0x1 << 0) | (0x1 << 2);
writel(val, OMAP3_CM_REG(ICLKEN_WKUP));
val = readl(OMAP3_CM_REG(FCLKEN_WKUP)) | (0x1 << 0);
writel(val, OMAP3_CM_REG(FCLKEN_WKUP));
/* start counting at 0 */
writel(0, OMAP_GPTIMER1_BASE + TLDR);
writel(0, OMAP3_GPTIMER1_BASE + TLDR);
/* enable clock */
writel(GPT_EN, OMAP_GPTIMER1_BASE + TCLR);
writel(GPT_EN, OMAP3_GPTIMER1_BASE + TCLR);
/* enable 32kHz source - enabled out of reset */
/* determine sys_clk via gauging */
start = 20 + readl(S32K_CR); /* start time in 20 cycles */
while (readl(S32K_CR) < start) ; /* dead loop till start time */
/* get start sys_clk count */
cstart = readl(OMAP_GPTIMER1_BASE + TCRR);
cstart = readl(OMAP3_GPTIMER1_BASE + TCRR);
while (readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
/* get end sys_clk count */
cend = readl(OMAP_GPTIMER1_BASE + TCRR);
cend = readl(OMAP3_GPTIMER1_BASE + TCRR);
cdiff = cend - cstart; /* get elapsed ticks */
if (cdiv == 2)
@ -168,8 +171,8 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
if (running_in_sram()) {
sr32(CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_CKGEN), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
/*
* OMAP3430 ES1.0 Errata 1.50
@ -178,34 +181,34 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
*/
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
sr32(CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2 + 1);
sr32(CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2);
sr32(OMAP3_CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2 + 1);
sr32(OMAP3_CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
sr32(CM_REG(CLKSEL1_PLL), 27, 2, dp->m2);
sr32(OMAP3_CM_REG(CLKSEL1_PLL), 27, 2, dp->m2);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
sr32(CM_REG(CLKSEL1_PLL), 16, 11, dp->m);
sr32(OMAP3_CM_REG(CLKSEL1_PLL), 16, 11, dp->m);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
sr32(CM_REG(CLKSEL1_PLL), 8, 7, dp->n);
sr32(OMAP3_CM_REG(CLKSEL1_PLL), 8, 7, dp->n);
/* Set source CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(CM_REG(CLKSEL1_PLL), 6, 1, 0);
sr32(OMAP3_CM_REG(CLKSEL1_PLL), 6, 1, 0);
sr32(CM_REG(CLKSEL_CORE), 8, 4, CORE_SSI_DIV);
sr32(CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV);
sr32(CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV);
sr32(CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV);
sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV_34X);
sr32(CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 8, 4, CORE_SSI_DIV);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV);
sr32(OMAP3_CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV_34X);
sr32(OMAP3_CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
sr32(CM_REG(CLKEN_PLL), 4, 4, dp->fsel);
sr32(OMAP3_CM_REG(CLKEN_PLL), 4, 4, dp->fsel);
/* Lock Mode */
sr32(CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_CKGEN), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
} else if (running_in_flash()) {
/***Oopps.. Wrong .config!! *****/
hang();
@ -239,41 +242,41 @@ static void init_per_dpll_34x(u32 cpu_rev, u32 clk_sel)
* value and then write the default value.
*/
sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_STOP);
wait_on_value((0x1 << 1), 0, CM_REG(IDLEST_CKGEN), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL), 16, 3, PLL_STOP);
wait_on_value((0x1 << 1), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
/* Set M6 */
sr32(CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2 + 1);
sr32(CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2);
sr32(OMAP3_CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2 + 1);
sr32(OMAP3_CM_REG(CLKSEL1_EMU), 24, 5, PER_M6X2);
/* Set M5 */
sr32(CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2 + 1);
sr32(CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2);
sr32(OMAP3_CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2 + 1);
sr32(OMAP3_CM_REG(CLKSEL_CAM), 0, 5, PER_M5X2);
/* Set M4 */
sr32(CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2 + 1);
sr32(CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2);
sr32(OMAP3_CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2 + 1);
sr32(OMAP3_CM_REG(CLKSEL_DSS), 0, 5, PER_M4X2);
/* Set M3 */
sr32(CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2 + 1);
sr32(CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2);
sr32(OMAP3_CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2 + 1);
sr32(OMAP3_CM_REG(CLKSEL_DSS), 8, 5, PER_M3X2);
/* Set M2 */
sr32(CM_REG(CLKSEL3_PLL), 0, 5, dp->m2 + 1);
sr32(CM_REG(CLKSEL3_PLL), 0, 5, dp->m2);
sr32(OMAP3_CM_REG(CLKSEL3_PLL), 0, 5, dp->m2 + 1);
sr32(OMAP3_CM_REG(CLKSEL3_PLL), 0, 5, dp->m2);
/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
sr32(CM_REG(CLKSEL2_PLL), 8, 11, dp->m);
sr32(OMAP3_CM_REG(CLKSEL2_PLL), 8, 11, dp->m);
/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
sr32(CM_REG(CLKSEL2_PLL), 0, 7, dp->n);
sr32(OMAP3_CM_REG(CLKSEL2_PLL), 0, 7, dp->n);
/* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
sr32(CM_REG(CLKEN_PLL), 20, 4, dp->fsel);
sr32(OMAP3_CM_REG(CLKEN_PLL), 20, 4, dp->fsel);
/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_LOCK);
wait_on_value((0x1 << 1), 2, CM_REG(IDLEST_CKGEN), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL), 16, 3, PLL_LOCK);
wait_on_value((0x1 << 1), 2, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
}
static struct dpll_param mpu_dpll_param_34x_es1[] = {
@ -313,16 +316,16 @@ static void init_mpu_dpll_34x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
sr32(CM_REG(CLKSEL2_PLL_MPU), 0, 5, dp->m2);
sr32(OMAP3_CM_REG(CLKSEL2_PLL_MPU), 0, 5, dp->m2);
/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
sr32(CM_REG(CLKSEL1_PLL_MPU), 8, 11, dp->m);
sr32(OMAP3_CM_REG(CLKSEL1_PLL_MPU), 8, 11, dp->m);
/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
sr32(CM_REG(CLKSEL1_PLL_MPU), 0, 7, dp->n);
sr32(OMAP3_CM_REG(CLKSEL1_PLL_MPU), 0, 7, dp->n);
/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
sr32(CM_REG(CLKEN_PLL_MPU), 4, 4, dp->fsel);
sr32(OMAP3_CM_REG(CLKEN_PLL_MPU), 4, 4, dp->fsel);
}
static struct dpll_param iva_dpll_param_34x_es1[] = {
@ -359,24 +362,24 @@ static void init_iva_dpll_34x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_STOP);
wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_IVA2), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_STOP);
wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_PLL_IVA2), LDELAY);
/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
sr32(CM_REG(CLKSEL2_PLL_IVA2), 0, 5, dp->m2);
sr32(OMAP3_CM_REG(CLKSEL2_PLL_IVA2), 0, 5, dp->m2);
/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
sr32(CM_REG(CLKSEL1_PLL_IVA2), 8, 11, dp->m);
sr32(OMAP3_CM_REG(CLKSEL1_PLL_IVA2), 8, 11, dp->m);
/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
sr32(CM_REG(CLKSEL1_PLL_IVA2), 0, 7, dp->n);
sr32(OMAP3_CM_REG(CLKSEL1_PLL_IVA2), 0, 7, dp->n);
/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
sr32(CM_REG(CLKEN_PLL_IVA2), 4, 4, dp->fsel);
sr32(OMAP3_CM_REG(CLKEN_PLL_IVA2), 4, 4, dp->fsel);
/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_PLL_IVA2), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_PLL_IVA2), LDELAY);
}
/* FIXME: All values correspond to 26MHz only */
@ -401,37 +404,37 @@ static void init_core_dpll_36x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
if (running_in_sram()) {
sr32(CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_CKGEN), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
sr32(CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2);
sr32(OMAP3_CM_REG(CLKSEL1_EMU), 16, 5, CORE_M3X2);
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
sr32(CM_REG(CLKSEL1_PLL), 27, 5, dp->m2);
sr32(OMAP3_CM_REG(CLKSEL1_PLL), 27, 5, dp->m2);
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
sr32(CM_REG(CLKSEL1_PLL), 16, 11, dp->m);
sr32(OMAP3_CM_REG(CLKSEL1_PLL), 16, 11, dp->m);
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
sr32(CM_REG(CLKSEL1_PLL), 8, 7, dp->n);
sr32(OMAP3_CM_REG(CLKSEL1_PLL), 8, 7, dp->n);
/* Set source CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(CM_REG(CLKSEL1_PLL), 6, 1, 0);
sr32(OMAP3_CM_REG(CLKSEL1_PLL), 6, 1, 0);
sr32(CM_REG(CLKSEL_CORE), 8, 4, CORE_SSI_DIV);
sr32(CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV);
sr32(CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV);
sr32(CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV);
sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV_36X);
sr32(CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 8, 4, CORE_SSI_DIV);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV);
sr32(OMAP3_CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV_36X);
sr32(OMAP3_CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
sr32(CM_REG(CLKEN_PLL), 4, 4, dp->fsel);
sr32(OMAP3_CM_REG(CLKEN_PLL), 4, 4, dp->fsel);
/* Lock Mode */
sr32(CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_CKGEN), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
} else if (running_in_flash()) {
/***Oopps.. Wrong .config!! *****/
hang();
@ -459,36 +462,36 @@ static void init_per_dpll_36x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_STOP);
wait_on_value((0x1 << 1), 0, CM_REG(IDLEST_CKGEN), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL), 16, 3, PLL_STOP);
wait_on_value((0x1 << 1), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
/* Set M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
sr32(CM_REG(CLKSEL1_EMU), 24, 6, dp->m6);
sr32(OMAP3_CM_REG(CLKSEL1_EMU), 24, 6, dp->m6);
/* Set M5 (CLKSEL_CAM): CM_CLKSEL_CAM[0:5] */
sr32(CM_REG(CLKSEL_CAM), 0, 6, dp->m5);
sr32(OMAP3_CM_REG(CLKSEL_CAM), 0, 6, dp->m5);
/* Set M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
sr32(CM_REG(CLKSEL_DSS), 0, 6, dp->m4);
sr32(OMAP3_CM_REG(CLKSEL_DSS), 0, 6, dp->m4);
/* Set M3 (CLKSEL_DSS2): CM_CLKSEL_DSS[8:13] */
sr32(CM_REG(CLKSEL_DSS), 8, 6, dp->m3);
sr32(OMAP3_CM_REG(CLKSEL_DSS), 8, 6, dp->m3);
/* Set M2: CM_CLKSEL3_PLL[0:4] */
sr32(CM_REG(CLKSEL3_PLL), 0, 5, dp->m2);
sr32(OMAP3_CM_REG(CLKSEL3_PLL), 0, 5, dp->m2);
/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
sr32(CM_REG(CLKSEL2_PLL), 8, 12, dp->m);
sr32(OMAP3_CM_REG(CLKSEL2_PLL), 8, 12, dp->m);
/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
sr32(CM_REG(CLKSEL2_PLL), 0, 7, dp->n);
sr32(OMAP3_CM_REG(CLKSEL2_PLL), 0, 7, dp->n);
/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
sr32(CM_REG(CLKSEL_CORE), 12, 2, dp->m2div);
sr32(OMAP3_CM_REG(CLKSEL_CORE), 12, 2, dp->m2div);
/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
sr32(CM_REG(CLKEN_PLL), 16, 3, PLL_LOCK);
wait_on_value((0x1 << 1), 2, CM_REG(IDLEST_CKGEN), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL), 16, 3, PLL_LOCK);
wait_on_value((0x1 << 1), 2, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
}
/* FIXME: All values correspond to 26MHz only */
@ -513,16 +516,16 @@ static void init_mpu_dpll_36x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
sr32(CM_REG(CLKSEL2_PLL_MPU), 0, 5, dp->m2);
sr32(OMAP3_CM_REG(CLKSEL2_PLL_MPU), 0, 5, dp->m2);
/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
sr32(CM_REG(CLKSEL1_PLL_MPU), 8, 11, dp->m);
sr32(OMAP3_CM_REG(CLKSEL1_PLL_MPU), 8, 11, dp->m);
/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
sr32(CM_REG(CLKSEL1_PLL_MPU), 0, 7, dp->n);
sr32(OMAP3_CM_REG(CLKSEL1_PLL_MPU), 0, 7, dp->n);
/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
sr32(CM_REG(CLKEN_PLL_MPU), 4, 4, dp->fsel);
sr32(OMAP3_CM_REG(CLKEN_PLL_MPU), 4, 4, dp->fsel);
}
/* FIXME: All values correspond to 26MHz only */
@ -547,24 +550,24 @@ static void init_iva_dpll_36x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_STOP);
wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_IVA2), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_STOP);
wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_PLL_IVA2), LDELAY);
/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
sr32(CM_REG(CLKSEL2_PLL_IVA2), 0, 5, dp->m2);
sr32(OMAP3_CM_REG(CLKSEL2_PLL_IVA2), 0, 5, dp->m2);
/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
sr32(CM_REG(CLKSEL1_PLL_IVA2), 8, 11, dp->m);
sr32(OMAP3_CM_REG(CLKSEL1_PLL_IVA2), 8, 11, dp->m);
/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
sr32(CM_REG(CLKSEL1_PLL_IVA2), 0, 7, dp->n);
sr32(OMAP3_CM_REG(CLKSEL1_PLL_IVA2), 0, 7, dp->n);
/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
sr32(CM_REG(CLKEN_PLL_IVA2), 4, 4, dp->fsel);
sr32(OMAP3_CM_REG(CLKEN_PLL_IVA2), 4, 4, dp->fsel);
/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
sr32(CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_PLL_IVA2), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL_IVA2), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_PLL_IVA2), LDELAY);
}
/**
@ -587,7 +590,7 @@ void prcm_init(void)
osc_clk = get_osc_clk_speed();
get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
/* set input crystal speed */
sr32(PRM_REG(CLKSEL), 0, 3, sys_clkin_sel);
sr32(OMAP3_PRM_REG(CLKSEL), 0, 3, sys_clkin_sel);
/*
* OMAP3430:
@ -599,19 +602,19 @@ void prcm_init(void)
*/
if ((cpu_type != CPU_3630) && (sys_clkin_sel > 2)) {
/* input clock divider */
sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 2);
sr32(OMAP3_PRM_REG(CLKSRC_CTRL), 6, 2, 2);
clk_index = sys_clkin_sel / 2;
} else {
/* input clock divider */
sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 1);
sr32(OMAP3_PRM_REG(CLKSRC_CTRL), 6, 2, 1);
clk_index = sys_clkin_sel;
}
/*
* Unlock the MPU PLL. Run slow while clocks are being configured.
*/
sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS);
wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_MPU), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS);
wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_PLL_MPU), LDELAY);
if (cpu_type == CPU_3430) {
init_core_dpll_34x(cpu_rev, clk_index);
@ -633,12 +636,12 @@ void prcm_init(void)
/*
* Clock configuration complete. Lock MPU PLL.
*/
sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, CM_REG(IDLEST_PLL_MPU), LDELAY);
sr32(OMAP3_CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_PLL_MPU), LDELAY);
/* Set up GPTimers to sys_clk source only */
sr32(CM_REG(CLKSEL_PER), 0, 8, 0xff);
sr32(CM_REG(CLKSEL_WKUP), 0, 1, 1);
sr32(OMAP3_CM_REG(CLKSEL_PER), 0, 8, 0xff);
sr32(OMAP3_CM_REG(CLKSEL_WKUP), 0, 1, 1);
sdelay(5000);
@ -660,11 +663,11 @@ void prcm_init(void)
static void per_clocks_enable(void)
{
/* Enable GP2 timer. */
sr32(CM_REG(CLKSEL_PER), 0, 1, 0x1); /* GPT2 = sys clk */
sr32(CM_REG(ICLKEN_PER), 3, 1, 0x1); /* ICKen GPT2 */
sr32(CM_REG(FCLKEN_PER), 3, 1, 0x1); /* FCKen GPT2 */
sr32(OMAP3_CM_REG(CLKSEL_PER), 0, 1, 0x1); /* GPT2 = sys clk */
sr32(OMAP3_CM_REG(ICLKEN_PER), 3, 1, 0x1); /* ICKen GPT2 */
sr32(OMAP3_CM_REG(FCLKEN_PER), 3, 1, 0x1); /* FCKen GPT2 */
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
sr32(CM_REG(ICLKEN_WKUP), 2, 1, 0x1);
sr32(OMAP3_CM_REG(ICLKEN_WKUP), 2, 1, 0x1);
#define FCK_IVA2_ON 0x00000001
#define FCK_CORE1_ON 0x03fffe29
@ -678,18 +681,18 @@ static void per_clocks_enable(void)
#define ICK_CAM_ON 0x00000001
#define FCK_PER_ON 0x0003ffff
#define ICK_PER_ON 0x0003ffff
sr32(CM_REG(FCLKEN_IVA2), 0, 32, FCK_IVA2_ON);
sr32(CM_REG(FCLKEN1_CORE), 0, 32, FCK_CORE1_ON);
sr32(CM_REG(ICLKEN1_CORE), 0, 32, ICK_CORE1_ON);
sr32(CM_REG(ICLKEN2_CORE), 0, 32, ICK_CORE2_ON);
sr32(CM_REG(FCLKEN_WKUP), 0, 32, FCK_WKUP_ON);
sr32(CM_REG(ICLKEN_WKUP), 0, 32, ICK_WKUP_ON);
sr32(CM_REG(FCLKEN_DSS), 0, 32, FCK_DSS_ON);
sr32(CM_REG(ICLKEN_DSS), 0, 32, ICK_DSS_ON);
sr32(CM_REG(FCLKEN_CAM), 0, 32, FCK_CAM_ON);
sr32(CM_REG(ICLKEN_CAM), 0, 32, ICK_CAM_ON);
sr32(CM_REG(FCLKEN_PER), 0, 32, FCK_PER_ON);
sr32(CM_REG(ICLKEN_PER), 0, 32, ICK_PER_ON);
sr32(OMAP3_CM_REG(FCLKEN_IVA2), 0, 32, FCK_IVA2_ON);
sr32(OMAP3_CM_REG(FCLKEN1_CORE), 0, 32, FCK_CORE1_ON);
sr32(OMAP3_CM_REG(ICLKEN1_CORE), 0, 32, ICK_CORE1_ON);
sr32(OMAP3_CM_REG(ICLKEN2_CORE), 0, 32, ICK_CORE2_ON);
sr32(OMAP3_CM_REG(FCLKEN_WKUP), 0, 32, FCK_WKUP_ON);
sr32(OMAP3_CM_REG(ICLKEN_WKUP), 0, 32, ICK_WKUP_ON);
sr32(OMAP3_CM_REG(FCLKEN_DSS), 0, 32, FCK_DSS_ON);
sr32(OMAP3_CM_REG(ICLKEN_DSS), 0, 32, ICK_DSS_ON);
sr32(OMAP3_CM_REG(FCLKEN_CAM), 0, 32, FCK_CAM_ON);
sr32(OMAP3_CM_REG(ICLKEN_CAM), 0, 32, ICK_CAM_ON);
sr32(OMAP3_CM_REG(FCLKEN_PER), 0, 32, FCK_PER_ON);
sr32(OMAP3_CM_REG(ICLKEN_PER), 0, 32, ICK_PER_ON);
/* Settle down my friend */
sdelay(1000);

2
arch/arm/mach-omap/omap3_core.S
View File

@ -28,7 +28,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/wdt.h>
#include <mach/clocks.h>
#include <asm/barebox-arm-head.h>

60
arch/arm/mach-omap/omap3_generic.c
View File

@ -30,12 +30,13 @@
#include <common.h>
#include <init.h>
#include <io.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/gpmc.h>
#include <mach/sdrc.h>
#include <mach/control.h>
#include <mach/omap3-smx.h>
#include <mach/clocks.h>
#include <mach/omap3-clock.h>
#include <mach/wdt.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@ -52,7 +53,7 @@
*/
void __noreturn reset_cpu(unsigned long addr)
{
writel(PRM_RSTCTRL_RESET, PRM_REG(RSTCTRL));
writel(OMAP3_PRM_RSTCTRL_RESET, OMAP3_PRM_REG(RSTCTRL));
while (1);
}
@ -68,7 +69,7 @@ u32 get_cpu_type(void)
u32 idcode_val;
u16 hawkeye;
idcode_val = readl(IDCODE_REG);
idcode_val = readl(OMAP3_IDCODE_REG);
hawkeye = get_hawkeye(idcode_val);
@ -97,7 +98,7 @@ u32 get_cpu_rev(void)
u32 idcode_val;
u32 version, retval;
idcode_val = readl(IDCODE_REG);
idcode_val = readl(OMAP3_IDCODE_REG);
version = get_version(idcode_val);
@ -166,7 +167,7 @@ u32 get_sdr_cs_size(u32 offset)
{
u32 size;
/* get ram size field */
size = readl(SDRC_REG(MCFG_0) + offset) >> 8;
size = readl(OMAP3_SDRC_REG(MCFG_0) + offset) >> 8;
size &= 0x3FF; /* remove unwanted bits */
size *= 2 * (1024 * 1024); /* find size in MB */
return size;
@ -182,7 +183,7 @@ u32 get_sdr_cs1_base(void)
u32 base;
u32 cs_cfg;
cs_cfg = readl(SDRC_REG(CS_CFG));
cs_cfg = readl(OMAP3_SDRC_REG(CS_CFG));
/* get ram size field */
base = (cs_cfg & 0x0000000F) << 2; /* get CS1STARTHIGH */
base = base | ((cs_cfg & 0x00000300) >> 8); /* get CS1STARTLOW */
@ -200,26 +201,7 @@ EXPORT_SYMBOL(get_sdr_cs1_base);
*/
inline u32 get_sysboot_value(void)
{
return (0x0000003F & readl(CONTROL_REG(STATUS)));
}
/**
* @brief Return the current CS0 base address
*
* Return current address hardware will be
* fetching from. The below effectively gives what is correct, its a bit
* mis-leading compared to the TRM. For the most general case the mask
* needs to be also taken into account this does work in practice.
*
* @return base address
*/
u32 get_gpmc0_base(void)
{
u32 b;
b = readl(GPMC_REG(CONFIG7_0));
b &= 0x1F; /* keep base [5:0] */
b = b << 24; /* ret 0x0b000000 */
return b;
return (0x0000003F & readl(OMAP3_CONTROL_REG(STATUS)));
}
/**
@ -308,7 +290,7 @@ u32 get_boot_type(void)
u32 get_device_type(void)
{
int mode;
mode = readl(CONTROL_REG(STATUS)) & (DEVICE_MASK);
mode = readl(OMAP3_CONTROL_REG(STATUS)) & (DEVICE_MASK);
return (mode >>= 8);
}
@ -393,17 +375,17 @@ static void watchdog_init(void)
{
int pending = 1;
sr32(CM_REG(FCLKEN_WKUP), 5, 1, 1);
sr32(CM_REG(ICLKEN_WKUP), 5, 1, 1);
wait_on_value((0x1 << 5), 0x20, CM_REG(IDLEST_WKUP), 5);
sr32(OMAP3_CM_REG(FCLKEN_WKUP), 5, 1, 1);
sr32(OMAP3_CM_REG(ICLKEN_WKUP), 5, 1, 1);
wait_on_value((0x1 << 5), 0x20, OMAP3_CM_REG(IDLEST_WKUP), 5);
writel(WDT_DISABLE_CODE1, WDT_REG(WSPR));
writel(WDT_DISABLE_CODE1, OMAP3_WDT_REG(WSPR));
do {
pending = readl(WDT_REG(WWPS));
pending = readl(OMAP3_WDT_REG(WWPS));
} while (pending);
writel(WDT_DISABLE_CODE2, WDT_REG(WSPR));
writel(WDT_DISABLE_CODE2, OMAP3_WDT_REG(WSPR));
}
/**
@ -512,17 +494,17 @@ const struct gpmc_config omap3_nand_cfg = {
#ifndef __PBL__
static int omap3_gpio_init(void)
{
add_generic_device("omap-gpio", 0, NULL, OMAP_GPIO1_BASE,
add_generic_device("omap-gpio", 0, NULL, OMAP3_GPIO1_BASE,
0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 1, NULL, OMAP_GPIO2_BASE,
add_generic_device("omap-gpio", 1, NULL, OMAP3_GPIO2_BASE,
0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 2, NULL, OMAP_GPIO3_BASE,
add_generic_device("omap-gpio", 2, NULL, OMAP3_GPIO3_BASE,
0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 3, NULL, OMAP_GPIO4_BASE,
add_generic_device("omap-gpio", 3, NULL, OMAP3_GPIO4_BASE,
0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 4, NULL, OMAP_GPIO5_BASE,
add_generic_device("omap-gpio", 4, NULL, OMAP3_GPIO5_BASE,
0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 5, NULL, OMAP_GPIO6_BASE,
add_generic_device("omap-gpio", 5, NULL, OMAP3_GPIO6_BASE,
0xf00, IORESOURCE_MEM, NULL);
return 0;

3
arch/arm/mach-omap/omap4_clock.c
View File

@ -1,8 +1,9 @@
#include <common.h>
#include <io.h>
#include <mach/syslib.h>
#include <mach/silicon.h>
#include <mach/omap4-silicon.h>
#include <mach/clocks.h>
#include <mach/omap4-clock.h>
#define LDELAY 12000000

6
arch/arm/mach-omap/omap4_generic.c
View File

@ -1,8 +1,8 @@
#include <common.h>
#include <init.h>
#include <io.h>
#include <mach/clocks.h>
#include <mach/silicon.h>
#include <mach/omap4-clock.h>
#include <mach/omap4-silicon.h>
#include <mach/omap4-mux.h>
#include <mach/syslib.h>
#include <mach/xload.h>
@ -36,7 +36,7 @@
void __noreturn reset_cpu(unsigned long addr)
{
writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
writel(OMAP44XX_PRM_RSTCTRL_RESET, OMAP44XX_PRM_RSTCTRL);
while (1);
}

32
arch/arm/mach-omap/omap_devices.c Normal file
View File

@ -0,0 +1,32 @@
#include <driver.h>
#include <ns16550.h>
#include <asm/armlinux.h>
#include <mach/omap3-devices.h>
void omap_add_ram0(resource_size_t size)
{
arm_add_mem_device("ram0", 0x80000000, size);
}
void omap_add_sram0(resource_size_t base, resource_size_t size)
{
add_mem_device("sram0", base, size, IORESOURCE_MEM_WRITEABLE);
}
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.shift = 2,
};
struct device_d *omap_add_uart(int id, unsigned long base)
{
return add_ns16550_device(id, base, 1024,
IORESOURCE_MEM_8BIT, &serial_plat);
}
struct device_d *omap_add_i2c(int id, unsigned long base, void *pdata)
{
return add_generic_device("i2c-omap", id, NULL, base, SZ_4K,
IORESOURCE_MEM, pdata);
}

18
arch/arm/mach-omap/s32k_clksource.c
View File

@ -25,12 +25,19 @@
#include <clock.h>
#include <init.h>
#include <io.h>
#include <mach/silicon.h>
#include <mach/omap3-silicon.h>
#include <mach/omap4-silicon.h>
#include <mach/clocks.h>
#include <mach/timers.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
/** Sync 32Khz Timer registers */
#define S32K_CR 0x10
#define S32K_FREQUENCY 32768
static void __iomem *timerbase;
/**
* @brief Provide a simple clock read
*
@ -41,7 +48,7 @@
*/
static uint64_t s32k_clocksource_read(void)
{
return readl(S32K_CR);
return readl(timerbase + S32K_CR);
}
/* A bit obvious isn't it? */
@ -62,6 +69,13 @@ static struct clocksource s32k_cs = {
*/
static int s32k_clocksource_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_OMAP3))
timerbase = (void *)OMAP3_32KTIMER_BASE;
else if (IS_ENABLED(CONFIG_ARCH_OMAP4))
timerbase = (void *)OMAP44XX_32KTIMER_BASE;
else
BUG();
s32k_cs.mult = clocksource_hz2mult(S32K_FREQUENCY, s32k_cs.shift);
return init_clock(&s32k_cs);

2
arch/arm/mach-omap/xload.c
View File

@ -163,6 +163,8 @@ enum omap_boot_src omap_bootsrc(void)
return omap3_bootsrc();
#elif defined(CONFIG_ARCH_OMAP4)
return omap4_bootsrc();
#elif defined(CONFIG_ARCH_AM33XX)
return am33xx_bootsrc();
#endif
}

2
drivers/mci/Kconfig
View File

@ -67,7 +67,7 @@ config MCI_IMX_ESDHC_PIO
config MCI_OMAP_HSMMC
bool "OMAP HSMMC"
depends on ARCH_OMAP4 || ARCH_OMAP3
depends on ARCH_OMAP4 || ARCH_OMAP3 || ARCH_AM33XX
help
Enable this entry to add support to read and write SD cards on
both OMAP3 and OMAP4 based systems.

45
drivers/mci/omap_hsmmc.c
View File

@ -59,6 +59,18 @@ struct hsmmc {
unsigned int capa; /* 0x140 */
};
struct omap_mmc_driver_data {
unsigned long reg_ofs;
};
static struct omap_mmc_driver_data omap3_data = {
.reg_ofs = 0,
};
static struct omap_mmc_driver_data omap4_data = {
.reg_ofs = 0x100,
};
/*
* OMAP HS MMC Bit definitions
*/
@ -175,6 +187,7 @@ struct omap_hsmmc {
struct mci_host mci;
struct device_d *dev;
struct hsmmc *base;
void __iomem *iobase;
};
#define to_hsmmc(mci) container_of(mci, struct omap_hsmmc, mci)
@ -565,6 +578,13 @@ static int omap_mmc_probe(struct device_d *dev)
{
struct omap_hsmmc *hsmmc;
struct omap_hsmmc_platform_data *pdata;
struct omap_mmc_driver_data *drvdata;
unsigned long reg_ofs = 0;
int ret;
ret = dev_get_drvdata(dev, (unsigned long *)&drvdata);
if (!ret)
reg_ofs = drvdata->reg_ofs;
hsmmc = xzalloc(sizeof(*hsmmc));
@ -575,7 +595,8 @@ static int omap_mmc_probe(struct device_d *dev)
hsmmc->mci.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
hsmmc->mci.hw_dev = dev;
hsmmc->base = dev_request_mem_region(dev, 0);
hsmmc->iobase = dev_request_mem_region(dev, 0);
hsmmc->base = hsmmc->iobase + reg_ofs;
hsmmc->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
@ -592,16 +613,28 @@ static int omap_mmc_probe(struct device_d *dev)
return 0;
}
static struct platform_device_id omap_mmc_ids[] = {
{
.name = "omap3-hsmmc",
.driver_data = (unsigned long)&omap3_data,
}, {
.name = "omap4-hsmmc",
.driver_data = (unsigned long)&omap4_data,
}, {
/* sentinel */
},
};
static struct driver_d omap_mmc_driver = {
.name = "omap-hsmmc",
.probe = omap_mmc_probe,
.name = "omap-hsmmc",
.probe = omap_mmc_probe,
.id_table = omap_mmc_ids,
};
static int omap_mmc_init_driver(void)
{
platform_driver_register(&omap_mmc_driver);
return 0;
platform_driver_register(&omap_mmc_driver);
return 0;
}
device_initcall(omap_mmc_init_driver);

1
drivers/mtd/nand/nand_omap_gpmc.c
View File

@ -68,7 +68,6 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <io.h>
#include <mach/silicon.h>
#include <mach/gpmc.h>
#include <mach/gpmc_nand.h>

76
drivers/usb/host/ehci-omap.c
View File

@ -30,37 +30,37 @@ void omap_usb_utmi_init(struct omap_hcd *omap, u8 tll_channel_mask)
/* Program the 3 TLL channels upfront */
for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
reg = __raw_readl(OMAP3_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
/* Disable AutoIdle, BitStuffing and use SDR Mode */
reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
| OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
__raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
__raw_writel(reg, OMAP3_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
}
/* Program Common TLL register */
reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_SHARED_CONF);
reg = __raw_readl(OMAP3_USBTLL_BASE + OMAP_TLL_SHARED_CONF);
reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
| OMAP_TLL_SHARED_CONF_USB_DIVRATION
| OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
__raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_SHARED_CONF);
__raw_writel(reg, OMAP3_USBTLL_BASE + OMAP_TLL_SHARED_CONF);
/* Enable channels now */
for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
reg = __raw_readl(OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
reg = __raw_readl(OMAP3_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
/* Enable only the reg that is needed */
if (!(tll_channel_mask & 1<<i))
continue;
reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
__raw_writel(reg, OMAP_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
__raw_writel(reg, OMAP3_USBTLL_BASE + OMAP_TLL_CHANNEL_CONF(i));
__raw_writeb(0xbe,
OMAP_USBTLL_BASE + OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
OMAP3_USBTLL_BASE + OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
}
}
@ -78,56 +78,56 @@ int ehci_omap_init(struct omap_hcd *omap)
}
v = __raw_readl(CM_REG(CLKSEL4_PLL));
v = __raw_readl(OMAP3_CM_REG(CLKSEL4_PLL));
v |= (12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT);
v |= (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT);
__raw_writel(v, CM_REG(CLKSEL4_PLL));
__raw_writel(v, OMAP3_CM_REG(CLKSEL4_PLL));
v = __raw_readl(CM_REG(CLKSEL5_PLL));
v = __raw_readl(OMAP3_CM_REG(CLKSEL5_PLL));
v |= (1 << OMAP3430ES2_DIV_120M_SHIFT);
__raw_writel(v, CM_REG(CLKSEL5_PLL));
__raw_writel(v, OMAP3_CM_REG(CLKSEL5_PLL));
v = __raw_readl(CM_REG(CLKEN2_PLL));
v = __raw_readl(OMAP3_CM_REG(CLKEN2_PLL));
v |= (7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT);
v |= (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT);
__raw_writel(v, CM_REG(CLKEN2_PLL));
__raw_writel(v, OMAP3_CM_REG(CLKEN2_PLL));
/* PRCM settings for USBHOST:
* Interface clk un-related to domain transition
*/
v = __raw_readl(CM_REG(AIDLE_USBH));
v = __raw_readl(OMAP3_CM_REG(AIDLE_USBH));
v |= (0 << OMAP3430ES2_AUTO_USBHOST_SHIFT);
__raw_writel(v, CM_REG(AIDLE_USBH));
__raw_writel(v, OMAP3_CM_REG(AIDLE_USBH));
/* Disable sleep dependency with MPU and IVA */
v = __raw_readl(CM_REG(SLEEPD_USBH));
v = __raw_readl(OMAP3_CM_REG(SLEEPD_USBH));
v |= (0 << OMAP3430ES2_EN_MPU_SHIFT);
v |= (0 << OMAP3430ES2_EN_IVA2_SHIFT);
__raw_writel(v, CM_REG(SLEEPD_USBH));
__raw_writel(v, OMAP3_CM_REG(SLEEPD_USBH));
/* Disable Automatic transition of clock */
v = __raw_readl(CM_REG(CLKSTCTRL_USBH));
v = __raw_readl(OMAP3_CM_REG(CLKSTCTRL_USBH));
v |= (0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT);
__raw_writel(v, CM_REG(CLKSTCTRL_USBH));
__raw_writel(v, OMAP3_CM_REG(CLKSTCTRL_USBH));
/* Enable Clocks for USBHOST */
/* enable usbhost_ick */
v = __raw_readl(CM_REG(ICLKEN_USBH));
v = __raw_readl(OMAP3_CM_REG(ICLKEN_USBH));
v |= (1 << OMAP3430ES2_EN_USBHOST_SHIFT);
__raw_writel(v, CM_REG(ICLKEN_USBH));
__raw_writel(v, OMAP3_CM_REG(ICLKEN_USBH));
/* enable usbhost_120m_fck */
v = __raw_readl(CM_REG(FCLKEN_USBH));
v = __raw_readl(OMAP3_CM_REG(FCLKEN_USBH));
v |= (1 << OMAP3430ES2_EN_USBHOST2_SHIFT);
__raw_writel(v, CM_REG(FCLKEN_USBH));
__raw_writel(v, OMAP3_CM_REG(FCLKEN_USBH));
/* enable usbhost_48m_fck */
v = __raw_readl(CM_REG(FCLKEN_USBH));
v = __raw_readl(OMAP3_CM_REG(FCLKEN_USBH));
v |= (1 << OMAP3430ES2_EN_USBHOST1_SHIFT);
__raw_writel(v, CM_REG(FCLKEN_USBH));
__raw_writel(v, OMAP3_CM_REG(FCLKEN_USBH));
if (omap->phy_reset) {
/* Refer: ISSUE1 */
@ -144,28 +144,28 @@ int ehci_omap_init(struct omap_hcd *omap)
}
/* enable usbtll_fck */
v = __raw_readl(CM_REG(FCLKEN3_CORE));
v = __raw_readl(OMAP3_CM_REG(FCLKEN3_CORE));
v |= (1 << OMAP3430ES2_EN_USBTLL_SHIFT);
__raw_writel(v, CM_REG(FCLKEN3_CORE));
__raw_writel(v, OMAP3_CM_REG(FCLKEN3_CORE));
/* Configure TLL for 60Mhz clk for ULPI */
/* enable usbtll_ick */
v = __raw_readl(CM_REG(ICLKEN3_CORE));
v = __raw_readl(OMAP3_CM_REG(ICLKEN3_CORE));
v |= (1 << OMAP3430ES2_EN_USBTLL_SHIFT);
__raw_writel(v, CM_REG(ICLKEN3_CORE));
__raw_writel(v, OMAP3_CM_REG(ICLKEN3_CORE));
v = __raw_readl(CM_REG(AIDLE3_CORE));
v = __raw_readl(OMAP3_CM_REG(AIDLE3_CORE));
v |= (0 << OMAP3430ES2_AUTO_USBTLL_SHIFT);
__raw_writel(v, CM_REG(AIDLE3_CORE));
__raw_writel(v, OMAP3_CM_REG(AIDLE3_CORE));
/* perform TLL soft reset, and wait until reset is complete */
__raw_writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
OMAP_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
/* Wait for TLL reset to complete */
start = get_time_ns();
while (!(__raw_readl(OMAP_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
while (!(__raw_readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
& OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
if (is_timeout(start, timeout * USECOND)) {
return -ETIMEDOUT;
@ -175,18 +175,18 @@ int ehci_omap_init(struct omap_hcd *omap)
/* (1<<3) = no idle mode only for initial debugging */
__raw_writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
OMAP_USBTLL_SYSCONFIG_CACTIVITY, OMAP_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
OMAP_USBTLL_SYSCONFIG_CACTIVITY, OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
/* Put UHH in NoIdle/NoStandby mode */
v = __raw_readl(OMAP_UHH_CONFIG_BASE + OMAP_UHH_SYSCONFIG);
v = __raw_readl(OMAP3_UHH_CONFIG_BASE + OMAP_UHH_SYSCONFIG);
v |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
| OMAP_UHH_SYSCONFIG_SIDLEMODE
| OMAP_UHH_SYSCONFIG_CACTIVITY
| OMAP_UHH_SYSCONFIG_MIDLEMODE);
v &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
__raw_writel(v, OMAP_UHH_CONFIG_BASE + OMAP_UHH_SYSCONFIG);
__raw_writel(v, OMAP3_UHH_CONFIG_BASE + OMAP_UHH_SYSCONFIG);
v = __raw_readl(OMAP_UHH_CONFIG_BASE + OMAP_UHH_HOSTCONFIG);
v = __raw_readl(OMAP3_UHH_CONFIG_BASE + OMAP_UHH_HOSTCONFIG);
/* setup ULPI bypass and burst configurations */
v |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
@ -225,7 +225,7 @@ int ehci_omap_init(struct omap_hcd *omap)
v |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
}
__raw_writel(v, OMAP_UHH_CONFIG_BASE + OMAP_UHH_HOSTCONFIG);
__raw_writel(v, OMAP3_UHH_CONFIG_BASE + OMAP_UHH_HOSTCONFIG);
if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
(omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||