From db62ca84fb097fa0916e948f300334e7b7f07448 Mon Sep 17 00:00:00 2001 From: Ian Abbott Date: Mon, 7 Nov 2016 18:16:21 +0000 Subject: [PATCH] net/designware: Consecutive writes to the same register to be avoided There are a few registers where consecutive writes to the same location should be avoided or have a delay. According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required: DMA Registers: Register 0 Bit 7 Register 6 All bits except for 24, 16-13, 2-1. GMAC Registers: Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3. [Original U-Boot patch by Dinh Nguyen ] Signed-off-by: Ian Abbott Signed-off-by: Sascha Hauer --- drivers/net/designware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 1d662a71d..21fb44ef2 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -248,8 +248,8 @@ static int dwc_ether_init(struct eth_device *dev) dev->set_ethaddr(dev, priv->macaddr); writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); - writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); - writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | + TXSECONDFRAME, &dma_p->opmode); writel(FRAMEBURSTENABLE | DISABLERXOWN, &mac_p->conf); return 0; }