sysmo-bts
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barebox
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Merge branch 'next'

This commit is contained in:
Sascha Hauer 2011-08-04 14:49:33 +02:00
parent 8949efd0e1 454f331bfe
commit db879ec1a9
195 changed files with 5429 additions and 4273 deletions
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1
Documentation/boards.dox
View File

@ -18,6 +18,7 @@ ARM type:
@li @subpage the3stack
@li @subpage mx23_evk
@li @subpage board_babage
@li @subpage board_loco
@li @subpage chumbyone
@li @subpage scb9328
@li @subpage netx

1
arch/arm/Makefile
View File

@ -102,6 +102,7 @@ board-$(CONFIG_MACH_MX23EVK) := freescale-mx23-evk
board-$(CONFIG_MACH_CHUMBY) := chumby_falconwing
board-$(CONFIG_MACH_TX28) := karo-tx28
board-$(CONFIG_MACH_FREESCALE_MX51_PDK) := freescale-mx51-pdk
board-$(CONFIG_MACH_FREESCALE_MX53_LOCO) := freescale-mx53-loco
board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
board-$(CONFIG_MACH_MINI2440) := mini2440
board-$(CONFIG_MACH_VERSATILEPB) := versatile

83
arch/arm/boards/a9m2410/a9m2410.c
View File

@ -35,44 +35,14 @@
#include <mach/s3c24x0-iomap.h>
#include <mach/s3c24x0-nand.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "ram",
.map_base = CS6_BASE,
.platform_data = &ram_pdata,
};
// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
};
static struct device_d nand_dev = {
.id = -1,
.name = "s3c24x0_nand",
.map_base = S3C24X0_NAND_BASE,
.platform_data = &nand_info,
};
/*
* SMSC 91C111 network controller on the baseboard
* connected to CS line 1 and interrupt line
* GPIO3, data width is 32 bit
*/
static struct device_d network_dev = {
.id = -1,
.name = "smc91c111",
.map_base = CS1_BASE + 0x300,
.size = 16,
};
static int a9m2410_devices_init(void)
static int a9m2410_mem_init(void)
{
resource_size_t size = 0;
uint32_t reg;
/*
@ -83,25 +53,25 @@ static int a9m2410_devices_init(void)
switch (reg &= 0x7) {
case 0:
sdram_dev.size = 32 * 1024 * 1024;
size = 32 * 1024 * 1024;
break;
case 1:
sdram_dev.size = 64 * 1024 * 1024;
size = 64 * 1024 * 1024;
break;
case 2:
sdram_dev.size = 128 * 1024 * 1024;
size = 128 * 1024 * 1024;
break;
case 4:
sdram_dev.size = 2 * 1024 * 1024;
size = 2 * 1024 * 1024;
break;
case 5:
sdram_dev.size = 4 * 1024 * 1024;
size = 4 * 1024 * 1024;
break;
case 6:
sdram_dev.size = 8 * 1024 * 1024;
size = 8 * 1024 * 1024;
break;
case 7:
sdram_dev.size = 16 * 1024 * 1024;
size = 16 * 1024 * 1024;
break;
}
@ -130,6 +100,16 @@ static int a9m2410_devices_init(void)
*/
writel(0x40140, MISCCR);
arm_add_mem_device("ram0", CS6_BASE, size);
return 0;
}
mem_initcall(a9m2410_mem_init);
static int a9m2410_devices_init(void)
{
uint32_t reg;
/* ----------- configure the access to the outer space ---------- */
reg = readl(BWSCON);
@ -151,9 +131,15 @@ static int a9m2410_devices_init(void)
writel(reg, MISCCR);
/* ----------- the devices the boot loader should work with -------- */
register_device(&nand_dev);
register_device(&sdram_dev);
register_device(&network_dev);
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
IORESOURCE_MEM, &nand_info);
/*
* SMSC 91C111 network controller on the baseboard
* connected to CS line 1 and interrupt line
* GPIO3, data width is 32 bit
*/
add_generic_device("smc91c111", -1, NULL, CS1_BASE + 0x300, 16,
IORESOURCE_MEM, NULL);
#ifdef CONFIG_NAND
/* ----------- add some vital partitions -------- */
@ -164,8 +150,7 @@ static int a9m2410_devices_init(void)
dev_add_bb_dev("env_raw", "env0");
#endif
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
armlinux_set_bootparams((void*)CS6_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_A9M2410);
return 0;
@ -180,16 +165,10 @@ void __bare_init nand_boot(void)
}
#endif
static struct device_d a9m2410_serial_device = {
.id = -1,
.name = "s3c24x0_serial",
.map_base = UART1_BASE,
.size = UART1_SIZE,
};
static int a9m2410_console_init(void)
{
register_device(&a9m2410_serial_device);
add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}

70
arch/arm/boards/a9m2440/a9m2440.c
View File

@ -38,41 +38,10 @@
#include "baseboards.h"
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = CS6_BASE,
.platform_data = &ram_pdata,
};
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
};
static struct device_d nand_dev = {
.id = -1,
.name = "s3c24x0_nand",
.map_base = S3C24X0_NAND_BASE,
.platform_data = &nand_info,
};
/*
* cs8900 network controller onboard
* Connected to CS line 5 + A24 and interrupt line EINT9,
* data width is 16 bit
*/
static struct device_d network_dev = {
.id = -1,
.name = "cs8900",
.map_base = CS5_BASE + (1 << 24) + 0x300,
.size = 16,
};
static int a9m2440_check_for_ram(uint32_t addr)
{
uint32_t tmp1, tmp2;
@ -103,10 +72,8 @@ static void a9m2440_disable_second_sdram_bank(void)
writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable clock */
}
static int a9m2440_devices_init(void)
static int a9m2440_mem_init(void)
{
uint32_t reg;
/*
* The special SDRAM setup code for this machine will always enable
* both SDRAM banks. But the second SDRAM device may not exists!
@ -136,7 +103,15 @@ static int a9m2440_devices_init(void)
break;
}
sdram_dev.size = s3c24x0_get_memory_size();
arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
return 0;
}
mem_initcall(a9m2440_mem_init);
static int a9m2440_devices_init(void)
{
uint32_t reg;
/* ----------- configure the access to the outer space ---------- */
reg = readl(BWSCON);
@ -158,9 +133,15 @@ static int a9m2440_devices_init(void)
writel(reg, MISCCR);
/* ----------- the devices the boot loader should work with -------- */
register_device(&nand_dev);
register_device(&sdram_dev);
register_device(&network_dev);
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
IORESOURCE_MEM, &nand_info);
/*
* cs8900 network controller onboard
* Connected to CS line 5 + A24 and interrupt line EINT9,
* data width is 16 bit
*/
add_generic_device("cs8900", -1, NULL, CS5_BASE + (1 << 24) + 0x300, 16,
IORESOURCE_MEM, NULL);
#ifdef CONFIG_NAND
/* ----------- add some vital partitions -------- */
@ -170,8 +151,7 @@ static int a9m2440_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
armlinux_set_bootparams((void*)CS6_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_A9M2440);
return 0;
@ -186,16 +166,10 @@ void __bare_init nand_boot(void)
}
#endif
static struct device_d a9m2440_serial_device = {
.id = -1,
.name = "s3c24x0_serial",
.map_base = UART1_BASE,
.size = UART1_SIZE,
};
static int a9m2440_console_init(void)
{
register_device(&a9m2440_serial_device);
add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}

18
arch/arm/boards/at91rm9200ek/init.c
View File

@ -34,17 +34,19 @@
#include <mach/gpio.h>
#include <mach/io.h>
static struct device_d cfi_dev = {
.id = 0,
.name = "cfi_flash",
.map_base = AT91_CHIPSELECT_0,
};
static struct at91_ether_platform_data ether_pdata = {
.flags = AT91SAM_ETHER_RMII,
.phy_addr = 0,
};
static int at91rm9200ek_mem_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
return 0;
}
mem_initcall(at91rm9200ek_mem_init);
static int at91rm9200ek_devices_init(void)
{
/*
@ -53,9 +55,9 @@ static int at91rm9200ek_devices_init(void)
*/
at91_set_gpio_output(AT91_PIN_PA23, 1);
at91_add_device_sdram(64 * 1024 * 1024);
at91_add_device_eth(&ether_pdata);
register_device(&cfi_dev);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
#if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");

9
arch/arm/boards/at91sam9260ek/init.c
View File

@ -141,13 +141,20 @@ static void at91sam9260ek_phy_reset(void)
AT91_RSTC_URSTEN);
}
static int at91sam9260ek_mem_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
return 0;
}
mem_initcall(at91sam9260ek_mem_init);
static int at91sam9260ek_devices_init(void)
{
ek_add_device_nand();
at91sam9260ek_phy_reset();
at91_add_device_eth(&macb_pdata);
at91_add_device_sdram(64 * 1024 * 1024);
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
ek_set_board_type();

23
arch/arm/boards/at91sam9261ek/init.c
View File

@ -89,20 +89,9 @@ static void ek_add_device_nand(void)
*/
#if defined(CONFIG_DRIVER_NET_DM9000)
static struct dm9000_platform_data dm9000_data = {
.iobase = AT91_CHIPSELECT_2,
.iodata = AT91_CHIPSELECT_2 + 4,
.buswidth = DM9000_WIDTH_16,
.srom = 0,
};
static struct device_d dm9000_dev = {
.id = 0,
.name = "dm9000",
.map_base = AT91_CHIPSELECT_2,
.size = 8,
.platform_data = &dm9000_data,
};
/*
* SMC timings for the DM9000.
* Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
@ -136,16 +125,24 @@ static void __init ek_add_device_dm9000(void)
/* Configure Interrupt pin as input, no pull-up */
at91_set_gpio_input(AT91_PIN_PC11, 0);
register_device(&dm9000_dev);
add_dm9000_device(0, AT91_CHIPSELECT_2, AT91_CHIPSELECT_2 + 4,
IORESOURCE_MEM_16BIT, &dm9000_data);
}
#else
static void __init ek_add_device_dm9000(void) {}
#endif /* CONFIG_DRIVER_NET_DM9000 */
static int at91sam9261ek_mem_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
return 0;
}
mem_initcall(at91sam9261ek_mem_init);
static int at91sam9261ek_devices_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
ek_add_device_nand();
ek_add_device_dm9000();

18
arch/arm/boards/at91sam9263ek/init.c
View File

@ -87,13 +87,6 @@ static void ek_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
}
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = AT91_CHIPSELECT_0,
.size = 8 * 1024 * 1024,
};
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_RMII,
.phy_addr = 0,
@ -114,6 +107,14 @@ static void ek_add_device_mci(void)
static void ek_add_device_mci(void) {}
#endif
static int at91sam9263ek_mem_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
return 0;
}
mem_initcall(at91sam9263ek_mem_init);
static int at91sam9263ek_devices_init(void)
{
/*
@ -124,10 +125,9 @@ static int at91sam9263ek_devices_init(void)
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
at91_add_device_sdram(64 * 1024 * 1024);
ek_add_device_nand();
at91_add_device_eth(&macb_pdata);
register_device(&cfi_dev);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 8 * 1024 * 1024, 0);
ek_add_device_mci();
#if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)

8
arch/arm/boards/at91sam9m10g45ek/init.c
View File

@ -126,10 +126,16 @@ static void ek_add_device_mci(void)
static void ek_add_device_mci(void) {}
#endif
static int at91sam9m10g45ek_mem_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
return 0;
}
mem_initcall(at91sam9m10g45ek_mem_init);
static int at91sam9m10g45ek_devices_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
ek_add_device_nand();
at91_add_device_eth(&macb_pdata);
ek_add_device_mci();

79
arch/arm/boards/chumby_falconwing/falconwing.c
View File

@ -34,30 +34,11 @@
#include <mach/fb.h>
#include <mach/usb.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_MEMORY_BASE,
.size = 64 * 1024 * 1024,
.platform_data = &ram_pdata,
};
static struct mxs_mci_platform_data mci_pdata = {
.caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34, /* fixed to 3.3 V */
};
static struct device_d mci_dev = {
.name = "mxs_mci",
.map_base = IMX_SSP1_BASE,
.platform_data = &mci_pdata,
};
#define GPIO_LCD_RESET 50
#define GPIO_LCD_BACKLIGHT 60
@ -111,13 +92,6 @@ static struct imx_fb_platformdata fb_mode = {
.fixed_screen_size = MAX_FB_SIZE,
};
static struct device_d ldcif_dev = {
.name = "stmfb",
.map_base = IMX_FB_BASE,
.size = 4096,
.platform_data = &fb_mode,
};
static const uint32_t pad_setup[] = {
/* may be not required as already done by the bootlet code */
#if 0
@ -287,22 +261,13 @@ static const uint32_t pad_setup[] = {
GPMI_RDY3_GPIO | GPIO_IN | PULLUP(1),
};
#ifdef CONFIG_MMU
static int falconwing_mmu_init(void)
static int falconwing_mem_init(void)
{
mmu_init();
arm_create_section(0x40000000, 0x40000000, 64, PMD_SECT_DEF_CACHED);
arm_create_section(0x50000000, 0x40000000, 64, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
arm_add_mem_device("ram0", IMX_MEMORY_BASE, 64 * 1024 * 1024);
return 0;
}
postcore_initcall(falconwing_mmu_init);
#endif
mem_initcall(falconwing_mem_init);
/**
* Try to register an environment storage on the attached MCI card
@ -340,20 +305,6 @@ static int register_persistant_environment(void)
return devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0");
}
static struct ehci_platform_data chumby_usb_pdata = {
.flags = EHCI_HAS_TT,
.hccr_offset = 0x100,
.hcor_offset = 0x140,
};
static struct device_d usb_dev = {
.name = "ehci",
.id = -1,
.map_base = IMX_USB_BASE,
.size = 0x200,
.platform_data = &chumby_usb_pdata,
};
#define GPIO_USB_HUB_RESET 29
#define GPIO_USB_HUB_POWER 26
@ -366,7 +317,8 @@ static void falconwing_init_usb(void)
gpio_direction_output(GPIO_USB_HUB_RESET, 1);
imx_usb_phy_enable();
register_device(&usb_dev);
add_generic_usb_ehci_device(-1, IMX_USB_BASE, NULL);
}
static int falconwing_devices_init(void)
@ -377,17 +329,17 @@ static int falconwing_devices_init(void)
for (i = 0; i < ARRAY_SIZE(pad_setup); i++)
imx_gpio_mode(pad_setup[i]);
register_device(&sdram_dev);
imx_set_ioclk(480000000); /* enable IOCLK to run at the PLL frequency */
/* run the SSP unit clock at 100,000 kHz */
imx_set_sspclk(0, 100000000, 1);
register_device(&mci_dev);
register_device(&ldcif_dev);
add_generic_device("mxs_mci", 0, NULL, IMX_SSP1_BASE, 0,
IORESOURCE_MEM, &mci_pdata);
add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 4096,
IORESOURCE_MEM, &fb_mode);
falconwing_init_usb();
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100));
armlinux_set_bootparams((void *)IMX_MEMORY_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_CHUMBY);
rc = register_persistant_environment();
@ -399,15 +351,12 @@ static int falconwing_devices_init(void)
device_initcall(falconwing_devices_init);
static struct device_d falconwing_serial_device = {
.name = "stm_serial",
.map_base = IMX_DBGUART_BASE,
.size = 8192,
};
static int falconwing_console_init(void)
{
return register_device(&falconwing_serial_device);
add_generic_device("stm_serial", 0, NULL, IMX_DBGUART_BASE, 8192,
IORESOURCE_MEM, NULL);
return 0;
}
console_initcall(falconwing_console_init);

119
arch/arm/boards/edb93xx/edb93xx.c
View File

@ -34,83 +34,30 @@
#define DEVCFG_U1EN (1 << 18)
/*
* Up to 32MiB NOR type flash, connected to
* CS line 6, data width is 16 bit
*/
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0x60000000,
.size = EDB93XX_CFI_FLASH_SIZE,
};
static struct memory_platform_data ram_dev_pdata0 = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram0_dev = {
.id = -1,
.name = "mem",
.map_base = CONFIG_EP93XX_SDRAM_BANK0_BASE,
.size = CONFIG_EP93XX_SDRAM_BANK0_SIZE,
.platform_data = &ram_dev_pdata0,
};
static int ep93xx_mem_init(void)
{
arm_add_mem_device("ram0", CONFIG_EP93XX_SDRAM_BANK0_BASE,
CONFIG_EP93XX_SDRAM_BANK0_SIZE);
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
static struct memory_platform_data ram_dev_pdata1 = {
.name = "ram1",
.flags = DEVFS_RDWR,
};
static struct device_d sdram1_dev = {
.id = -1,
.name = "mem",
.map_base = CONFIG_EP93XX_SDRAM_BANK1_BASE,
.size = CONFIG_EP93XX_SDRAM_BANK1_SIZE,
.platform_data = &ram_dev_pdata1,
};
arm_add_mem_device("ram1", CONFIG_EP93XX_SDRAM_BANK1_BASE,
CONFIG_EP93XX_SDRAM_BANK1_SIZE);
#endif
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
static struct memory_platform_data ram_dev_pdata2 = {
.name = "ram2",
.flags = DEVFS_RDWR,
};
static struct device_d sdram2_dev = {
.id = -1,
.name = "mem",
.map_base = CONFIG_EP93XX_SDRAM_BANK2_BASE,
.size = CONFIG_EP93XX_SDRAM_BANK2_SIZE,
.platform_data = &ram_dev_pdata2,
};
arm_add_mem_device("ram2", CONFIG_EP93XX_SDRAM_BANK2_BASE,
CONFIG_EP93XX_SDRAM_BANK2_SIZE);
#endif
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
static struct memory_platform_data ram_dev_pdata3 = {
.name = "ram3",
.flags = DEVFS_RDWR,
};
static struct device_d sdram3_dev = {
.id = -1,
.name = "mem",
.map_base = CONFIG_EP93XX_SDRAM_BANK3_BASE,
.size = CONFIG_EP93XX_SDRAM_BANK3_SIZE,
.platform_data = &ram_dev_pdata3,
};
arm_add_mem_device("ram3", CONFIG_EP93XX_SDRAM_BANK3_BASE,
CONFIG_EP93XX_SDRAM_BANK2_SIZE);
#endif
static struct device_d eth_dev = {
.id = -1,
.name = "ep93xx_eth",
};
return 0;
}
mem_initcall(ep93xx_mem_init);
static int ep93xx_devices_init(void)
{
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0x60000000, EDB93XX_CFI_FLASH_SIZE, 0);
/*
* Create partitions that should be
@ -121,29 +68,11 @@ static int ep93xx_devices_init(void)
protect_file("/dev/env0", 1);
register_device(&sdram0_dev);
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
register_device(&sdram1_dev);
#endif
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
register_device(&sdram2_dev);
#endif
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
register_device(&sdram3_dev);
#endif
armlinux_add_dram(&sdram0_dev);
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
armlinux_add_dram(&sdram1_dev);
#endif
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
armlinux_add_dram(&sdram2_dev);
#endif
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
armlinux_add_dram(&sdram3_dev);
#endif
register_device(&eth_dev);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 6, data width is 16 bit
*/
add_generic_device("ep93xx_eth", -1, NULL, 0, 0, IORESOURCE_MEM, NULL);
armlinux_set_bootparams((void *)CONFIG_EP93XX_SDRAM_BANK0_BASE + 0x100);
@ -154,13 +83,6 @@ static int ep93xx_devices_init(void)
device_initcall(ep93xx_devices_init);
static struct device_d edb93xx_serial_device = {
.id = -1,
.name = "pl010_serial",
.map_base = UART1_BASE,
.size = 4096,
};
static int edb93xx_console_init(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
@ -179,7 +101,8 @@ static int edb93xx_console_init(void)
writel(0xAA, &syscon->sysswlock);
writel(value, &syscon->devicecfg);
register_device(&edb93xx_serial_device);
add_generic_device("pl010_serial", -1, NULL, UART1_BASE, 4096,
IORESOURCE_MEM, NULL);
return 0;
}

56
arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
View File

@ -37,6 +37,7 @@
#include <generated/mach-types.h>
#include <mach/imx-nand.h>
#include <mach/imxfb.h>
#include <mach/iim.h>
#include <fec.h>
#include <nand.h>
#include <mach/imx-flash-header.h>
@ -90,19 +91,6 @@ static struct fec_platform_data fec_info = {
.phy_addr = 1,
};
static struct memory_platform_data sdram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram0_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 64 * 1024 * 1024,
.platform_data = &sdram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
@ -161,12 +149,6 @@ static void imx25_usb_init(void)
writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
}
static struct device_d usbh2_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE + 0x400,
.size = 0x200,
};
#endif
static struct fsl_usb2_platform_data usb_pdata = {
@ -174,30 +156,13 @@ static struct fsl_usb2_platform_data usb_pdata = {
.phy_mode = FSL_USB2_PHY_UTMI,
};
static struct device_d usbotg_dev = {
.name = "fsl-udc",
.map_base = IMX_OTG_BASE,
.size = 0x200,
.platform_data = &usb_pdata,
};
#ifdef CONFIG_MMU
static void eukrea_cpuimx25_mmu_init(void)
static int eukrea_cpuimx25_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024);
arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
return 0;
}
#else
static void eukrea_cpuimx25_mmu_init(void)
{
}
#endif
mem_initcall(eukrea_cpuimx25_mem_init);
static struct pad_desc eukrea_cpuimx25_pads[] = {
MX25_PAD_FEC_MDC__FEC_MDC,
@ -255,13 +220,12 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
static int eukrea_cpuimx25_devices_init(void)
{
eukrea_cpuimx25_mmu_init();
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
ARRAY_SIZE(eukrea_cpuimx25_pads));
led_gpio_register(&led0);
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
nand_info.width = 1;
@ -275,8 +239,6 @@ static int eukrea_cpuimx25_devices_init(void)
PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
register_device(&sdram0_dev);
/* enable LCD */
gpio_direction_output(26, 1);
gpio_set_value(26, 1);
@ -291,11 +253,11 @@ static int eukrea_cpuimx25_devices_init(void)
#ifdef CONFIG_USB
imx25_usb_init();
register_device(&usbh2_dev);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
#endif
register_device(&usbotg_dev);
add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200,
IORESOURCE_MEM, &usb_pdata);
armlinux_add_dram(&sdram0_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25);

107
arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
View File

@ -48,40 +48,12 @@
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC0000000,
.size = 32 * 1024 * 1024,
};
#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
static struct device_d cfi_dev1 = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC2000000,
.size = 32 * 1024 * 1024,
};
#endif
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
#define SDRAM0 256
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
#define SDRAM0 128
#endif
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0xa0000000,
.size = SDRAM0 * 1024 * 1024,
.platform_data = &ram_pdata,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 1,
@ -94,28 +66,9 @@ struct imx_nand_platform_data nand_info = {
};
#ifdef CONFIG_DRIVER_SERIAL_NS16550
unsigned int quad_uart_read(unsigned long base, unsigned char reg_idx)
{
unsigned int reg_addr = (unsigned int)base;
reg_addr += reg_idx << 1;
return 0xff & readw(reg_addr);
}
EXPORT_SYMBOL(quad_uart_read);
void quad_uart_write(unsigned int val, unsigned long base,
unsigned char reg_idx)
{
unsigned int reg_addr = (unsigned int)base;
reg_addr += reg_idx << 1;
writew(0xff & val, reg_addr);
}
EXPORT_SYMBOL(quad_uart_write);
static struct NS16550_plat quad_uart_serial_plat = {
.clock = 14745600,
.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
.reg_read = quad_uart_read,
.reg_write = quad_uart_write,
.shift = 1,
};
#ifdef CONFIG_EUKREA_CPUIMX27_QUART1
@ -127,14 +80,6 @@ static struct NS16550_plat quad_uart_serial_plat = {
#elif defined CONFIG_EUKREA_CPUIMX27_QUART4
#define QUART_OFFSET 0x1000000
#endif
static struct device_d quad_uart_serial_device = {
.id = -1,
.name = "serial_ns16550",
.map_base = IMX_CS3_BASE + QUART_OFFSET,
.size = 0xF,
.platform_data = (void *)&quad_uart_serial_plat,
};
#endif
static struct i2c_board_info i2c_devices[] = {
@ -143,23 +88,13 @@ static struct i2c_board_info i2c_devices[] = {
},
};
#ifdef CONFIG_MMU
static void eukrea_cpuimx27_mmu_init(void)
static int eukrea_cpuimx27_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", 0xa0000000, SDRAM0 * 1024 * 1024);
arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
return 0;
}
#else
static void eukrea_cpuimx27_mmu_init(void)
{
}
#endif
mem_initcall(eukrea_cpuimx27_mem_init);
#ifdef CONFIG_DRIVER_VIDEO_IMX
static struct imx_fb_videomode imxfb_mode = {
@ -185,14 +120,6 @@ static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = {
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
static struct device_d imxfb_dev = {
.id = -1,
.name = "imxfb",
.map_base = 0x10021000,
.size = 0x1000,
.platform_data = &eukrea_cpuimx27_fb_data,
};
#endif
static int eukrea_cpuimx27_devices_init(void)
@ -255,8 +182,6 @@ static int eukrea_cpuimx27_devices_init(void)
#endif
};
eukrea_cpuimx27_mmu_init();
/* configure 16 bit nor flash on cs0 */
CS0U = 0x00008F03;
CS0L = 0xA0330D01;
@ -266,12 +191,11 @@ static int eukrea_cpuimx27_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
register_device(&cfi_dev1);
add_cfi_flash_device(-1, 0xC2000000, 32 * 1024 * 1024, 0);
#endif
imx27_add_nand(&nand_info);
register_device(&sdram_dev);
PCCR0 |= PCCR0_I2C1_EN;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
@ -285,14 +209,13 @@ static int eukrea_cpuimx27_devices_init(void)
printf("Using environment in %s Flash\n", envdev);
#ifdef CONFIG_DRIVER_VIDEO_IMX
register_device(&imxfb_dev);
imx_add_fb((void *)0x10021000, &eukrea_cpuimx27_fb_data);
gpio_direction_output(GPIO_PORTE | 5, 0);
gpio_set_value(GPIO_PORTE | 5, 1);
gpio_direction_output(GPIO_PORTA | 25, 0);
gpio_set_value(GPIO_PORTA | 25, 1);
#endif
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_CPUIMX27);
@ -301,19 +224,10 @@ static int eukrea_cpuimx27_devices_init(void)
device_initcall(eukrea_cpuimx27_devices_init);
#ifdef CONFIG_DRIVER_SERIAL_IMX
static struct device_d eukrea_cpuimx27_serial_device = {
.id = -1,
.name = "imx_serial",
.map_base = IMX_UART1_BASE,
.size = 4096,
};
#endif
static int eukrea_cpuimx27_console_init(void)
{
#ifdef CONFIG_DRIVER_SERIAL_IMX
register_device(&eukrea_cpuimx27_serial_device);
imx_add_uart((void *)IMX_UART1_BASE, -1);
#endif
/* configure 8 bit UART on cs3 */
FMCR &= ~0x2;
@ -321,7 +235,8 @@ static int eukrea_cpuimx27_console_init(void)
CS3L = 0x0D1D0D01;
CS3A = 0x00D20000;
#ifdef CONFIG_DRIVER_SERIAL_NS16550
register_device(&quad_uart_serial_device);
add_ns16550_device(-1, IMX_CS3_BASE + QUART_OFFSET, 0xf,
IORESOURCE_MEM_16BIT, &quad_uart_serial_plat);
#endif
return 0;
}

67
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
View File

@ -61,19 +61,6 @@ static struct fec_platform_data fec_info = {
.phy_addr = 0x1F,
};
static struct memory_platform_data sdram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 128 * 1024 * 1024,
.platform_data = &sdram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
@ -130,46 +117,30 @@ static void imx35_usb_init(void)
tmp = readl(IMX_OTG_BASE + 0x5a8);
writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
}
static struct device_d usbh2_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE + 0x400,
.size = 0x200,
};
#endif
#ifdef CONFIG_USB_GADGET
static struct fsl_usb2_platform_data usb_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
static struct device_d usbotg_dev = {
.name = "fsl-udc",
.map_base = IMX_OTG_BASE,
.size = 0x200,
.platform_data = &usb_pdata,
};
#ifdef CONFIG_MMU
static int eukrea_cpuimx35_mmu_init(void)
{
mmu_init();
arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
#ifdef CONFIG_CACHE_L2X0
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
#endif
static int eukrea_cpuimx35_mem_init(void)
{
arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
return 0;
}
postcore_initcall(eukrea_cpuimx35_mmu_init);
#endif
mem_initcall(eukrea_cpuimx35_mem_init);
static int eukrea_cpuimx35_mmu_init(void)
{
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
return 0;
}
postmmu_initcall(eukrea_cpuimx35_mmu_init);
static int eukrea_cpuimx35_devices_init(void)
{
@ -181,8 +152,6 @@ static int eukrea_cpuimx35_devices_init(void)
dev_add_bb_dev("env_raw", "env0");
imx35_add_fec(&fec_info);
register_device(&sdram_dev);
imx35_add_fb(&ipu_fb_data);
imx35_add_i2c0(NULL);
@ -190,15 +159,15 @@ static int eukrea_cpuimx35_devices_init(void)
#ifdef CONFIG_USB
imx35_usb_init();
register_device(&usbh2_dev);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
#endif
#ifdef CONFIG_USB_GADGET
/* Workaround ENGcm09152 */
tmp = readl(IMX_OTG_BASE + 0x608);
writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
register_device(&usbotg_dev);
add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200,
IORESOURCE_MEM, &usb_pdata);
#endif
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);

41
arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
View File

@ -42,19 +42,6 @@
#include <mach/iomux-mx51.h>
#include <mach/devices-imx51.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x90000000,
.size = 256 * 1024 * 1024,
.platform_data = &ram_pdata,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
};
@ -106,35 +93,16 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
#define GPIO_LAN8700_RESET (1 * 32 + 31)
#define GPIO_LCD_BL (2 * 32 + 4)
#ifdef CONFIG_MMU
static void eukrea_cpuimx51_mmu_init(void)
static int eukrea_cpuimx51_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", 0x90000000, 256 * 1024 * 1024);
arm_create_section(0x90000000, 0x90000000, 256, PMD_SECT_DEF_CACHED);
arm_create_section(0xa0000000, 0x90000000, 256, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
#if TEXT_BASE & (0x100000 - 1)
#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
#else
arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
#endif
mmu_enable();
return 0;
}
#else
static void eukrea_cpuimx51_mmu_init(void)
{
}
#endif
mem_initcall(eukrea_cpuimx51_mem_init);
static int eukrea_cpuimx51_devices_init(void)
{
eukrea_cpuimx51_mmu_init();
register_device(&sdram_dev);
imx51_add_fec(&fec_info);
#ifdef CONFIG_MCI_IMX_ESDHC
imx51_add_mmc0(NULL);
@ -150,7 +118,6 @@ static int eukrea_cpuimx51_devices_init(void)
gpio_set_value(GPIO_LAN8700_RESET, 1);
gpio_direction_output(GPIO_LCD_BL, 0);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX51SD);

110
arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
View File

@ -19,29 +19,29 @@
#include <config.h>
#include <mach/imx-regs.h>
#include <mach/clock-imx51.h>
#include <mach/clock-imx51_53.h>
#define ROM_SI_REV_OFFSET 0x48
.macro setup_pll pll, freq
ldr r2, =\pll
ldr r1, =0x00001232
str r1, [r2, #MX51_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
str r1, [r2, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r2, #MX51_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
str r1, [r2, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
str r3, [r2, #MX51_PLL_DP_OP]
str r3, [r2, #MX51_PLL_DP_HFS_OP]
str r3, [r2, #MX5_PLL_DP_OP]
str r3, [r2, #MX5_PLL_DP_HFS_OP]
str r4, [r2, #MX51_PLL_DP_MFD]
str r4, [r2, #MX51_PLL_DP_HFS_MFD]
str r4, [r2, #MX5_PLL_DP_MFD]
str r4, [r2, #MX5_PLL_DP_HFS_MFD]
str r5, [r2, #MX51_PLL_DP_MFN]
str r5, [r2, #MX51_PLL_DP_HFS_MFN]
str r5, [r2, #MX5_PLL_DP_MFN]
str r5, [r2, #MX5_PLL_DP_HFS_MFN]
ldr r1, =0x00001232
str r1, [r2, #MX51_PLL_DP_CTL]
1: ldr r1, [r2, #MX51_PLL_DP_CTL]
str r1, [r2, #MX5_PLL_DP_CTL]
1: ldr r1, [r2, #MX5_PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
.endm
@ -80,67 +80,67 @@ board_init_lowlevel:
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #MX51_CCM_CCGR0]
str r1, [r0, #MX5_CCM_CCGR0]
ldr r1, =0x0
str r1, [r0, #MX51_CCM_CCGR1]
str r1, [r0, #MX51_CCM_CCGR2]
str r1, [r0, #MX51_CCM_CCGR3]
str r1, [r0, #MX5_CCM_CCGR1]
str r1, [r0, #MX5_CCM_CCGR2]
str r1, [r0, #MX5_CCM_CCGR3]
ldr r1, =0x00030000
str r1, [r0, #MX51_CCM_CCGR4]
str r1, [r0, #MX5_CCM_CCGR4]
ldr r1, =0x00FFF030
str r1, [r0, #MX51_CCM_CCGR5]
str r1, [r0, #MX5_CCM_CCGR5]
ldr r1, =0x00000300
str r1, [r0, #MX51_CCM_CCGR6]
str r1, [r0, #MX5_CCM_CCGR6]
/* Disable IPU and HSC dividers */
mov r1, #0x60000
str r1, [r0, #MX51_CCM_CCDR]
str r1, [r0, #MX5_CCM_CCDR]
#ifdef IMX51_TO_2
/* Make sure to switch the DDR away from PLL 1 */
ldr r1, =0x19239145
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
/* make sure divider effective */
1: ldr r1, [r0, #MX51_CCM_CDHIPR]
1: ldr r1, [r0, #MX5_CCM_CDHIPR]
cmp r1, #0x0
bne 1b
#endif
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #MX51_CCM_CCSR]
str r1, [r0, #MX5_CCM_CCSR]
mov r3, #MX51_PLL_DP_OP_800
mov r4, #MX51_PLL_DP_MFD_800
mov r5, #MX51_PLL_DP_MFN_800
mov r3, #MX5_PLL_DP_OP_800
mov r4, #MX5_PLL_DP_MFD_800
mov r5, #MX5_PLL_DP_MFN_800
setup_pll MX51_PLL1_BASE_ADDR
mov r3, #MX51_PLL_DP_OP_665
mov r4, #MX51_PLL_DP_MFD_665
mov r5, #MX51_PLL_DP_MFN_665
mov r3, #MX5_PLL_DP_OP_665
mov r4, #MX5_PLL_DP_MFD_665
mov r5, #MX5_PLL_DP_MFN_665
setup_pll MX51_PLL3_BASE_ADDR
/* Switch peripheral to PLL 3 */
ldr r1, =0x000010C0
str r1, [r0, #MX51_CCM_CBCMR]
str r1, [r0, #MX5_CCM_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
mov r3, #MX51_PLL_DP_OP_665
mov r4, #MX51_PLL_DP_MFD_665
mov r5, #MX51_PLL_DP_MFN_665
mov r3, #MX5_PLL_DP_OP_665
mov r4, #MX5_PLL_DP_MFD_665
mov r5, #MX5_PLL_DP_MFN_665
setup_pll MX51_PLL2_BASE_ADDR
/* Switch peripheral to PLL2 */
ldr r1, =0x19239145
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
ldr r1, =0x000020C0
str r1, [r0, #MX51_CCM_CBCMR]
str r1, [r0, #MX5_CCM_CBCMR]
mov r3, #MX51_PLL_DP_OP_216
mov r4, #MX51_PLL_DP_MFD_216
mov r5, #MX51_PLL_DP_MFN_216
mov r3, #MX5_PLL_DP_OP_216
mov r4, #MX5_PLL_DP_MFD_216
mov r5, #MX5_PLL_DP_MFN_216
setup_pll MX51_PLL3_BASE_ADDR
/* Set the platform clock dividers */
@ -154,52 +154,52 @@ board_init_lowlevel:
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
str r1, [r0, #MX51_CCM_CACRR]
str r1, [r0, #MX5_CCM_CACRR]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #MX51_CCM_CCSR]
str r1, [r0, #MX5_CCM_CCSR]
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
#ifdef IMX51_TO_2
ldr r1, =0x000020C2
str r1, [r0, #MX51_CCM_CBCMR]
str r1, [r0, #MX5_CCM_CBCMR]
// ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
ldr r1, =0x59239100
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
#else
ldr r1, =0x0000E3C2
str r1, [r0, #MX51_CCM_CBCMR]
str r1, [r0, #MX5_CCM_CBCMR]
// emi=ahb, all perclk dividers are 1 since using 24MHz
// DDR divider=6 to have 665/6=110MHz
ldr r1, =0x013B9100
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
#endif
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #MX51_CCM_CCGR0]
str r1, [r0, #MX51_CCM_CCGR1]
str r1, [r0, #MX51_CCM_CCGR2]
str r1, [r0, #MX51_CCM_CCGR3]
str r1, [r0, #MX51_CCM_CCGR4]
str r1, [r0, #MX51_CCM_CCGR5]
str r1, [r0, #MX51_CCM_CCGR6]
str r1, [r0, #MX5_CCM_CCGR0]
str r1, [r0, #MX5_CCM_CCGR1]
str r1, [r0, #MX5_CCM_CCGR2]
str r1, [r0, #MX5_CCM_CCGR3]
str r1, [r0, #MX5_CCM_CCGR4]
str r1, [r0, #MX5_CCM_CCGR5]
str r1, [r0, #MX5_CCM_CCGR6]
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #MX51_CCM_CSCMR1]
str r1, [r0, #MX5_CCM_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #MX51_CCM_CSCDR1]
str r1, [r0, #MX5_CCM_CSCDR1]
/* make sure divider effective */
1: ldr r1, [r0, #MX51_CCM_CDHIPR]
1: ldr r1, [r0, #MX5_CCM_CDHIPR]
cmp r1, #0x0
bne 1b
mov r1, #0x0
str r1, [r0, #MX51_CCM_CCDR]
str r1, [r0, #MX5_CCM_CCDR]
writel(0x1, 0x73fa8074)
ldr r0, =0x73f88000

32
arch/arm/boards/freescale-mx23-evk/mx23-evk.c
View File

@ -25,24 +25,17 @@
#include <generated/mach-types.h>
#include <mach/imx-regs.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static int mx23_evk_mem_init(void)
{
arm_add_mem_device("ram0", IMX_MEMORY_BASE, 32 * 1024 * 1024);
static struct device_d sdram_dev = {
.name = "mem",
.map_base = IMX_MEMORY_BASE,
.size = 32 * 1024 * 1024,
.platform_data = &ram_pdata,
};
return 0;
}
mem_initcall(mx23_evk_mem_init);
static int mx23_evk_devices_init(void)
{
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100));
armlinux_set_bootparams((void*)IMX_MEMORY_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_MX23EVK);
return 0;
@ -50,15 +43,12 @@ static int mx23_evk_devices_init(void)
device_initcall(mx23_evk_devices_init);
static struct device_d mx23_evk_serial_device = {
.name = "stm_serial",
.map_base = IMX_DBGUART_BASE,
.size = 8192,
};
static int mx23_evk_console_init(void)
{
return register_device(&mx23_evk_serial_device);
add_generic_device("stm_serial", 0, NULL, IMX_DBGUART_BASE, 8192,
IORESOURCE_MEM, NULL);
return 0;
}
console_initcall(mx23_evk_console_init);

63
arch/arm/boards/freescale-mx25-3-stack/3stack.c
View File

@ -37,6 +37,7 @@
#include <mach/imx-flash-header.h>
#include <mach/iomux-mx25.h>
#include <mach/generic.h>
#include <mach/iim.h>
#include <linux/err.h>
#include <i2c/i2c.h>
#include <mfd/mc34704.h>
@ -113,38 +114,6 @@ static struct fec_platform_data fec_info = {
.phy_addr = 1,
};
static struct memory_platform_data sdram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram0_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
.size = 64 * 1024 * 1024,
#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
.size = 128 * 1024 * 1024,
#else
#error "Unsupported SDRAM type"
#endif
.platform_data = &sdram_pdata,
};
static struct memory_platform_data sram_pdata = {
.name = "sram0",
.flags = DEVFS_RDWR,
};
static struct device_d sram0_dev = {
.id = -1,
.name = "mem",
.map_base = 0x78000000,
.size = 128 * 1024,
.platform_data = &sram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
@ -169,13 +138,6 @@ static void imx25_usb_init(void)
tmp = readl(IMX_OTG_BASE + 0x5a8);
writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
}
static struct device_d usbh2_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE + 0x400,
.size = 0x200,
};
#endif
static struct i2c_board_info i2c_devices[] = {
@ -230,6 +192,22 @@ static int imx25_3ds_fec_init(void)
}
late_initcall(imx25_3ds_fec_init);
static int imx25_mem_init(void)
{
#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
#define SDRAM_SIZE 64 * 1024 * 1024
#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
#define SDRAM_SIZE 128 * 1024 * 1024
#else
#error "Unsupported SDRAM type"
#endif
arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM_SIZE);
add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE);
return 0;
}
mem_initcall(imx25_mem_init);
static int imx25_devices_init(void)
{
#ifdef CONFIG_USB
@ -237,9 +215,10 @@ static int imx25_devices_init(void)
* the CPLD has to be initialized.
*/
imx25_usb_init();
register_device(&usbh2_dev);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
#endif
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
@ -253,13 +232,9 @@ static int imx25_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
register_device(&sdram0_dev);
register_device(&sram0_dev);
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx25_add_i2c0(NULL);
armlinux_add_dram(&sdram0_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX25_3DS);
armlinux_set_serial(imx_uid());

49
arch/arm/boards/freescale-mx35-3-stack/3stack.c
View File

@ -59,43 +59,16 @@
#define MX35PDK_BOARD_REV_1 0
#define MX35PDK_BOARD_REV_2 1
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = IMX_CS0_BASE,
.size = 64 * 1024 * 1024,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 0x1F,
};
static struct memory_platform_data sdram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 128 * 1024 * 1024,
.platform_data = &sdram_pdata,
};
struct imx_nand_platform_data nand_info = {
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct device_d smc911x_dev = {
.id = -1,
.name = "smc911x",
.map_base = IMX_CS5_BASE,
.size = IMX_CS5_RANGE,
};
static struct i2c_board_info i2c_devices[] = {
{
I2C_BOARD_INFO("mc13892-i2c", 0x08),
@ -104,12 +77,6 @@ static struct i2c_board_info i2c_devices[] = {
},
};
static struct device_d i2c_dev = {
.id = -1,
.name = "i2c-imx",
.map_base = IMX_I2C1_BASE,
};
/*
* Generic display, shipped with the PDK
*/
@ -161,6 +128,13 @@ static void set_board_rev(int rev)
imx35_3ds_system_rev = (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
}
static int f3s_mem_init(void)
{
arm_add_mem_device("ram0", IMX_SDRAM_CS0, 124 * 1024 * 1024);
return 0;
}
mem_initcall(f3s_mem_init);
static int f3s_devices_init(void)
{
@ -182,7 +156,7 @@ static int f3s_devices_init(void)
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
register_device(&cfi_dev);
add_cfi_flash_device(-1, IMX_CS0_BASE, 64 * 1024 * 1024, 0);
switch ((reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */
@ -202,17 +176,16 @@ static int f3s_devices_init(void)
set_silicon_rev(imx_silicon_revision());
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
register_device(&i2c_dev);
imx35_add_i2c0(NULL);
imx35_add_fec(&fec_info);
register_device(&smc911x_dev);
add_generic_device("smc911x", -1, NULL, IMX_CS5_BASE, IMX_CS5_RANGE,
IORESOURCE_MEM, NULL);
imx35_add_mmc0(NULL);
register_device(&sdram_dev);
imx35_add_fb(&ipu_fb_data);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX35_3DS);

38
arch/arm/boards/freescale-mx51-pdk/board.c
View File

@ -19,7 +19,6 @@
*/
#include <common.h>
#include <net.h>
#include <init.h>
#include <environment.h>
#include <mach/imx-regs.h>
@ -40,19 +39,7 @@
#include <mach/generic.h>
#include <mach/iomux-mx51.h>
#include <mach/devices-imx51.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x90000000,
.size = 512 * 1024 * 1024,
.platform_data = &ram_pdata,
};
#include <mach/iim.h>
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
@ -86,23 +73,13 @@ static struct pad_desc f3s_pads[] = {
IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, 0x85), /* FIXME: needed? */
};
#ifdef CONFIG_MMU
static void babbage_mmu_init(void)
static int babbage_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", 0x90000000, 512 * 1024 * 1024);
arm_create_section(0x90000000, 0x90000000, 512, PMD_SECT_DEF_CACHED);
arm_create_section(0xb0000000, 0x90000000, 512, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x20000000);
mmu_enable();
return 0;
}
#else
static void babbage_mmu_init(void)
{
}
#endif
mem_initcall(babbage_mem_init);
#define BABBAGE_ECSPI1_CS0 (3 * 32 + 24)
static int spi_0_cs[] = {BABBAGE_ECSPI1_CS0};
@ -240,9 +217,7 @@ static void babbage_power_init(void)
static int f3s_devices_init(void)
{
babbage_mmu_init();
register_device(&sdram_dev);
imx51_iim_register_fec_ethaddr();
imx51_add_fec(&fec_info);
imx51_add_mmc0(NULL);
@ -252,7 +227,6 @@ static int f3s_devices_init(void)
babbage_power_init();
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);

110
arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
View File

@ -19,29 +19,29 @@
#include <config.h>
#include <mach/imx-regs.h>
#include <mach/clock-imx51.h>
#include <mach/clock-imx51_53.h>
#define ROM_SI_REV_OFFSET 0x48
.macro setup_pll pll, freq
ldr r2, =\pll
ldr r1, =0x00001232
str r1, [r2, #MX51_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
str r1, [r2, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r2, #MX51_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
str r1, [r2, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
str r3, [r2, #MX51_PLL_DP_OP]
str r3, [r2, #MX51_PLL_DP_HFS_OP]
str r3, [r2, #MX5_PLL_DP_OP]
str r3, [r2, #MX5_PLL_DP_HFS_OP]
str r4, [r2, #MX51_PLL_DP_MFD]
str r4, [r2, #MX51_PLL_DP_HFS_MFD]
str r4, [r2, #MX5_PLL_DP_MFD]
str r4, [r2, #MX5_PLL_DP_HFS_MFD]
str r5, [r2, #MX51_PLL_DP_MFN]
str r5, [r2, #MX51_PLL_DP_HFS_MFN]
str r5, [r2, #MX5_PLL_DP_MFN]
str r5, [r2, #MX5_PLL_DP_HFS_MFN]
ldr r1, =0x00001232
str r1, [r2, #MX51_PLL_DP_CTL]
1: ldr r1, [r2, #MX51_PLL_DP_CTL]
str r1, [r2, #MX5_PLL_DP_CTL]
1: ldr r1, [r2, #MX5_PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
.endm
@ -80,67 +80,67 @@ board_init_lowlevel:
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #MX51_CCM_CCGR0]
str r1, [r0, #MX5_CCM_CCGR0]
ldr r1, =0x0
str r1, [r0, #MX51_CCM_CCGR1]
str r1, [r0, #MX51_CCM_CCGR2]
str r1, [r0, #MX51_CCM_CCGR3]
str r1, [r0, #MX5_CCM_CCGR1]
str r1, [r0, #MX5_CCM_CCGR2]
str r1, [r0, #MX5_CCM_CCGR3]
ldr r1, =0x00030000
str r1, [r0, #MX51_CCM_CCGR4]
str r1, [r0, #MX5_CCM_CCGR4]
ldr r1, =0x00FFF030
str r1, [r0, #MX51_CCM_CCGR5]
str r1, [r0, #MX5_CCM_CCGR5]
ldr r1, =0x00000300
str r1, [r0, #MX51_CCM_CCGR6]
str r1, [r0, #MX5_CCM_CCGR6]
/* Disable IPU and HSC dividers */
mov r1, #0x60000
str r1, [r0, #MX51_CCM_CCDR]
str r1, [r0, #MX5_CCM_CCDR]
#ifdef IMX51_TO_2
/* Make sure to switch the DDR away from PLL 1 */
ldr r1, =0x19239145
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
/* make sure divider effective */
1: ldr r1, [r0, #MX51_CCM_CDHIPR]
1: ldr r1, [r0, #MX5_CCM_CDHIPR]
cmp r1, #0x0
bne 1b
#endif
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #MX51_CCM_CCSR]
str r1, [r0, #MX5_CCM_CCSR]
mov r3, #MX51_PLL_DP_OP_800
mov r4, #MX51_PLL_DP_MFD_800
mov r5, #MX51_PLL_DP_MFN_800
mov r3, #MX5_PLL_DP_OP_800
mov r4, #MX5_PLL_DP_MFD_800
mov r5, #MX5_PLL_DP_MFN_800
setup_pll MX51_PLL1_BASE_ADDR
mov r3, #MX51_PLL_DP_OP_665
mov r4, #MX51_PLL_DP_MFD_665
mov r5, #MX51_PLL_DP_MFN_665
mov r3, #MX5_PLL_DP_OP_665
mov r4, #MX5_PLL_DP_MFD_665
mov r5, #MX5_PLL_DP_MFN_665
setup_pll MX51_PLL3_BASE_ADDR
/* Switch peripheral to PLL 3 */
ldr r1, =0x000010C0
str r1, [r0, #MX51_CCM_CBCMR]
str r1, [r0, #MX5_CCM_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
mov r3, #MX51_PLL_DP_OP_665
mov r4, #MX51_PLL_DP_MFD_665
mov r5, #MX51_PLL_DP_MFN_665
mov r3, #MX5_PLL_DP_OP_665
mov r4, #MX5_PLL_DP_MFD_665
mov r5, #MX5_PLL_DP_MFN_665
setup_pll MX51_PLL2_BASE_ADDR
/* Switch peripheral to PLL2 */
ldr r1, =0x19239145
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
ldr r1, =0x000020C0
str r1, [r0, #MX51_CCM_CBCMR]
str r1, [r0, #MX5_CCM_CBCMR]
mov r3, #MX51_PLL_DP_OP_216
mov r4, #MX51_PLL_DP_MFD_216
mov r5, #MX51_PLL_DP_MFN_216
mov r3, #MX5_PLL_DP_OP_216
mov r4, #MX5_PLL_DP_MFD_216
mov r5, #MX5_PLL_DP_MFN_216
setup_pll MX51_PLL3_BASE_ADDR
/* Set the platform clock dividers */
@ -154,52 +154,52 @@ board_init_lowlevel:
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
str r1, [r0, #MX51_CCM_CACRR]
str r1, [r0, #MX5_CCM_CACRR]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #MX51_CCM_CCSR]
str r1, [r0, #MX5_CCM_CCSR]
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
#ifdef IMX51_TO_2
ldr r1, =0x000020C2
str r1, [r0, #MX51_CCM_CBCMR]
str r1, [r0, #MX5_CCM_CBCMR]
// ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
ldr r1, =0x59239100
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
#else
ldr r1, =0x0000E3C2
str r1, [r0, #MX51_CCM_CBCMR]
str r1, [r0, #MX5_CCM_CBCMR]
// emi=ahb, all perclk dividers are 1 since using 24MHz
// DDR divider=6 to have 665/6=110MHz
ldr r1, =0x013B9100
str r1, [r0, #MX51_CCM_CBCDR]
str r1, [r0, #MX5_CCM_CBCDR]
#endif
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #MX51_CCM_CCGR0]
str r1, [r0, #MX51_CCM_CCGR1]
str r1, [r0, #MX51_CCM_CCGR2]
str r1, [r0, #MX51_CCM_CCGR3]
str r1, [r0, #MX51_CCM_CCGR4]
str r1, [r0, #MX51_CCM_CCGR5]
str r1, [r0, #MX51_CCM_CCGR6]
str r1, [r0, #MX5_CCM_CCGR0]
str r1, [r0, #MX5_CCM_CCGR1]
str r1, [r0, #MX5_CCM_CCGR2]
str r1, [r0, #MX5_CCM_CCGR3]
str r1, [r0, #MX5_CCM_CCGR4]
str r1, [r0, #MX5_CCM_CCGR5]
str r1, [r0, #MX5_CCM_CCGR6]
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #MX51_CCM_CSCMR1]
str r1, [r0, #MX5_CCM_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #MX51_CCM_CSCDR1]
str r1, [r0, #MX5_CCM_CSCDR1]
/* make sure divider effective */
1: ldr r1, [r0, #MX51_CCM_CDHIPR]
1: ldr r1, [r0, #MX5_CCM_CDHIPR]
cmp r1, #0x0
bne 1b
mov r1, #0x0
str r1, [r0, #MX51_CCM_CCDR]
str r1, [r0, #MX5_CCM_CCDR]
writel(0x1, 0x73fa8074)
ldr r0, =0x73f88000

3
arch/arm/boards/freescale-mx53-loco/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-y += lowlevel_init.o
obj-y += board.o
obj-y += flash_header.o

129
arch/arm/boards/freescale-mx53-loco/board.c Normal file
View File

@ -0,0 +1,129 @@
/*
* Copyright (C) 2007 Sascha Hauer, Pengutronix
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <environment.h>
#include <fcntl.h>
#include <fec.h>
#include <fs.h>
#include <init.h>
#include <nand.h>
#include <net.h>
#include <partition.h>
#include <sizes.h>
#include <generated/mach-types.h>
#include <mach/imx-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
#include <mach/gpio.h>
#include <mach/imx-nand.h>
#include <mach/iim.h>
#include <asm/armlinux.h>
#include <asm/io.h>
#include <asm/mmu.h>
static struct fec_platform_data fec_info = {
.xcv_type = RMII,
};
static struct pad_desc loco_pads[] = {
/* UART1 */
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
/* FEC */
MX53_PAD_FEC_MDC__FEC_MDC,
MX53_PAD_FEC_MDIO__FEC_MDIO,
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
MX53_PAD_FEC_RX_ER__FEC_RX_ER,
MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
MX53_PAD_FEC_RXD1__FEC_RDATA_1,
MX53_PAD_FEC_RXD0__FEC_RDATA_0,
MX53_PAD_FEC_TX_EN__FEC_TX_EN,
MX53_PAD_FEC_TXD1__FEC_TDATA_1,
MX53_PAD_FEC_TXD0__FEC_TDATA_0,
/* FEC_nRST */
MX53_PAD_PATA_DA_0__GPIO7_6,
/* SD1 */
MX53_PAD_SD1_CMD__ESDHC1_CMD,
MX53_PAD_SD1_CLK__ESDHC1_CLK,
MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD1_CD */
MX53_PAD_EIM_DA13__GPIO3_13,
};
static int loco_mem_init(void)
{
arm_add_mem_device("ram0", 0x70000000, SZ_512M);
arm_add_mem_device("ram1", 0xb0000000, SZ_512M);
return 0;
}
mem_initcall(loco_mem_init);
#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
static void loco_fec_reset(void)
{
gpio_direction_output(LOCO_FEC_PHY_RST, 0);
mdelay(1);
gpio_set_value(LOCO_FEC_PHY_RST, 1);
}
static int loco_devices_init(void)
{
imx51_iim_register_fec_ethaddr();
imx53_add_fec(&fec_info);
imx53_add_mmc0(NULL);
loco_fec_reset();
armlinux_set_bootparams((void *)0x70000100);
armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
loco_fec_reset();
return 0;
}
device_initcall(loco_devices_init);
static int loco_part_init(void)
{
devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
return 0;
}
late_initcall(loco_part_init);
static int loco_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(loco_pads, ARRAY_SIZE(loco_pads));
imx53_add_uart0();
return 0;
}
console_initcall(loco_console_init);

20
arch/arm/include/asm/global_data.h → arch/arm/boards/freescale-mx53-loco/config.h
View File

@ -1,9 +1,6 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
/**
* @file
* @brief Global defintions for the ARM i.MX51 based babbage board
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -12,7 +9,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -21,10 +18,7 @@
* MA 02111-1307 USA
*/
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
typedef struct global_data gd_t;
#ifndef __CONFIG_H
#define __CONFIG_H
#define DECLARE_GLOBAL_DATA_PTR
#endif /* __ASM_GBL_DATA_H */
#endif /* __CONFIG_H */

51
arch/arm/boards/freescale-mx53-loco/env/config vendored Normal file
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@ -0,0 +1,51 @@
#!/bin/sh
machine=loco
eth0.serverip=
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'nfs', 'tftp', 'nor' or 'nand'
kernel_loc=tftp
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-$machine.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage_type=zimage
kernelimage=zImage-$machine
#kernelimage_type=uimage
#kernelimage=uImage-$machine
#kernelimage_type=raw
#kernelimage=Image-$machine
#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200"
disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)"
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

101
arch/arm/boards/freescale-mx53-loco/flash_header.c Normal file
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@ -0,0 +1,101 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/byteorder.h>
#include <mach/imx-flash-header.h>
void __naked __flash_header_start go(void)
{
__asm__ __volatile__("b exception_vectors\n");
}
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), },
{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), },
{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), },
{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), },
{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), },
{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), },
{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), },
{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), },
{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), },
{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), },
{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), },
{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), },
{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x092080b0), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x09208138), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00001800), },
{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
};
#define APP_DEST CONFIG_TEXT_BASE
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = APP_DEST + 0x1000,
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + 0x400,
.boot_data.start = APP_DEST,
.boot_data.size = 0x40000,
.dcd.header.tag = DCD_HEADER_TAG,
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};

172
arch/arm/boards/freescale-mx53-loco/lowlevel_init.S Normal file
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@ -0,0 +1,172 @@
/*
* Copyright (C) 2007 Guennadi Liakhovetski <lg@denx.de>
* Copyright (C) 2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <config.h>
#include <mach/imx-regs.h>
#include <mach/clock-imx51_53.h>
/*
* L2CC Cache setup/invalidation/disable
*/
.macro init_l2cc
/* explicitly disable L2 cache */
mrc 15, 0, r0, c1, c0, 1
bic r0, r0, #0x2
mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */
mov r0, #0xC0 /* tag RAM */
add r0, r0, #0x4 /* data RAM */
orr r0, r0, #(1 << 24) /* disable write allocate delay */
orr r0, r0, #(1 << 23) /* disable write allocate combine */
orr r0, r0, #(1 << 22) /* disable write allocate */
cmp r3, #0x10 /* r3 contains the silicon rev */
/* disable write combine for TO 2 and lower revs */
orrls r0, r0, #(1 << 25)
mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
* The PACR default values are good.*/
.macro init_aips
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
ldr r0, =MX53_AIPS1_BASE_ADDR
ldr r1, =0x77777777
str r1, [r0, #0x0]
str r1, [r0, #0x4]
ldr r0, =MX53_AIPS2_BASE_ADDR
str r1, [r0, #0x0]
str r1, [r0, #0x4]
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
.endm /* init_aips */
.macro setup_pll pll, freq
ldr r0, =\pll
ldr r1, =0x00001232
str r1, [r0, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r0, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
ldr r1, W_DP_OP_\freq
str r1, [r0, #MX5_PLL_DP_OP]
str r1, [r0, #MX5_PLL_DP_HFS_OP]
ldr r1, W_DP_MFD_\freq
str r1, [r0, #MX5_PLL_DP_MFD]
str r1, [r0, #MX5_PLL_DP_HFS_MFD]
ldr r1, W_DP_MFN_\freq
str r1, [r0, #MX5_PLL_DP_MFN]
str r1, [r0, #MX5_PLL_DP_HFS_MFN]
ldr r1, =0x00001232
str r1, [r0, #MX5_PLL_DP_CTL]
1: ldr r1, [r0, #MX5_PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
.endm
.macro init_clock
ldr r0, =MX53_CCM_BASE_ADDR
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #MX5_CCM_CCSR]
setup_pll MX53_PLL1_BASE_ADDR, 1000
setup_pll MX53_PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
ldr r0, =MX53_ARM_BASE_ADDR
ldr r1, =0x00000725
str r1, [r0, #0x14]
ldr r0, =MX53_CCM_BASE_ADDR
mov r1, #0
str r1, [r0, #MX5_CCM_CACRR]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #MX5_CCM_CCSR]
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #MX5_CCM_CCGR0]
str r1, [r0, #MX5_CCM_CCGR1]
str r1, [r0, #MX5_CCM_CCGR2]
str r1, [r0, #MX5_CCM_CCGR3]
str r1, [r0, #MX5_CCM_CCGR4]
str r1, [r0, #MX5_CCM_CCGR5]
str r1, [r0, #MX5_CCM_CCGR6]
#if 0
str r1, [r0, #MX5_CCM_CCGR7]
#endif
ldr r1, [r0, #MX5_CCM_CSCDR1]
orr r1, r1, #0x3f
eor r1, r1, #0x3f
orr r1, r1, #0x21
str r1, [r0, #MX5_CCM_CSCDR1]
/* make sure divider effective */
1: ldr r1, [r0, #MX5_CCM_CDHIPR]
cmp r1, #0x0
bne 1b
mov r1, #0x0
str r1, [r0, #MX5_CCM_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #MX5_CCM_CCOSR]
.endm
.globl board_init_lowlevel
board_init_lowlevel:
mov r10, lr
init_l2cc
init_aips
init_clock
mov pc, r10
/* Board level setting value */
W_DP_OP_1000: .word MX5_PLL_DP_OP_1000
W_DP_MFD_1000: .word MX5_PLL_DP_MFD_1000
W_DP_MFN_1000: .word MX5_PLL_DP_MFN_1000
W_DP_OP_800: .word MX5_PLL_DP_OP_800
W_DP_MFD_800: .word MX5_PLL_DP_MFD_800
W_DP_MFN_800: .word MX5_PLL_DP_MFN_800
W_DP_OP_665: .word MX5_PLL_DP_OP_665
W_DP_MFD_665: .word MX5_PLL_DP_MFD_665
W_DP_MFN_665: .word MX5_PLL_DP_MFN_665
W_DP_OP_216: .word MX5_PLL_DP_OP_216
W_DP_MFD_216: .word MX5_PLL_DP_MFD_216
W_DP_MFN_216: .word MX5_PLL_DP_MFN_216

4
arch/arm/boards/freescale-mx53-loco/mx53-pdk.dox Normal file
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@ -0,0 +1,4 @@
/** @page board_loco Freescale i.MX53 PDK (Loco) Board
*/

87
arch/arm/boards/guf-cupid/board.c
View File

@ -43,44 +43,18 @@
#include <mach/imx-ipu-fb.h>
#include <mach/imx-pll.h>
#include <mach/iomux-mx35.h>
#include <mach/devices-imx35.h>
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
};
static struct device_d fec_dev = {
.id = -1,
.name = "fec_imx",
.map_base = IMX_FEC_BASE,
.platform_data = &fec_info,
};
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram0_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 128 * 1024 * 1024,
.platform_data = &ram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct device_d nand_dev = {
.id = -1,
.name = "imx_nand",
.map_base = IMX_NFC_BASE,
.platform_data = &nand_info,
};
static struct fb_videomode guf_cupid_fb_mode = {
/* 800x480 @ 70 Hz */
.name = "CPT CLAA070LC0JCT",
@ -122,38 +96,21 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = {
.enable = cupid_fb_enable,
};
static struct device_d imx_ipu_fb_dev = {
.id = -1,
.name = "imx-ipu-fb",
.map_base = 0x53fc0000,
.size = 0x1000,
.platform_data = &ipu_fb_data,
};
static struct device_d esdhc_dev = {
.name = "imx-esdhc",
.map_base = IMX_SDHC1_BASE,
};
#ifdef CONFIG_MMU
static int cupid_mmu_init(void)
static int cupid_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
#ifdef CONFIG_CACHE_L2X0
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
#endif
return 0;
}
postcore_initcall(cupid_mmu_init);
#endif
mem_initcall(cupid_mem_init);
static int cupid_mmu_init(void)
{
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
return 0;
}
postmmu_initcall(cupid_mmu_init);
static int cupid_devices_init(void)
{
@ -169,19 +126,17 @@ static int cupid_devices_init(void)
else
nand_info.width = 1; /* 8 bit */
register_device(&fec_dev);
register_device(&nand_dev);
imx35_add_fec(&fec_info);
imx35_add_nand(&nand_info);
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
register_device(&sdram0_dev);
register_device(&imx_ipu_fb_dev);
register_device(&esdhc_dev);
imx35_add_fb(&ipu_fb_data);
imx35_add_mmc0(NULL);
armlinux_add_dram(&sdram0_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_GUF_CUPID);
@ -190,13 +145,6 @@ static int cupid_devices_init(void)
device_initcall(cupid_devices_init);
static struct device_d cupid_serial_device = {
.id = -1,
.name = "imx_serial",
.map_base = IMX_UART1_BASE,
.size = 16 * 1024,
};
static struct pad_desc cupid_pads[] = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
@ -289,7 +237,8 @@ static int cupid_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(cupid_pads, ARRAY_SIZE(cupid_pads));
register_device(&cupid_serial_device);
imx35_add_uart0();
return 0;
}

46
arch/arm/boards/guf-neso/board.c
View File

@ -54,19 +54,6 @@
#define LCD_POWER_GPIO (GPIO_PORTF + 18)
#define BACKLIGHT_POWER_GPIO (GPIO_PORTE + 5)
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0xa0000000,
.size = 128 * 1024 * 1024,
.platform_data = &ram_pdata,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 31,
@ -127,14 +114,6 @@ static struct imx_fb_platform_data neso_fb_data = {
};
#ifdef CONFIG_USB
static struct device_d usbh2_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE + 0x400,
.size = 0x200,
};
static void neso_usbh_init(void)
{
uint32_t temp;
@ -157,23 +136,13 @@ static void neso_usbh_init(void)
}
#endif
#ifdef CONFIG_MMU
static void neso_mmu_init(void)
static int neso_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
return 0;
}
#else
static void neso_mmu_init(void)
{
}
#endif
mem_initcall(neso_mem_init);
static int neso_devices_init(void)
{
@ -301,20 +270,16 @@ static int neso_devices_init(void)
gpio_direction_output(OTG_PHY_CS_GPIO, 1);
gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
neso_mmu_init();
/* initialize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
imx27_add_nand(&nand_info);
register_device(&sdram_dev);
imx27_add_fb(&neso_fb_data);
#ifdef CONFIG_USB
neso_usbh_init();
register_device(&usbh2_dev);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
#endif
imx27_add_fec(&fec_info);
@ -325,7 +290,6 @@ static int neso_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_NESO);

42
arch/arm/boards/imx21ads/imx21ads.c
View File

@ -41,38 +41,11 @@
#define MX21ADS_IO_REG 0xCC800000
#define MX21ADS_IO_LCDON (1 << 9)
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC8000000,
.size = 32 * 1024 * 1024,
};
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0xc0000000,
.size = 64 * 1024 * 1024,
.platform_data = &ram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
};
static struct device_d cs8900_dev = {
.id = -1,
.name = "cs8900",
.map_base = IMX_CS1_BASE,
// IRQ is connected to UART3_RTS
};
/* Sharp LQ035Q7DB02 QVGA display */
static struct imx_fb_videomode imx_fb_modedata = {
.mode = {
@ -142,6 +115,14 @@ static int imx21ads_timing_init(void)
core_initcall(imx21ads_timing_init);
static int mx21ads_mem_init(void)
{
arm_add_mem_device("ram0", 0xc0000000, 64 * 1024 * 1024);
return 0;
}
mem_initcall(mx21ads_mem_init);
static int mx21ads_devices_init(void)
{
int i;
@ -183,13 +164,12 @@ static int mx21ads_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&cfi_dev);
register_device(&sdram_dev);
add_cfi_flash_device(-1, 0xC8000000, 32 * 1024 * 1024, 0);
imx21_add_nand(&nand_info);
register_device(&cs8900_dev);
add_generic_device("cs8900", -1, NULL, IMX_CS1_BASE, 0x1000,
IORESOURCE_MEM, NULL);
imx21_add_fb(&imx_fb_data);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xc0000100);
armlinux_set_architecture(MACH_TYPE_MX21ADS);

34
arch/arm/boards/imx27ads/imx27ads.c
View File

@ -34,26 +34,6 @@
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC0000000,
.size = 32 * 1024 * 1024,
};
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0xa0000000,
.size = 128 * 1024 * 1024,
.platform_data = &ram_pdata,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 1,
@ -94,6 +74,14 @@ static int imx27ads_timing_init(void)
core_initcall(imx27ads_timing_init);
static int mx27ads_mem_init(void)
{
arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
return 0;
}
mem_initcall(mx27ads_mem_init);
static int mx27ads_devices_init(void)
{
int i;
@ -126,15 +114,13 @@ static int mx27ads_devices_init(void)
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&cfi_dev);
register_device(&sdram_dev);
imx27_add_fec(&fec_info);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_fec(&fec_info);
devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_MX27ADS);

72
arch/arm/boards/karo-tx25/board.c
View File

@ -36,6 +36,7 @@
#include <nand.h>
#include <mach/iomux-mx25.h>
#include <mach/generic.h>
#include <mach/iim.h>
#include <linux/err.h>
#include <mach/devices-imx25.h>
#include <asm/mmu.h>
@ -45,74 +46,22 @@ static struct fec_platform_data fec_info = {
.phy_addr = 0x1f,
};
static struct memory_platform_data sdram0_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram0_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 32 * 1024 * 1024,
.platform_data = &sdram0_pdata,
};
static struct memory_platform_data sdram1_pdata = {
.name = "ram1",
.flags = DEVFS_RDWR,
};
static struct device_d sdram1_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS1,
.size = 32 * 1024 * 1024,
.platform_data = &sdram1_pdata,
};
static struct memory_platform_data sram_pdata = {
.name = "sram0",
.flags = DEVFS_RDWR,
};
static struct device_d sram0_dev = {
.id = -1,
.name = "mem",
.map_base = 0x78000000,
.size = 128 * 1024,
.platform_data = &sram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
#ifdef CONFIG_MMU
static int tx25_mmu_init(void)
static int tx25_mem_init(void)
{
mmu_init();
arm_create_section(0x80000000, 0x80000000, 32, PMD_SECT_DEF_CACHED);
arm_create_section(0x82000000, 0x80000000, 32, PMD_SECT_DEF_UNCACHED);
arm_create_section(0x90000000, 0x90000000, 32, PMD_SECT_DEF_CACHED);
arm_create_section(0x92000000, 0x90000000, 32, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x02000000);
#if TEXT_BASE & (0x100000 - 1)
#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
#else
arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
#endif
mmu_enable();
arm_add_mem_device("ram0", IMX_SDRAM_CS0, 32 * 1024 * 1024);
arm_add_mem_device("ram0", IMX_SDRAM_CS1, 32 * 1024 * 1024);
add_mem_device("ram0", 0x78000000, 128 * 1024,
IORESOURCE_MEM_WRITEABLE);
return 0;
}
postcore_initcall(tx25_mmu_init);
#endif
mem_initcall(tx25_mem_init);
static struct pad_desc karo_tx25_padsd_fec[] = {
MX25_PAD_D11__GPIO_4_9, /* FEC PHY power on pin */
@ -158,6 +107,7 @@ static int tx25_devices_init(void)
{
gpio_fec_active();
imx25_iim_register_fec_ethaddr();
imx25_add_fec(&fec_info);
if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
@ -171,12 +121,6 @@ static int tx25_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
register_device(&sdram0_dev);
register_device(&sdram1_dev);
register_device(&sram0_dev);
armlinux_add_dram(&sdram0_dev);
armlinux_add_dram(&sdram1_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_TX25);
armlinux_set_serial(imx_uid());

39
arch/arm/boards/karo-tx28/tx28-stk5.c
View File

@ -35,24 +35,12 @@ static struct mxs_mci_platform_data mci_pdata = {
.f_max = 25000000,
};
static struct device_d mci_socket = {
.name = "mxs_mci",
.map_base = IMX_SSP0_BASE,
.platform_data = &mci_pdata,
};
/* PhyAD[0..2]=0, RMIISEL=1 */
static struct fec_platform_data fec_info = {
.xcv_type = RMII,
.phy_addr = 0,
};
static struct device_d fec_dev = {
.name = "fec_imx",
.map_base = IMX_FEC0_BASE,
.platform_data = &fec_info,
};
/*
* The TX28 EVK comes with a VGA connector. We can support many video modes
*
@ -215,13 +203,6 @@ static struct imx_fb_platformdata tx28_fb_pdata = {
.enable = tx28_fb_enable,
};
static struct device_d ldcif_dev = {
.name = "stmfb",
.map_base = IMX_FB_BASE,
.size = 4096,
.platform_data = &tx28_fb_pdata,
};
static const uint32_t tx28_starterkit_pad_setup[] = {
/*
* Part II of phy's initialization
@ -378,17 +359,20 @@ void base_board_init(void)
/* run the SSP unit clock at 100 MHz */
imx_set_sspclk(0, 100000000, 1);
register_device(&mci_socket);
add_generic_device("mxs_mci", 0, NULL, IMX_SSP0_BASE, 0,
IORESOURCE_MEM, &mci_pdata);
if (tx28_fb_pdata.fixed_screen < (void *)&_end) {
printf("Warning: fixed_screen overlaps barebox\n");
tx28_fb_pdata.fixed_screen = NULL;
}
register_device(&ldcif_dev);
add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 4096,
IORESOURCE_MEM, &tx28_fb_pdata);
imx_enable_enetclk();
register_device(&fec_dev);
add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0,
IORESOURCE_MEM, &fec_info);
ret = register_persistent_environment();
if (ret != 0)
@ -396,15 +380,12 @@ void base_board_init(void)
"storage (%d)\n", ret);
}
static struct device_d tx28kit_serial_device = {
.name = "stm_serial",
.map_base = IMX_DBGUART_BASE,
.size = 8192,
};
static int tx28kit_console_init(void)
{
return register_device(&tx28kit_serial_device);
add_generic_device("stm_serial", 0, NULL, IMX_DBGUART_BASE, 8192,
IORESOURCE_MEM, NULL);
return 0;
}
console_initcall(tx28kit_console_init);

33
arch/arm/boards/karo-tx28/tx28.c
View File

@ -23,19 +23,6 @@
#include <mach/imx-regs.h>
#include <asm/mmu.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_MEMORY_BASE,
.size = 128 * 1024 * 1024,
.platform_data = &ram_pdata,
};
/* setup the CPU card internal signals */
static const uint32_t tx28_pad_setup[] = {
/* NAND interface */
@ -83,22 +70,13 @@ static const uint32_t tx28_pad_setup[] = {
extern void base_board_init(void);
#ifdef CONFIG_MMU
static int tx28_mmu_init(void)
static int tx28_mem_init(void)
{
mmu_init();
arm_create_section(0x40000000, 0x40000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x50000000, 0x40000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
arm_add_mem_device("ram0", IMX_MEMORY_BASE, 128 * 1024 * 1024);
return 0;
}
postcore_initcall(tx28_mmu_init);
#endif
mem_initcall(tx28_mem_init);
static int tx28_devices_init(void)
{
@ -108,10 +86,7 @@ static int tx28_devices_init(void)
for (i = 0; i < ARRAY_SIZE(tx28_pad_setup); i++)
imx_gpio_mode(tx28_pad_setup[i]);
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)(sdram_dev.map_base + 0x100));
armlinux_set_bootparams((void *)IMX_MEMORY_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_TX28);
base_board_init();

76
arch/arm/boards/mini2440/mini2440.c
View File

@ -44,29 +44,11 @@
#include <mach/mci.h>
#include <mach/fb.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = CS6_BASE,
.platform_data = &ram_pdata,
};
static struct s3c24x0_nand_platform_data nand_info = {
.nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1),
.flash_bbt = 1, /* same as the kernel */
};
static struct device_d nand_dev = {
.name = "s3c24x0_nand",
.map_base = S3C24X0_NAND_BASE,
.platform_data = &nand_info,
};
/*
* dm9000 network controller onboard
* Connected to CS line 4 and interrupt line EINT7,
@ -75,19 +57,9 @@ static struct device_d nand_dev = {
* Area 2: Offset 0x304...0x307
*/
static struct dm9000_platform_data dm9000_data = {
.iobase = CS4_BASE + 0x300,
.iodata = CS4_BASE + 0x304,
.buswidth = DM9000_WIDTH_16,
.srom = 1,
};
static struct device_d dm9000_dev = {
.name = "dm9000",
.map_base = CS4_BASE + 0x300,
.size = 8,
.platform_data = &dm9000_data,
};
static struct s3c_mci_platform_data mci_data = {
.caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
@ -95,12 +67,6 @@ static struct s3c_mci_platform_data mci_data = {
.detect_invert = 0,
};
static struct device_d mci_dev = {
.name = "s3c_mci",
.map_base = S3C2410_SDI_BASE,
.platform_data = &mci_data,
};
static struct fb_videomode s3c24x0_fb_modes[] = {
#ifdef CONFIG_MINI2440_VIDEO_N35
{
@ -166,12 +132,6 @@ static struct s3c_fb_platform_data s3c24x0_fb_data = {
.passive_display = 0,
};
static struct device_d s3cfb_dev = {
.name = "s3c_fb",
.map_base = S3C2410_LCD_BASE,
.platform_data = &s3c24x0_fb_data,
};
static const unsigned pin_usage[] = {
/* address bus, used by NOR, SDRAM */
GPA1_ADDR16,
@ -303,13 +263,19 @@ static const unsigned pin_usage[] = {
GPH7_RXD2,
};
static int mini2440_mem_init(void)
{
arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
return 0;
}
mem_initcall(mini2440_mem_init);
static int mini2440_devices_init(void)
{
uint32_t reg;
int i;
sdram_dev.size = s3c24x0_get_memory_size();
/* ----------- configure the access to the outer space ---------- */
for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
s3c_gpio_mode(pin_usage[i]);
@ -328,9 +294,11 @@ static int mini2440_devices_init(void)
reg |= 0x10000;
writel(reg, MISCCR);
register_device(&nand_dev);
register_device(&sdram_dev);
register_device(&dm9000_dev);
add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
IORESOURCE_MEM, &nand_info);
add_dm9000_device(0, CS4_BASE + 0x300, CS4_BASE + 0x304,
IORESOURCE_MEM_16BIT, &dm9000_data);
#ifdef CONFIG_NAND
/* ----------- add some vital partitions -------- */
devfs_del_partition("self_raw");
@ -341,10 +309,11 @@ static int mini2440_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
register_device(&mci_dev);
register_device(&s3cfb_dev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
add_generic_device("s3c_mci", 0, NULL, S3C2410_SDI_BASE, 0,
IORESOURCE_MEM, &mci_data);
add_generic_device("s3c_fb", 0, NULL, S3C2410_LCD_BASE, 0,
IORESOURCE_MEM, &s3c24x0_fb_data);
armlinux_set_bootparams((void*)CS6_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_MINI2440);
return 0;
@ -359,12 +328,6 @@ void __bare_init nand_boot(void)
}
#endif
static struct device_d mini2440_serial_device = {
.name = "s3c24x0_serial",
.map_base = UART1_BASE,
.size = UART1_SIZE,
};
static int mini2440_console_init(void)
{
/*
@ -376,7 +339,8 @@ static int mini2440_console_init(void)
s3c_gpio_mode(GPH2_TXD0);
s3c_gpio_mode(GPH3_RXD0);
register_device(&mini2440_serial_device);
add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
IORESOURCE_MEM, NULL);
return 0;
}

18
arch/arm/boards/mmccpu/init.c
View File

@ -37,18 +37,19 @@
#include <mach/gpio.h>
#include <mach/io.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = AT91_CHIPSELECT_0,
.size = 0, /* zero means autodetect size */
};
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_MII | AT91SAM_ETHER_FORCE_LINK,
.phy_addr = 4,
};
static int mmccpu_mem_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
return 0;
}
mem_initcall(mmccpu_mem_init);
static int mmccpu_devices_init(void)
{
/*
@ -59,9 +60,8 @@ static int mmccpu_devices_init(void)
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
at91_add_device_sdram(128 * 1024 * 1024);
at91_add_device_eth(&macb_pdata);
register_device(&cfi_dev);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0");

57
arch/arm/boards/netx/netx.c
View File

@ -30,51 +30,27 @@
#include <generated/mach-types.h>
#include <mach/netx-eth.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC0000000,
.size = 32 * 1024 * 1024,
};
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x80000000,
.size = 64 * 1024 * 1024,
.platform_data = &ram_pdata,
};
struct netx_eth_platform_data eth0_data = {
.xcno = 0,
};
static struct device_d netx_eth_dev0 = {
.id = -1,
.name = "netx-eth",
.platform_data = &eth0_data,
};
struct netx_eth_platform_data eth1_data = {
.xcno = 1,
};
static struct device_d netx_eth_dev1 = {
.id = -1,
.name = "netx-eth",
.platform_data = &eth1_data,
};
static int netx_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, 64 * 1024 * 1024);
return 0;
}
mem_initcall(netx_mem_init);
static int netx_devices_init(void) {
register_device(&cfi_dev);
register_device(&sdram_dev);
register_device(&netx_eth_dev0);
register_device(&netx_eth_dev1);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, &eth0_data);
add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, &eth1_data);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
@ -83,7 +59,6 @@ static int netx_devices_init(void) {
protect_file("/dev/env0", 1);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_NXDB500);
@ -92,13 +67,6 @@ static int netx_devices_init(void) {
device_initcall(netx_devices_init);
static struct device_d netx_serial_device = {
.id = -1,
.name = "netx_serial",
.map_base = NETX_PA_UART0,
.size = 0x40,
};
static int netx_console_init(void)
{
/* configure gpio for serial */
@ -107,7 +75,8 @@ static int netx_console_init(void)
*(volatile unsigned long *)(0x00100808) = 2;
*(volatile unsigned long *)(0x0010080c) = 2;
register_device(&netx_serial_device);
add_generic_device("netx_serial", -1, NULL, NETX_PA_UART0, 0x40,
IORESOURCE_MEM, NULL);
return 0;
}

39
arch/arm/boards/nhk8815/setup.c
View File

@ -33,13 +33,6 @@
#include <mach/nand.h>
#include <mach/fsmc.h>
static struct device_d nhk8815_network_dev = {
.id = -1,
.name = "smc91c111",
.map_base = 0x34000300,
.size = 16,
};
static int nhk8815_nand_init(void)
{
/* FSMC setup for nand chip select (8-bit nand in 8815NHK) */
@ -54,24 +47,45 @@ static int nhk8815_nand_init(void)
}
static struct nomadik_nand_platform_data nhk8815_nand_data = {
.addr_va = NAND_IO_ADDR,
.cmd_va = NAND_IO_CMD,
.data_va = NAND_IO_DATA,
.options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \
| NAND_NO_READRDY | NAND_NO_AUTOINCR,
.init = nhk8815_nand_init,
};
static struct resource nhk8815_nand_resources[] = {
{
.start = NAND_IO_ADDR,
.size = 0xfff,
.flags = IORESOURCE_MEM,
}, {
.start = NAND_IO_CMD,
.size = 0xfff,
.flags = IORESOURCE_MEM,
}, {
.start = NAND_IO_DATA,
.size = 0xfff,
.flags = IORESOURCE_MEM,
}
};
static struct device_d nhk8815_nand_device = {
.id = -1,
.name = "nomadik_nand",
.num_resources = ARRAY_SIZE(nhk8815_nand_resources),
.resource = nhk8815_nand_resources,
.platform_data = &nhk8815_nand_data,
};
static int nhk8815_devices_init(void)
static int nhk8815_mem_init(void)
{
st8815_add_device_sdram(64 * 1024 *1024);
return 0;
}
mem_initcall(nhk8815_mem_init);
static int nhk8815_devices_init(void)
{
writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
@ -81,7 +95,8 @@ static int nhk8815_devices_init(void)
writel(0x0000305b, FSMC_BCR(1));
writel(0x00033f33, FSMC_BTR(1));
register_device(&nhk8815_network_dev);
add_generic_device("smc91c111", -1, NULL, 0x34000300, 16,
IORESOURCE_MEM, NULL);
register_device(&nhk8815_nand_device);

78
arch/arm/boards/omap/board-beagle.c
View File

@ -237,17 +237,6 @@ void board_init(void)
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
.reg_read = omap_uart_read,
.reg_write = omap_uart_write,
};
static struct device_d beagle_serial_device = {
.id = -1,
.name = "serial_ns16550",
.map_base = OMAP_UART3_BASE,
.size = 1024,
.platform_data = (void *)&serial_plat,
};
/**
@ -259,24 +248,14 @@ static struct device_d beagle_serial_device = {
static int beagle_console_init(void)
{
/* Register the serial port */
return register_device(&beagle_serial_device);
add_ns16550_device(-1, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
&serial_plat);
return 0;
}
console_initcall(beagle_console_init);
#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
static struct memory_platform_data sram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x80000000,
.size = 128 * 1024 * 1024,
.platform_data = &sram_pdata,
};
#ifdef CONFIG_USB_EHCI_OMAP
static struct omap_hcd omap_ehci_pdata = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
@ -290,52 +269,33 @@ static struct omap_hcd omap_ehci_pdata = {
static struct ehci_platform_data ehci_pdata = {
.flags = 0,
.hccr_offset = 0x100,
.hcor_offset = 0x110,
};
static struct device_d usbh_dev = {
.id = -1,
.name = "ehci",
.map_base = 0x48064700,
.size = 4 * 1024,
.platform_data = &ehci_pdata,
};
#endif /* CONFIG_USB_EHCI_OMAP */
static struct device_d i2c_dev = {
.id = -1,
.name = "i2c-omap",
.map_base = OMAP_I2C1_BASE,
};
static struct i2c_board_info i2c_devices[] = {
{
I2C_BOARD_INFO("twl4030", 0x48),
},
};
static struct device_d hsmmc_dev = {
.id = -1,
.name = "omap-hsmmc",
.map_base = 0x4809C000,
.size = SZ_4K,
};
static int beagle_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
return 0;
}
mem_initcall(beagle_mem_init);
static int beagle_devices_init(void)
{
int ret;
ret = register_device(&sdram_dev);
if (ret)
goto failed;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
register_device(&i2c_dev);
add_generic_device("i2c-omap", -1, NULL, 0x4809C000, SZ_4K,
IORESOURCE_MEM, NULL);
#ifdef CONFIG_USB_EHCI_OMAP
if (ehci_omap_init(&omap_ehci_pdata) >= 0)
register_device(&usbh_dev);
add_usb_ehci_device(-1, 0x48064700 + 0x100,
0x48064700 + 0x110, &ehci_pdata);
#endif /* CONFIG_USB_EHCI_OMAP */
#ifdef CONFIG_GPMC
/* WP is made high and WAIT1 active Low */
@ -343,13 +303,13 @@ static int beagle_devices_init(void)
#endif
gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_HAMMING_CODE_HW_ROMCODE);
register_device(&hsmmc_dev);
add_generic_device("omap-hsmmc", -1, NULL, OMAP_I2C1_BASE, 0,
IORESOURCE_MEM, NULL);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP3_BEAGLE);
failed:
return ret;
return 0;
}
device_initcall(beagle_devices_init);

55
arch/arm/boards/omap/board-omap3evm.c
View File

@ -58,6 +58,7 @@
#include <mach/control.h>
#include <mach/omap3-mux.h>
#include <mach/gpmc.h>
#include <errno.h>
#include "board.h"
@ -212,21 +213,6 @@ void board_init(void)
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
.reg_read = omap_uart_read,
.reg_write = omap_uart_write,
};
static struct device_d omap3evm_serial_device = {
.id = -1,
.name = "serial_ns16550",
#if defined(CONFIG_OMAP3EVM_UART1)
.map_base = OMAP_UART1_BASE,
#elif defined(CONFIG_OMAP3EVM_UART3)
.map_base = OMAP_UART3_BASE,
#endif
.size = 1024,
.platform_data = (void *)&serial_plat,
};
/**
@ -236,42 +222,35 @@ static struct device_d omap3evm_serial_device = {
*/
static int omap3evm_init_console(void)
{
return register_device(&omap3evm_serial_device);
add_ns16550_device(-1,
#if defined(CONFIG_OMAP3EVM_UART1)
OMAP_UART1_BASE,
#elif defined(CONFIG_OMAP3EVM_UART3)
OMAP_UART3_BASE,
#endif
1024, IORESOURCE_MEM_8BIT, &serial_plat);
return 0;
}
console_initcall(omap3evm_init_console);
#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
static struct memory_platform_data sram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static int omap3evm_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x80000000,
.size = 128 * 1024 * 1024,
.platform_data = &sram_pdata,
};
return 0;
}
mem_initcall(omap3evm_mem_init);
static int omap3evm_init_devices(void)
{
int ret;
ret = register_device(&sdram_dev);
if (ret)
goto failed;
#ifdef CONFIG_GPMC
/*
* WP is made high and WAIT1 active Low
*/
gpmc_generic_init(0x10);
#endif
armlinux_add_dram(&sdram_dev);
failed:
return ret;
return 0;
}
device_initcall(omap3evm_init_devices);

59
arch/arm/boards/omap/board-sdp343x.c
View File

@ -61,6 +61,7 @@
#include <mach/control.h>
#include <mach/omap3-mux.h>
#include <mach/gpmc.h>
#include <errno.h>
#include "board.h"
/******************** Board Boot Time *******************/
@ -604,17 +605,6 @@ static void mux_config(void)
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
.reg_read = omap_uart_read,
.reg_write = omap_uart_write,
};
static struct device_d sdp3430_serial_device = {
.id = -1,
.name = "serial_ns16550",
.map_base = OMAP_UART3_BASE,
.size = 1024,
.platform_data = (void *)&serial_plat,
};
/**
@ -625,50 +615,31 @@ static struct device_d sdp3430_serial_device = {
static int sdp3430_console_init(void)
{
/* Register the serial port */
return register_device(&sdp3430_serial_device);
add_ns16550_device(-1, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
&serial_plat);
return 0;
}
console_initcall(sdp3430_console_init);
#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
/*------------------------- FLASH Devices -----------------------------------*/
static int sdp3430_flash_init(void)
static int sdp3430_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
return 0;
}
mem_initcall(sdp3430_mem_init);
static int sdp3430_devices_init(void)
{
#ifdef CONFIG_GPMC
/* WP is made high and WAIT1 active Low */
gpmc_generic_init(0x10);
#endif
return 0;
}
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x80000000,
.size = 128 * 1024 * 1024,
.platform_data = &ram_pdata,
};
/*-----------------------Generic Devices Initialization ---------------------*/
static int sdp3430_devices_init(void)
{
int ret;
ret = register_device(&sdram_dev);
if (ret)
goto failed;
ret = sdp3430_flash_init();
if (ret)
goto failed;
armlinux_add_dram(&sdram_dev);
failed:
return ret;
}
device_initcall(sdp3430_devices_init);

80
arch/arm/boards/panda/board.c
View File

@ -32,66 +32,29 @@ static int board_revision;
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
.reg_read = omap_uart_read,
.reg_write = omap_uart_write,
};
static struct device_d panda_serial_device = {
.id = -1,
.name = "serial_ns16550",
.map_base = OMAP44XX_UART3_BASE,
.size = 1024,
.platform_data = (void *)&serial_plat,
};
static int panda_console_init(void)
{
/* Register the serial port */
return register_device(&panda_serial_device);
}
console_initcall(panda_console_init);
static struct memory_platform_data sram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x80000000,
.size = SZ_1G,
.platform_data = &sram_pdata,
};
#ifdef CONFIG_MMU
static int panda_mmu_init(void)
{
mmu_init();
arm_create_section(0x80000000, 0x80000000, 256, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 256, PMD_SECT_DEF_UNCACHED);
mmu_enable();
add_ns16550_device(-1, OMAP44XX_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
&serial_plat);
return 0;
}
device_initcall(panda_mmu_init);
#endif
console_initcall(panda_console_init);
static int panda_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, SZ_1G);
return 0;
}
mem_initcall(panda_mem_init);
#ifdef CONFIG_USB_EHCI
static struct ehci_platform_data ehci_pdata = {
.flags = 0,
.hccr_offset = 0x0,
.hcor_offset = 0x10,
};
static struct device_d usbh_dev = {
.id = -1,
.name = "ehci",
.map_base = 0x4a064c00,
.size = 4 * 1024,
.platform_data = &ehci_pdata,
};
static void panda_ehci_init(void)
@ -124,8 +87,13 @@ static void panda_ehci_init(void)
/* enable power to hub */
gpio_set_value(GPIO_HUB_POWER, 1);
register_device(&usbh_dev);
add_usb_ehci_device(-1, 0x4a064c00,
0x4a064c00 + 0x10, &ehci_pdata);
}
#else
static void panda_ehci_init(void)
{}
#endif
static void __init panda_boardrev_init(void)
{
@ -136,13 +104,6 @@ static void __init panda_boardrev_init(void)
pr_info("PandaBoard Revision: %03d\n", board_revision);
}
static struct device_d hsmmc_dev = {
.id = -1,
.name = "omap-hsmmc",
.map_base = 0x4809C100,
.size = SZ_4K,
};
static int panda_devices_init(void)
{
panda_boardrev_init();
@ -171,11 +132,10 @@ static int panda_devices_init(void)
sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
}
register_device(&sdram_dev);
register_device(&hsmmc_dev);
add_generic_device("omap-hsmmc", -1, NULL, 0x4809C100, SZ_4K,
IORESOURCE_MEM, NULL);
panda_ehci_init();
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP4_PANDA);

148
arch/arm/boards/pcm037/pcm037.c
View File

@ -39,87 +39,18 @@
#include <mach/imx-nand.h>
#include <mach/devices-imx31.h>
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = IMX_CS0_BASE,
.size = 32 * 1024 * 1024, /* area size */
};
/*
* up to 2MiB static RAM type memory, connected
* to CS4, data width is 16 bit
*/
static struct memory_platform_data sram_dev_pdata0 = {
.name = "sram0",
.flags = DEVFS_RDWR,
};
static struct device_d sram_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_CS4_BASE,
.size = IMX_CS4_RANGE, /* area size */
.platform_data = &sram_dev_pdata0,
};
/*
* SMSC 9217 network controller
* connected to CS line 1 and interrupt line
* GPIO3, data width is 16 bit
*/
static struct device_d network_dev = {
.id = -1,
.name = "smc911x",
.map_base = IMX_CS1_BASE,
.size = IMX_CS1_RANGE, /* area size */
};
#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
#define SDRAM0 128
#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
#define SDRAM0 256
#endif
static struct memory_platform_data ram_dev_pdata0 = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram0_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = SDRAM0 * 1024 * 1024, /* fix size */
.platform_data = &ram_dev_pdata0,
};
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
#define SDRAM1 128
#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
#define SDRAM1 256
#endif
static struct memory_platform_data ram_dev_pdata1 = {
.name = "ram1",
.flags = DEVFS_RDWR,
};
static struct device_d sdram1_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS1,
.size = SDRAM1 * 1024 * 1024, /* fix size */
.platform_data = &ram_dev_pdata1,
};
#endif
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
@ -127,20 +58,6 @@ struct imx_nand_platform_data nand_info = {
};
#ifdef CONFIG_USB
static struct device_d usbotg_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE,
.size = 0x200,
};
static struct device_d usbh2_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE + 0x400,
.size = 0x200,
};
static void pcm037_usb_init(void)
{
u32 tmp;
@ -229,32 +146,27 @@ static void pcm037_usb_init(void)
}
#endif
#ifdef CONFIG_MMU
static void pcm037_mmu_init(void)
static int pcm037_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM0 * 1024 * 1024);
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
arm_add_mem_device("ram1", IMX_SDRAM_CS1, SDRAM1 * 1024 * 1024);
#endif
arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
return 0;
}
mem_initcall(pcm037_mem_init);
setup_dma_coherent(0x10000000);
mmu_enable();
#ifdef CONFIG_CACHE_L2X0
static int pcm037_mmu_init(void)
{
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
#endif
return 0;
}
#else
static void pcm037_mmu_init(void)
{
}
#endif
postmmu_initcall(pcm037_mmu_init);
static int imx31_devices_init(void)
{
pcm037_mmu_init();
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
__REG(CSCR_L(0)) = 0x10000d03;
__REG(CSCR_A(0)) = 0x00720900;
@ -271,7 +183,11 @@ static int imx31_devices_init(void)
__REG(CSCR_L(5)) = 0x444A0301;
__REG(CSCR_A(5)) = 0x44443302;
register_device(&cfi_dev);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(-1, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
/*
* Create partitions that should be
@ -282,24 +198,28 @@ static int imx31_devices_init(void)
protect_file("/dev/env0", 1);
register_device(&sram_dev);
/*
* up to 2MiB static RAM type memory, connected
* to CS4, data width is 16 bit
*/
add_mem_device("sram0", IMX_CS4_BASE, IMX_CS4_RANGE, /* area size */
IORESOURCE_MEM_WRITEABLE);
imx31_add_nand(&nand_info);
register_device(&network_dev);
register_device(&sdram0_dev);
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
register_device(&sdram1_dev);
#endif
/*
* SMSC 9217 network controller
* connected to CS line 1 and interrupt line
* GPIO3, data width is 16 bit
*/
add_generic_device("smc911x", -1, NULL, IMX_CS1_BASE, IMX_CS1_RANGE,
IORESOURCE_MEM, NULL);
#ifdef CONFIG_USB
pcm037_usb_init();
register_device(&usbotg_dev);
register_device(&usbh2_dev);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE, NULL);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
#endif
armlinux_add_dram(&sdram0_dev);
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
armlinux_add_dram(&sdram1_dev);
#endif
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_PCM037);

70
arch/arm/boards/pcm038/pcm038.c
View File

@ -47,39 +47,6 @@
#include "pll.h"
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0xC0000000,
.size = 32 * 1024 * 1024,
};
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0xa0000000,
.size = 128 * 1024 * 1024,
.platform_data = &ram_pdata,
};
static struct memory_platform_data sram_pdata = {
.name = "sram0",
.flags = DEVFS_RDWR,
};
static struct device_d sram_dev = {
.id = -1,
.name = "mem",
.map_base = 0xc8000000,
.size = 512 * 1024, /* Can be up to 2MiB */
.platform_data = &sram_pdata,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 1,
@ -142,13 +109,6 @@ static struct imx_fb_platform_data pcm038_fb_data = {
};
#ifdef CONFIG_USB
static struct device_d usbh2_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE + 0x400,
.size = 0x200,
};
static void pcm038_usbh_init(void)
{
uint32_t temp;
@ -169,23 +129,15 @@ static void pcm038_usbh_init(void)
}
#endif
#ifdef CONFIG_MMU
static void pcm038_mmu_init(void)
static int pcm038_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
add_mem_device("ram0", 0xc8000000, 512 * 1024, /* Can be up to 2MiB */
IORESOURCE_MEM_WRITEABLE);
return 0;
}
#else
static void pcm038_mmu_init(void)
{
}
#endif
mem_initcall(pcm038_mem_init);
static int pcm038_devices_init(void)
{
@ -263,8 +215,6 @@ static int pcm038_devices_init(void)
PD26_AF_USBH2_DATA5,
};
pcm038_mmu_init();
/* configure 16 bit nor flash on cs0 */
CS0U = 0x0000CC03;
CS0L = 0xa0330D01;
@ -289,18 +239,17 @@ static int pcm038_devices_init(void)
gpio_direction_output(GPIO_PORTD | 28, 0);
gpio_set_value(GPIO_PORTD | 28, 0);
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
register_device(&cfi_dev);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_nand(&nand_info);
register_device(&sdram_dev);
register_device(&sram_dev);
imx27_add_fb(&pcm038_fb_data);
#ifdef CONFIG_USB
pcm038_usbh_init();
register_device(&usbh2_dev);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
#endif
/* Register the fec device after the PLL re-initialisation
@ -330,7 +279,6 @@ static int pcm038_devices_init(void)
printf("Using environment in %s Flash\n", envdev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_PCM038);

60
arch/arm/boards/pcm043/pcm043.c
View File

@ -46,34 +46,10 @@
#include <mach/iomux-mx35.h>
#include <mach/devices-imx35.h>
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = IMX_CS0_BASE,
.size = 32 * 1024 * 1024, /* area size */
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
};
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram0_dev = {
.id = -1,
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 128 * 1024 * 1024,
.platform_data = &ram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
@ -123,25 +99,21 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = {
.bpp = 16,
};
#ifdef CONFIG_MMU
static int pcm043_mmu_init(void)
static int pcm043_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
#ifdef CONFIG_CACHE_L2X0
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
#endif
return 0;
}
postcore_initcall(pcm043_mmu_init);
#endif
mem_initcall(pcm043_mem_init);
static int pcm043_mmu_init(void)
{
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
return 0;
}
postmmu_initcall(pcm043_mmu_init);
struct gpio_led led0 = {
.gpio = 1 * 32 + 6,
@ -170,7 +142,11 @@ static int imx35_devices_init(void)
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
register_device(&cfi_dev);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(-1, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */
switch ( (reg >> 25) & 0x3) {
@ -189,10 +165,9 @@ static int imx35_devices_init(void)
}
}
register_device(&sdram0_dev);
imx35_add_fb(&ipu_fb_data);
armlinux_add_dram(&sdram0_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_PCM043);
@ -236,6 +211,7 @@ static int imx35_console_init(void)
mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
imx35_add_uart0();
return 0;
}

84
arch/arm/boards/pcm049/board.c
View File

@ -43,81 +43,26 @@
static struct NS16550_plat serial_plat = {
.clock = 48000000, /* 48MHz (APLL96/2) */
.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
.reg_read = omap_uart_read,
.reg_write = omap_uart_write,
};
static struct device_d pcm049_serial_device = {
.id = -1,
.name = "serial_ns16550",
.map_base = OMAP44XX_UART3_BASE,
.size = 1024,
.platform_data = (void *)&serial_plat,
};
static int pcm049_console_init(void)
{
/* Register the serial port */
return register_device(&pcm049_serial_device);
}
console_initcall(pcm049_console_init);
static struct memory_platform_data sram_pdata = {
.name = "sram0",
.flags = DEVFS_RDWR,
};
static struct device_d sram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x40300000,
.size = 48 * 1024,
.platform_data = &sram_pdata,
};
static struct memory_platform_data sdram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x80000000,
.size = SZ_512M,
.platform_data = &sdram_pdata,
};
#ifdef CONFIG_MMU
static int pcm049_mmu_init(void)
{
mmu_init();
arm_create_section(0x80000000, 0x80000000, 256, PMD_SECT_DEF_CACHED);
/* warning: This shadows the second half of our ram */
arm_create_section(0x90000000, 0x80000000, 256, PMD_SECT_DEF_UNCACHED);
mmu_enable();
add_ns16550_device(-1, OMAP44XX_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat);
return 0;
}
device_initcall(pcm049_mmu_init);
#endif
console_initcall(pcm049_console_init);
static struct device_d hsmmc_dev = {
.id = -1,
.name = "omap-hsmmc",
.map_base = 0x4809C100,
.size = SZ_4K,
};
static int pcm049_mem_init(void)
{
arm_add_mem_device("ram0", 0x80000000, SZ_512M);
static struct device_d smc911x_dev = {
.id = -1,
.name = "smc911x",
.map_base = 0x2C000000,
.size = 0x4000,
};
add_mem_device("sram0", 0x40300000, 48 * 1024,
IORESOURCE_MEM_WRITEABLE);
return 0;
}
mem_initcall(pcm049_mem_init);
static struct gpmc_config net_cfg = {
.cfg = {
@ -136,14 +81,14 @@ static void pcm049_network_init(void)
{
gpmc_cs_config(5, &net_cfg);
register_device(&smc911x_dev);
add_generic_device("smc911x", -1, NULL, 0x2C000000, 0x4000,
IORESOURCE_MEM, NULL);
}
static int pcm049_devices_init(void)
{
register_device(&sdram_dev);
register_device(&sram_dev);
register_device(&hsmmc_dev);
add_generic_device("omap-hsmmc", -1, NULL, 0x4809C100, SZ_4K,
IORESOURCE_MEM, NULL);
gpmc_generic_init(0x10);
@ -160,7 +105,6 @@ static int pcm049_devices_init(void)
dev_add_bb_dev("env_raw", "env0");
#endif
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_PCM049);

61
arch/arm/boards/phycard-i.MX27/pca100.c
View File

@ -41,19 +41,6 @@
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0xa0000000,
.size = 128 * 1024 * 1024,
.platform_data = &ram_pdata,
};
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 1,
@ -66,20 +53,6 @@ struct imx_nand_platform_data nand_info = {
};
#ifdef CONFIG_USB
static struct device_d usbotg_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE,
.size = 0x200,
};
static struct device_d usbh2_dev = {
.id = -1,
.name = "ehci",
.map_base = IMX_OTG_BASE + 0x400,
.size = 0x200,
};
static void pca100_usb_register(void)
{
mdelay(10);
@ -90,29 +63,19 @@ static void pca100_usb_register(void)
mdelay(10);
isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x170), 1);
register_device(&usbotg_dev);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE, NULL);
isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x570), 1);
register_device(&usbh2_dev);
add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
}
#endif
#ifdef CONFIG_MMU
static void pca100_mmu_init(void)
static int pca100_mem_init(void)
{
mmu_init();
arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
mmu_enable();
return 0;
}
#else
static void pca100_mmu_init(void)
{
}
#endif
mem_initcall(pca100_mem_init);
static void pca100_usb_init(void)
{
@ -224,7 +187,6 @@ static int pca100_devices_init(void)
imx_gpio_mode(mode[i]);
imx27_add_nand(&nand_info);
register_device(&sdram_dev);
imx27_add_fec(&fec_info);
imx27_add_mmc0(NULL);
@ -241,7 +203,6 @@ static int pca100_devices_init(void)
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(2149);
@ -250,17 +211,9 @@ static int pca100_devices_init(void)
device_initcall(pca100_devices_init);
static struct device_d pca100_serial_device = {
.id = -1,
.name = "imx_serial",
.map_base = IMX_UART1_BASE,
.size = 4096,
};
static int pca100_console_init(void)
{
pca100_mmu_init();
register_device(&pca100_serial_device);
imx27_add_uart0();
return 0;
}

30
arch/arm/boards/pm9261/init.c
View File

@ -89,20 +89,9 @@ static void pm_add_device_nand(void)
*/
#if defined(CONFIG_DRIVER_NET_DM9000)
static struct dm9000_platform_data dm9000_data = {
.iobase = AT91_CHIPSELECT_2,
.iodata = AT91_CHIPSELECT_2 + 4,
.buswidth = DM9000_WIDTH_16,
.srom = 1,
};
static struct device_d dm9000_dev = {
.id = 0,
.name = "dm9000",
.map_base = AT91_CHIPSELECT_2,
.size = 8,
.platform_data = &dm9000_data,
};
/*
* SMC timings for the DM9000.
* Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
@ -130,25 +119,26 @@ static void __init pm_add_device_dm9000(void)
/* Configure chip-select 2 (DM9000) */
sam9_smc_configure(2, &dm9000_smc_config);
register_device(&dm9000_dev);
add_dm9000_device(0, AT91_CHIPSELECT_2, AT91_CHIPSELECT_2 + 4,
IORESOURCE_MEM_16BIT, &dm9000_data);
}
#else
static void __init ek_add_device_dm9000(void) {}
#endif /* CONFIG_DRIVER_NET_DM9000 */
static struct device_d cfi_dev = {
.id = 0,
.name = "cfi_flash",
.map_base = AT91_CHIPSELECT_0,
.size = 4 * 1024 * 1024,
};
static int pm9261_mem_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
return 0;
}
mem_initcall(pm9261_mem_init);
static int pm9261_devices_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
pm_add_device_nand();
register_device(&cfi_dev);
pm_add_device_dm9000();
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");

18
arch/arm/boards/pm9263/init.c
View File

@ -86,18 +86,19 @@ static void pm_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
}
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = AT91_CHIPSELECT_0,
.size = 4 * 1024 * 1024,
};
static struct at91_ether_platform_data macb_pdata = {
.flags = AT91SAM_ETHER_RMII,
.phy_addr = 0,
};
static int pm9263_mem_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
return 0;
}
mem_initcall(pm9263_mem_init);
static int pm9263_devices_init(void)
{
/*
@ -108,10 +109,9 @@ static int pm9263_devices_init(void)
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
at91_add_device_sdram(64 * 1024 * 1024);
pm_add_device_nand();
at91_add_device_eth(&macb_pdata);
register_device(&cfi_dev);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");

9
arch/arm/boards/pm9g45/init.c
View File

@ -82,9 +82,16 @@ static struct at91_ether_platform_data macb_pdata = {
.phy_addr = 0,
};
static int pm9g45_devices_init(void)
static int pm9g45_mem_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
return 0;
}
mem_initcall(pm9g45_mem_init);
static int pm9g45_devices_init(void)
{
pm_add_device_nand();
at91_add_device_eth(&macb_pdata);

56
arch/arm/boards/scb9328/env/config vendored Normal file
View File

@ -0,0 +1,56 @@
#!/bin/sh
machine=scb9328
eth0.serverip=
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'net', 'nor' or 'nand'
kernel_loc=net
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-$machine.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage_type=zimage
kernelimage=zImage-$machine
#kernelimage_type=uimage
#kernelimage=uImage-$machine
#kernelimage_type=raw
#kernelimage=Image-$machine
#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200"
nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nor=3
nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nand=7
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

58
arch/arm/boards/scb9328/scb9328.c
View File

@ -32,43 +32,12 @@
#include <fcntl.h>
#include <dm9000.h>
#include <led.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = 0x10000000,
.size = 16 * 1024 * 1024,
};
static struct memory_platform_data sdram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = 0x08000000,
.size = 16 * 1024 * 1024,
.platform_data = &sdram_pdata,
};
#include <mach/devices-imx1.h>
static struct dm9000_platform_data dm9000_data = {
.iobase = 0x16000000,
.iodata = 0x16000004,
.buswidth = DM9000_WIDTH_16,
.srom = 1,
};
static struct device_d dm9000_dev = {
.id = -1,
.name = "dm9000",
.map_base = 0x16000000,
.size = 8,
.platform_data = &dm9000_data,
};
struct gpio_led leds[] = {
{
.gpio = 32 + 21,
@ -81,6 +50,14 @@ struct gpio_led leds[] = {
},
};
static int scb9328_mem_init(void)
{
arm_add_mem_device("ram0", 0x08000000, 16 * 1024 * 1024);
return 0;
}
mem_initcall(scb9328_mem_init);
static int scb9328_devices_init(void)
{
int i;
@ -111,15 +88,14 @@ static int scb9328_devices_init(void)
CS5U = 0x00008400;
CS5L = 0x00000D03;
register_device(&cfi_dev);
register_device(&sdram_dev);
register_device(&dm9000_dev);
add_cfi_flash_device(-1, 0x10000000, 16 * 1024 * 1024, 0);
add_dm9000_device(-1, 0x16000000, 0x16000004,
IORESOURCE_MEM_16BIT, &dm9000_data);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x08000100);
armlinux_set_architecture(MACH_TYPE_SCB9328);
@ -128,20 +104,14 @@ static int scb9328_devices_init(void)
device_initcall(scb9328_devices_init);
static struct device_d scb9328_serial_device = {
.id = -1,
.name = "imx_serial",
.map_base = IMX_UART1_BASE,
.size = 4096,
};
static int scb9328_console_init(void)
{
/* init gpios for serial port */
imx_gpio_mode(PC11_PF_UART1_TXD);
imx_gpio_mode(PC12_PF_UART1_RXD);
register_device(&scb9328_serial_device);
imx1_add_uart0();
return 0;
}

27
arch/arm/boards/versatile/versatilepb.c
View File

@ -33,13 +33,6 @@
#include <partition.h>
#include <sizes.h>
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
.map_base = VERSATILE_FLASH_BASE,
.size = VERSATILE_FLASH_SIZE,
};
static int vpb_console_init(void)
{
versatile_register_uart(0);
@ -47,22 +40,22 @@ static int vpb_console_init(void)
}
console_initcall(vpb_console_init);
static struct device_d smc911x_dev = {
.id = -1,
.name = "smc91c111",
.map_base = VERSATILE_ETH_BASE,
.size = 64 * 1024,
};
static int vpb_devices_init(void)
static int vpb_mem_init(void)
{
versatile_add_sdram(64 * 1024 *1024);
register_device(&cfi_dev);
return 0;
}
mem_initcall(vpb_mem_init);
static int vpb_devices_init(void)
{
add_cfi_flash_device(-1, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
register_device(&smc911x_dev);
add_generic_device("smc91c111", -1, NULL, VERSATILE_ETH_BASE, 64 * 1024,
IORESOURCE_MEM, NULL);
armlinux_set_architecture(MACH_TYPE_VERSATILE_PB);
armlinux_set_bootparams((void *)(0x00000100));

6
arch/arm/configs/cupid_defconfig
View File

@ -5,9 +5,11 @@ CONFIG_MACH_GUF_CUPID=y
CONFIG_IMX_CLKO=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x87F00000
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@ -46,9 +48,9 @@ CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_MTD=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
CONFIG_NAND_IMX=y
CONFIG_NAND_IMX_BOOT=y
CONFIG_NAND_IMX_BOOT_2K=y
CONFIG_UBI=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX_IPU=y

9
arch/arm/configs/freescale_mx51_babbage_defconfig
View File

@ -1,17 +1,21 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_INTERNAL_BOOT=y
CONFIG_ARCH_IMX51=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x97f00000
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx51-pdk/env/"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
@ -22,7 +26,6 @@ CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
@ -31,8 +34,10 @@ CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_NET_TFTP_PUSH=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_DRIVER_CFI=y

51
arch/arm/configs/freescale_mx53_loco_defconfig Normal file
View File

@ -0,0 +1,51 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX53=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x7ff00000
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx53-loco/env/"
CONFIG_DEBUG_INFO=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_NET_TFTP_PUSH=y
CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y

9
arch/arm/configs/neso_defconfig
View File

@ -1,11 +1,14 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_ARCH_IMX27=y
CONFIG_MACH_NESO=y
CONFIG_IMX_CLKO=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@ -23,7 +26,6 @@ CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_RESET=y
@ -45,11 +47,11 @@ CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_DRIVER_SPI_MC13783=y
CONFIG_MTD=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
CONFIG_NAND_IMX=y
CONFIG_NAND_IMX_BOOT=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
@ -57,3 +59,4 @@ CONFIG_USB_ISP1504=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
CONFIG_DRIVER_SPI_MC13783=y

6
arch/arm/configs/pca100_defconfig
View File

@ -1,11 +1,14 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_ARCH_IMX27=y
CONFIG_MACH_PCA100=y
CONFIG_IMX_CLKO=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x500000
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@ -43,8 +46,9 @@ CONFIG_NET_USB_ASIX=y
# CONFIG_SPI is not set
CONFIG_MTD=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
CONFIG_NAND_IMX=y
CONFIG_NAND_IMX_BOOT=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI=y

5
arch/arm/configs/pcm037_defconfig
View File

@ -1,9 +1,13 @@
CONFIG_ARCH_IMX=y
CONFIG_CACHE_L2X0=y
CONFIG_ARCH_IMX31=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@ -30,6 +34,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_NET_TFTP_PUSH=y

7
arch/arm/configs/pcm038_defconfig
View File

@ -1,12 +1,15 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_ARCH_IMX27=y
CONFIG_MACH_PCM038=y
CONFIG_IMX_CLKO=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0xa7f00000
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@ -24,7 +27,6 @@ CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_RESET=y
@ -46,8 +48,9 @@ CONFIG_DRIVER_CFI=y
CONFIG_CFI_BUFFER_WRITE=y
CONFIG_MTD=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
CONFIG_NAND_IMX=y
CONFIG_NAND_IMX_BOOT=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI=y

1
arch/arm/configs/pcm043_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_ARCH_IMX35=y
CONFIG_MACH_PCM043=y
CONFIG_IMX_CLKO=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y

4
arch/arm/configs/scb9328_defconfig
View File

@ -2,6 +2,9 @@ CONFIG_ARCH_IMX=y
CONFIG_MACH_SCB9328=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@ -10,7 +13,6 @@ CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/scb9328/env/"
CONFIG_POLLER=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y

2
arch/arm/cpu/Kconfig
View File

@ -87,5 +87,5 @@ config ARCH_HAS_L2X0
config CACHE_L2X0
bool "Enable L2x0 PrimeCell"
depends on ARCH_HAS_L2X0
depends on MMU && ARCH_HAS_L2X0

14
arch/arm/cpu/cpu.c
View File

@ -30,6 +30,7 @@
#include <cache.h>
#include <asm/mmu.h>
#include <asm/system.h>
#include <asm/memory.h>
/**
* Enable processor's instruction cache
@ -89,6 +90,19 @@ void arch_shutdown(void)
#endif
}
LIST_HEAD(memory_list);
void armlinux_add_dram(struct device_d *dev)
{
struct arm_memory *mem = xzalloc(sizeof(*mem));
mem->dev = dev;
mem->start = dev->resource[0].start;
mem->size = dev->resource[0].size;
list_add_tail(&mem->list, &memory_list);
}
/**
* @page arm_boot_preparation Linux Preparation on ARM
*

196
arch/arm/cpu/mmu.c
View File

@ -1,10 +1,13 @@
#include <common.h>
#include <init.h>
#include <asm/mmu.h>
#include <errno.h>
#include <sizes.h>
#include <asm/memory.h>
static unsigned long *ttb;
void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
static void create_section(unsigned long virt, unsigned long phys, int size_m,
unsigned int flags)
{
int i;
@ -23,6 +26,33 @@ void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
);
}
/*
* Do it the simple way for now and invalidate the entire
* tlb
*/
static inline void tlb_invalidate(void)
{
asm volatile (
"mov r0, #0\n"
"mcr p15, 0, r0, c7, c10, 4; @ drain write buffer\n"
"mcr p15, 0, r0, c8, c6, 0; @ invalidate D TLBs\n"
"mcr p15, 0, r0, c8, c5, 0; @ invalidate I TLBs\n"
:
:
: "r0"
);
}
#ifdef CONFIG_CPU_V7
#define PTE_FLAGS_CACHED (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE)
#define PTE_FLAGS_UNCACHED (0)
#else
#define PTE_FLAGS_CACHED (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE)
#define PTE_FLAGS_UNCACHED PTE_SMALL_AP_UNO_SRW
#endif
#define PTE_MASK ((1 << 12) - 1)
/*
* Create a second level translation table for the given virtual address.
* We initially create a flat uncached mapping on it.
@ -37,12 +67,92 @@ static u32 *arm_create_pte(unsigned long virt)
ttb[virt] = (unsigned long)table | PMD_TYPE_TABLE;
for (i = 0; i < 256; i++)
table[i] = virt | PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW;
for (i = 0; i < 256; i++) {
table[i] = virt | PTE_TYPE_SMALL | PTE_FLAGS_UNCACHED;
virt += PAGE_SIZE;
}
return table;
}
static void remap_range(void *_start, size_t size, uint32_t flags)
{
u32 pteentry;
struct arm_memory *mem;
unsigned long start = (unsigned long)_start;
u32 *p;
int numentries, i;
for_each_sdram_bank(mem) {
if (start >= mem->start && start < mem->start + mem->size)
goto found;
}
BUG();
return;
found:
pteentry = (start - mem->start) >> PAGE_SHIFT;
numentries = size >> PAGE_SHIFT;
p = mem->ptes + pteentry;
for (i = 0; i < numentries; i++) {
p[i] &= ~PTE_MASK;
p[i] |= flags | PTE_TYPE_SMALL;
}
dma_flush_range((unsigned long)p,
(unsigned long)p + numentries * sizeof(u32));
tlb_invalidate();
}
/*
* remap the memory bank described by mem cachable and
* bufferable
*/
static int arm_mmu_remap_sdram(struct arm_memory *mem)
{
unsigned long phys = (unsigned long)mem->start;
unsigned long ttb_start = phys >> 20;
unsigned long ttb_end = (phys + mem->size) >> 20;
unsigned long num_ptes = mem->size >> 10;
int i, pte;
debug("remapping SDRAM from 0x%08lx (size 0x%08lx)\n",
phys, mem->size);
/*
* We replace each 1MiB section in this range with second level page
* tables, therefore we must have 1Mib aligment here.
*/
if ((phys & (SZ_1M - 1)) || (mem->size & (SZ_1M - 1)))
return -EINVAL;
mem->ptes = memalign(0x400, num_ptes * sizeof(u32));
debug("ptes: 0x%p ttb_start: 0x%08lx ttb_end: 0x%08lx\n",
mem->ptes, ttb_start, ttb_end);
for (i = 0; i < num_ptes; i++) {
mem->ptes[i] = (phys + i * 4096) | PTE_TYPE_SMALL |
PTE_FLAGS_CACHED;
}
pte = 0;
for (i = ttb_start; i < ttb_end; i++) {
ttb[i] = (unsigned long)(&mem->ptes[pte]) | PMD_TYPE_TABLE |
(0 << 4);
pte += 256;
}
tlb_invalidate();
return 0;
}
/*
* We have 8 exception vectors and the table consists of absolute
* jumps, so we need 8 * 4 bytes for the instructions and another
@ -66,19 +176,21 @@ static void vectors_init(void)
memset(vectors, 0, PAGE_SIZE);
memcpy(vectors, &exception_vectors, ARM_VECTORS_SIZE);
exc[0] = (u32)vectors | PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW;
exc[0] = (u32)vectors | PTE_TYPE_SMALL | PTE_FLAGS_CACHED;
}
/*
* Prepare MMU for usage and create a flat mapping. Board
* code is responsible to remap the SDRAM cached
* Prepare MMU for usage enable it.
*/
void mmu_init(void)
static int mmu_init(void)
{
struct arm_memory *mem;
int i;
ttb = memalign(0x10000, 0x4000);
debug("ttb: 0x%p\n", ttb);
/* Set the ttb register */
asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
@ -86,24 +198,38 @@ void mmu_init(void)
i = 0x3;
asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
/* create a flat mapping */
arm_create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT);
/* create a flat mapping using 1MiB sections */
create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
PMD_TYPE_SECT);
vectors_init();
}
/*
* enable the MMU. Should be called after mmu_init()
*/
void mmu_enable(void)
{
/*
* First remap sdram cached using sections.
* This is to speed up the generation of 2nd level page tables
* below
*/
for_each_sdram_bank(mem)
create_section(mem->start, mem->start, mem->size >> 20,
PMD_SECT_DEF_CACHED);
asm volatile (
"bl __mmu_cache_on;"
:
:
: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
);
/*
* Now that we have the MMU and caches on remap sdram again using
* page tables
*/
for_each_sdram_bank(mem)
arm_mmu_remap_sdram(mem);
return 0;
}
mmu_initcall(mmu_init);
struct outer_cache_fns outer_cache;
@ -125,39 +251,41 @@ void mmu_disable(void)
);
}
/*
* For boards which need coherent memory for DMA. The idea
* is simple: Setup a uncached section containing your SDRAM
* and call setup_dma_coherent() with the offset between the
* cached and the uncached section. dma_alloc_coherent() then
* works using normal malloc but returns the corresponding
* pointer in the uncached area.
*/
static unsigned long dma_coherent_offset;
void setup_dma_coherent(unsigned long offset)
{
dma_coherent_offset = offset;
}
#define PAGE_ALIGN(s) ((s) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
void *dma_alloc_coherent(size_t size)
{
return xmemalign(4096, size) + dma_coherent_offset;
void *ret;
size = PAGE_ALIGN(size);
ret = xmemalign(4096, size);
#ifdef CONFIG_MMU
dma_inv_range((unsigned long)ret, (unsigned long)ret + size);
remap_range(ret, size, PTE_FLAGS_UNCACHED);
#endif
return ret;
}
unsigned long virt_to_phys(void *virt)
{
return (unsigned long)virt - dma_coherent_offset;
return (unsigned long)virt;
}
void *phys_to_virt(unsigned long phys)
{
return (void *)(phys + dma_coherent_offset);
return (void *)phys;
}
void dma_free_coherent(void *mem)
void dma_free_coherent(void *mem, size_t size)
{
free(mem - dma_coherent_offset);
#ifdef CONFIG_MMU
remap_range(mem, size, PTE_FLAGS_CACHED);
#endif
free(mem);
}
void dma_clean_range(unsigned long start, unsigned long end)

10
arch/arm/include/asm/armlinux.h
View File

@ -1,11 +1,12 @@
#ifndef __ARCH_ARMLINUX_H
#define __ARCH_ARMLINUX_H
#include <asm/memory.h>
#if defined CONFIG_CMD_BOOTM || defined CONFIG_CMD_BOOTZ || \
defined CONFIG_CMD_BOOTU
void armlinux_set_bootparams(void *params);
void armlinux_set_architecture(int architecture);
void armlinux_add_dram(struct device_d *dev);
void armlinux_set_revision(unsigned int);
void armlinux_set_serial(u64);
#else
@ -17,10 +18,6 @@ static inline void armlinux_set_architecture(int architecture)
{
}
static inline void armlinux_add_dram(struct device_d *dev)
{
}
static inline void armlinux_set_revision(unsigned int rev)
{
}
@ -34,4 +31,7 @@ struct image_data;
void start_linux(void *adr, int swap, struct image_data *data);
struct device_d *arm_add_mem_device(const char* name, resource_size_t start,
resource_size_t size);
#endif /* __ARCH_ARMLINUX_H */

24
arch/arm/include/asm/memory.h
View File

@ -1,16 +1,18 @@
/*
* linux/include/asm-arm/memory.h
*
* Copyright (C) 2000-2002 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Note: this file should not be included by non-asm/.h files
*/
#ifndef __ASM_ARM_MEMORY_H
#define __ASM_ARM_MEMORY_H
struct arm_memory {
struct list_head list;
struct device_d *dev;
u32 *ptes;
unsigned long start;
unsigned long size;
};
extern struct list_head memory_list;
void armlinux_add_dram(struct device_d *dev);
#define for_each_sdram_bank(mem) list_for_each_entry(mem, &memory_list, list)
#endif /* __ASM_ARM_MEMORY_H */

32
arch/arm/include/asm/mmu.h
View File

@ -3,21 +3,29 @@
#include <asm/pgtable.h>
#include <malloc.h>
#include <errno.h>
#define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT)
#define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED)
void mmu_init(void);
void mmu_enable(void);
void mmu_disable(void);
void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
unsigned int flags);
struct arm_memory;
void setup_dma_coherent(unsigned long offset);
static inline void mmu_enable(void)
{
}
void mmu_disable(void);
static inline void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
unsigned int flags)
{
}
static inline void setup_dma_coherent(unsigned long offset)
{
}
#ifdef CONFIG_MMU
void *dma_alloc_coherent(size_t size);
void dma_free_coherent(void *mem);
void dma_free_coherent(void *mem, size_t size);
void dma_clean_range(unsigned long, unsigned long);
void dma_flush_range(unsigned long, unsigned long);
@ -28,10 +36,10 @@ void *phys_to_virt(unsigned long phys);
#else
static inline void *dma_alloc_coherent(size_t size)
{
return xmalloc(size);
return xmemalign(4096, size);
}
static inline void dma_free_coherent(void *mem)
static inline void dma_free_coherent(void *mem, size_t size)
{
free(mem);
}
@ -60,7 +68,13 @@ static inline void dma_inv_range(unsigned long s, unsigned long e)
#endif
#ifdef CONFIG_CACHE_L2X0
void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
#else
static inline void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
}
#endif
struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);

24
arch/arm/lib/armlinux.c
View File

@ -37,11 +37,11 @@
#include <errno.h>
#include <asm/byteorder.h>
#include <asm/global_data.h>
#include <asm/setup.h>
#include <asm/barebox-arm.h>
#include <asm/armlinux.h>
#include <asm/system.h>
#include <asm/memory.h>
static struct tag *params;
static int armlinux_architecture = 0;
@ -64,23 +64,16 @@ static void setup_start_tag(void)
params = tag_next(params);
}
struct arm_memory {
struct list_head list;
struct device_d *dev;
};
static LIST_HEAD(memory_list);
static void setup_memory_tags(void)
{
struct arm_memory *mem;
list_for_each_entry(mem, &memory_list, list) {
for_each_sdram_bank(mem) {
params->hdr.tag = ATAG_MEM;
params->hdr.size = tag_size(tag_mem32);
params->u.mem.start = mem->dev->map_base;
params->u.mem.size = mem->dev->size;
params->u.mem.start = mem->dev->resource[0].start;
params->u.mem.size = mem->dev->resource[0].size;
params = tag_next(params);
}
@ -196,15 +189,6 @@ void armlinux_set_architecture(int architecture)
armlinux_architecture = architecture;
}
void armlinux_add_dram(struct device_d *dev)
{
struct arm_memory *mem = xzalloc(sizeof(*mem));
mem->dev = dev;
list_add_tail(&mem->list, &memory_list);
}
void armlinux_set_revision(unsigned int rev)
{
system_rev = rev;

1
arch/arm/lib/bootm.c
View File

@ -14,7 +14,6 @@
#include <errno.h>
#include <asm/byteorder.h>
#include <asm/global_data.h>
#include <asm/setup.h>
#include <asm/barebox-arm.h>
#include <asm/armlinux.h>

104
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -20,23 +20,9 @@
#include "generic.h"
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = AT91_CHIPSELECT_1,
.platform_data = &ram_pdata,
};
void at91_add_device_sdram(u32 size)
{
sdram_dev.size = size;
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
}
/* --------------------------------------------------------------------
@ -44,13 +30,6 @@ void at91_add_device_sdram(u32 size)
* -------------------------------------------------------------------- */
#if defined(CONFIG_DRIVER_NET_AT91_ETHER)
static struct device_d at91rm9200_eth_device = {
.id = 0,
.name = "at91_ether",
.map_base = AT91_VA_BASE_EMAC,
.size = 0x1000,
};
void __init at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
@ -79,8 +58,8 @@ void __init at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
}
at91rm9200_eth_device.platform_data = data;
register_device(&at91rm9200_eth_device);
add_generic_device("at91_ether", 0, NULL, AT91_VA_BASE_EMAC, 0x1000,
IORESOURCE_MEM, data);
}
#else
void __init at91_add_device_eth(struct at91_ether_platform_data *data) {}
@ -91,13 +70,6 @@ void __init at91_add_device_eth(struct at91_ether_platform_data *data) {}
* -------------------------------------------------------------------- */
#if defined(CONFIG_NAND_ATMEL)
static struct device_d at91rm9200_nand_device = {
.id = -1,
.name = "atmel_nand",
.map_base = AT91_CHIPSELECT_3,
.size = 0x10,
};
void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned int csa;
@ -132,8 +104,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
at91rm9200_nand_device.platform_data = data;
platform_device_register(&at91rm9200_nand_device);
add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
@ -143,26 +115,12 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) {}
* UART
* -------------------------------------------------------------------- */
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.map_base = (AT91_BASE_SYS + AT91_DBGU),
.size = 4096,
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
}
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.map_base = AT91RM9200_BASE_US0,
.size = 4096,
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
@ -180,13 +138,6 @@ static inline void configure_usart0_pins(unsigned pins)
}
}
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.map_base = AT91RM9200_BASE_US1,
.size = 4096,
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
@ -206,13 +157,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
}
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.map_base = AT91RM9200_BASE_US2,
.size = 4096,
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
@ -224,13 +168,6 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
}
static struct device_d uart3_serial_device = {
.id = 4,
.name = "atmel_serial",
.map_base = AT91RM9200_BASE_US3,
.size = 4096,
};
static inline void configure_usart3_pins(unsigned pins)
{
at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
@ -244,33 +181,46 @@ static inline void configure_usart3_pins(unsigned pins)
void __init at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91RM9200_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
clk_name = "usart0_clk";
start = AT91RM9200_BASE_US0;
id = 1;
break;
case AT91RM9200_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91RM9200_BASE_US1;
id = 2;
break;
case AT91RM9200_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart2_clk";
start = AT91RM9200_BASE_US2;
id = 3;
break;
case AT91RM9200_ID_US3:
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &uart3_serial_device, "usart");
register_device(&uart3_serial_device);
clk_name = "usart3_clk";
start = AT91RM9200_BASE_US3;
id = 4;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}

145
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -21,33 +21,12 @@
#include "generic.h"
static struct memory_platform_data sram_pdata = {
.name = "sram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = AT91_CHIPSELECT_1,
.platform_data = &sram_pdata,
};
void at91_add_device_sdram(u32 size)
{
sdram_dev.size = size;
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
}
#if defined(CONFIG_DRIVER_NET_MACB)
static struct device_d macb_dev = {
.id = -1,
.name = "macb",
.map_base = AT91SAM9260_BASE_EMAC,
.size = 0x1000,
};
void at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
@ -76,21 +55,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
}
macb_dev.platform_data = data;
register_device(&macb_dev);
add_generic_device("macb", 0, NULL, AT91SAM9260_BASE_EMAC, 0x1000,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_eth(struct at91_ether_platform_data *data) {}
#endif
#if defined(CONFIG_NAND_ATMEL)
static struct device_d nand_dev = {
.id = -1,
.name = "atmel_nand",
.map_base = AT91_CHIPSELECT_3,
.size = 0x10,
};
void at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
@ -113,33 +85,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
nand_dev.platform_data = data;
register_device(&nand_dev);
add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.map_base = AT91_BASE_SYS + AT91_DBGU,
.size = 4096,
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
}
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.map_base = AT91SAM9260_BASE_US0,
.size = 4096,
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
@ -159,13 +117,6 @@ static inline void configure_usart0_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
}
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.map_base = AT91SAM9260_BASE_US1,
.size = 4096,
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
@ -177,13 +128,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
}
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.map_base = AT91SAM9260_BASE_US2,
.size = 4096,
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
@ -195,13 +139,6 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
}
static struct device_d uart3_serial_device = {
.id = 4,
.name = "atmel_serial",
.map_base = AT91SAM9260_BASE_US3,
.size = 4096,
};
static inline void configure_usart3_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
@ -213,26 +150,12 @@ static inline void configure_usart3_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PC10, 0); /* CTS3 */
}
static struct device_d uart4_serial_device = {
.id = 5,
.name = "atmel_serial",
.map_base = AT91SAM9260_BASE_US4,
.size = 4096,
};
static inline void configure_usart4_pins(void)
{
at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
}
static struct device_d uart5_serial_device = {
.id = 6,
.name = "atmel_serial",
.map_base = AT91SAM9260_BASE_US5,
.size = 4096,
};
static inline void configure_usart5_pins(void)
{
at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
@ -241,58 +164,68 @@ static inline void configure_usart5_pins(void)
void at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91SAM9260_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
clk_name = "usart0_clk";
start = AT91SAM9260_BASE_US0;
id = 1;
break;
case AT91SAM9260_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91SAM9260_BASE_US1;
id = 2;
break;
case AT91SAM9260_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart2_clk";
start = AT91SAM9260_BASE_US2;
id = 3;
break;
case AT91SAM9260_ID_US3:
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &uart3_serial_device, "usart");
register_device(&uart3_serial_device);
clk_name = "usart3_clk";
start = AT91SAM9260_BASE_US3;
id = 4;
break;
case AT91SAM9260_ID_US4:
configure_usart4_pins();
at91_clock_associate("usart4_clk", &uart4_serial_device, "usart");
register_device(&uart4_serial_device);
clk_name = "usart4_clk";
start = AT91SAM9260_BASE_US4;
id = 5;
break;
case AT91SAM9260_ID_US5:
configure_usart5_pins();
at91_clock_associate("usart5_clk", &uart5_serial_device, "usart");
register_device(&uart5_serial_device);
clk_name = "usart5_clk";
start = AT91SAM9260_BASE_US5;
id = 6;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}
#if defined(CONFIG_MCI_ATMEL)
static struct device_d mci_device = {
.id = -1,
.name = "atmel_mci",
.map_base = AT91SAM9260_BASE_MCI,
.size = SZ_16K,
};
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
struct device_d *dev;
if (!data)
return;
@ -323,9 +256,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA11, 1);
}
mci_device.platform_data = data;
at91_clock_associate("mci_clk", &mci_device, "mci_clk");
register_device(&mci_device);
dev = add_generic_device("atmel_mci", 0, NULL, AT91SAM9260_BASE_MCI, SZ_16K,
IORESOURCE_MEM, data);
at91_clock_associate("mci_clk", dev, "mci_clk");
}
#else
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}

98
arch/arm/mach-at91/at91sam9261_devices.c
View File

@ -21,33 +21,12 @@
#include "generic.h"
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = AT91_CHIPSELECT_1,
.platform_data = &ram_pdata,
};
void at91_add_device_sdram(u32 size)
{
sdram_dev.size = size;
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
}
#if defined(CONFIG_NAND_ATMEL)
static struct device_d nand_dev = {
.id = 0,
.name = "atmel_nand",
.map_base = AT91_CHIPSELECT_3,
.size = 0x10,
};
void at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
@ -73,33 +52,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
nand_dev.platform_data = data;
register_device(&nand_dev);
add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.map_base = (AT91_BASE_SYS + AT91_DBGU),
.size = 4096,
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
}
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.map_base = AT91SAM9261_BASE_US0,
.size = 4096,
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
@ -111,13 +76,6 @@ static inline void configure_usart0_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
}
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.map_base = AT91SAM9261_BASE_US1,
.size = 4096,
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
@ -129,13 +87,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
}
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.map_base = AT91SAM9261_BASE_US2,
.size = 4096,
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
@ -149,43 +100,50 @@ static inline void configure_usart2_pins(unsigned pins)
void at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91SAM9261_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
clk_name = "usart0_clk";
start = AT91SAM9261_BASE_US0;
id = 1;
break;
case AT91SAM9261_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91SAM9261_BASE_US1;
id = 2;
break;
case AT91SAM9261_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart3_clk";
start = AT91SAM9261_BASE_US2;
id = 3;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}
#if defined(CONFIG_MCI_ATMEL)
static struct device_d mci_device = {
.id = -1,
.name = "atmel_mci",
.map_base = AT91SAM9261_BASE_MCI,
.size = SZ_16K,
};
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
struct device_d *dev;
if (!data)
return;
@ -216,9 +174,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_B_periph(AT91_PIN_PA6, 1);
}
mci_device.platform_data = data;
at91_clock_associate("mci_clk", &mci_device, "mci_clk");
register_device(&mci_device);
dev = add_generic_device("atmel_mci", 0, NULL, AT91SAM9261_BASE_MCI, SZ_16K,
IORESOURCE_MEM, data);
at91_clock_associate("mci_clk", dev, "mci_clk");
}
#else
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}

129
arch/arm/mach-at91/at91sam9263_devices.c
View File

@ -21,33 +21,12 @@
#include "generic.h"
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = AT91_CHIPSELECT_1,
.platform_data = &ram_pdata,
};
void at91_add_device_sdram(u32 size)
{
sdram_dev.size = size;
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
}
#if defined(CONFIG_DRIVER_NET_MACB)
static struct device_d macb_dev = {
.id = -1,
.name = "macb",
.map_base = AT91SAM9263_BASE_EMAC,
.size = 0x1000,
};
void at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
@ -75,21 +54,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
}
macb_dev.platform_data = data;
register_device(&macb_dev);
add_generic_device("macb", 0, NULL, AT91SAM9263_BASE_EMAC, 0x1000,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_eth(struct at91_ether_platform_data *data) {}
#endif
#if defined(CONFIG_NAND_ATMEL)
static struct device_d nand_dev = {
.id = -1,
.name = "atmel_nand",
.map_base = AT91_CHIPSELECT_3,
.size = 0x10,
};
void at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
@ -112,33 +84,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
nand_dev.platform_data = data;
register_device(&nand_dev);
add_generic_device("atmel_nand", -1, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.map_base = (AT91_BASE_SYS + AT91_DBGU),
.size = 4096,
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
}
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.map_base = AT91SAM9263_BASE_US0,
.size = 4096,
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
@ -150,13 +108,6 @@ static inline void configure_usart0_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
}
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.map_base = AT91SAM9263_BASE_US1,
.size = 4096,
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
@ -168,13 +119,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
}
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.map_base = AT91SAM9263_BASE_US2,
.size = 4096,
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
@ -188,51 +132,53 @@ static inline void configure_usart2_pins(unsigned pins)
void at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91SAM9263_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
clk_name = "usart0_clk";
start = AT91SAM9263_BASE_US0;
id = 1;
break;
case AT91SAM9263_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91SAM9263_BASE_US1;
id = 2;
break;
case AT91SAM9263_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart2_clk";
start = AT91SAM9263_BASE_US2;
id = 3;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}
#if defined(CONFIG_MCI_ATMEL)
static struct device_d mci0_device = {
.id = 0,
.name = "atmel_mci",
.map_base = AT91SAM9263_BASE_MCI0,
.size = SZ_16K,
};
static struct device_d mci1_device = {
.id = 1,
.name = "atmel_mci",
.map_base = AT91SAM9263_BASE_MCI1,
.size = SZ_16K,
};
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
if (!data)
return;
@ -250,6 +196,8 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_gpio_input(data->wp_pin, 1);
if (mmc_id == 0) { /* MCI0 */
start = AT91SAM9263_BASE_MCI0;
clk_name = "mci0_clk";
/* CLK */
at91_set_A_periph(AT91_PIN_PA12, 0);
@ -263,12 +211,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA4, 1);
at91_set_A_periph(AT91_PIN_PA5, 1);
}
mci0_device.platform_data = data;
at91_clock_associate("mci0_clk", &mci0_device, "mci_clk");
register_device(&mci0_device);
} else { /* MCI1 */
start = AT91SAM9263_BASE_MCI1;
clk_name = "mci1_clk";
/* CLK */
at91_set_A_periph(AT91_PIN_PA6, 0);
@ -282,11 +227,11 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA10, 1);
at91_set_A_periph(AT91_PIN_PA11, 1);
}
mci1_device.platform_data = data;
at91_clock_associate("mci1_clk", &mci1_device, "mci_clk");
register_device(&mci1_device);
}
dev = add_generic_device("atmel_mci", mmc_id, NULL, start, 4096,
IORESOURCE_MEM, data);
at91_clock_associate(clk_name, dev, "mci_clk");
}
#else
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}

141
arch/arm/mach-at91/at91sam9g45_devices.c
View File

@ -21,33 +21,12 @@
#include "generic.h"
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = AT91_CHIPSELECT_6,
.platform_data = &ram_pdata,
};
void at91_add_device_sdram(u32 size)
{
sdram_dev.size = size;
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
arm_add_mem_device("ram0", AT91_CHIPSELECT_6, size);
}
#if defined(CONFIG_DRIVER_NET_MACB)
static struct device_d macb_dev = {
.id = 0,
.name = "macb",
.map_base = AT91SAM9G45_BASE_EMAC,
.size = 0x1000,
};
void at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
@ -76,21 +55,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
}
macb_dev.platform_data = data;
register_device(&macb_dev);
add_generic_device("macb", 0, NULL, AT91SAM9G45_BASE_EMAC, 0x1000,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_eth(struct at91_ether_platform_data *data) {}
#endif
#if defined(CONFIG_NAND_ATMEL)
static struct device_d nand_dev = {
.id = -1,
.name = "atmel_nand",
.map_base = AT91_CHIPSELECT_3,
.size = 0x10,
};
void at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned long csa;
@ -116,33 +88,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
nand_dev.platform_data = data;
register_device(&nand_dev);
add_generic_device("atmel_nand", -1, NULL, AT91_CHIPSELECT_3, 0x10,
IORESOURCE_MEM, data);
}
#else
void at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
static struct device_d dbgu_serial_device = {
.id = -1,
.name = "atmel_serial",
.map_base = (AT91_BASE_SYS + AT91_DBGU),
.size = 4096,
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
}
static struct device_d uart0_serial_device = {
.id = -1,
.name = "atmel_serial",
.map_base = AT91SAM9G45_BASE_US0,
.size = 4096,
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
@ -154,13 +112,6 @@ static inline void configure_usart0_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
}
static struct device_d uart1_serial_device = {
.id = -1,
.name = "atmel_serial",
.map_base = AT91SAM9G45_BASE_US1,
.size = 4096,
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
@ -172,13 +123,6 @@ static inline void configure_usart1_pins(unsigned pins)
at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
}
static struct device_d uart2_serial_device = {
.id = -1,
.name = "atmel_serial",
.map_base = AT91SAM9G45_BASE_US2,
.size = 4096,
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
@ -190,13 +134,6 @@ static inline void configure_usart2_pins(unsigned pins)
at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
}
static struct device_d uart3_serial_device = {
.id = -1,
.name = "atmel_serial",
.map_base = AT91SAM9G45_ID_US3,
.size = 4096,
};
static inline void configure_usart3_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
@ -210,56 +147,59 @@ static inline void configure_usart3_pins(unsigned pins)
void at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
start = AT91_BASE_SYS + AT91_DBGU;
clk_name = "mck";
id = 0;
break;
case AT91SAM9G45_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
clk_name = "usart0_clk";
start = AT91SAM9G45_BASE_US0;
id = 1;
break;
case AT91SAM9G45_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
clk_name = "usart1_clk";
start = AT91SAM9G45_BASE_US1;
id = 2;
break;
case AT91SAM9G45_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
clk_name = "usart2_clk";
start = AT91SAM9G45_BASE_US2;
id = 3;
break;
case AT91SAM9G45_ID_US3:
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &uart2_serial_device, "usart");
register_device(&uart3_serial_device);
clk_name = "usart3_clk";
start = AT91SAM9G45_BASE_US3;
id = 4;
break;
default:
return;
}
dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
at91_clock_associate(clk_name, dev, "usart");
}
#if defined(CONFIG_MCI_ATMEL)
static struct device_d mci0_device = {
.id = 0,
.name = "atmel_mci",
.map_base = AT91SAM9G45_BASE_MCI0,
.size = SZ_16K,
};
static struct device_d mci1_device = {
.id = 1,
.name = "atmel_mci",
.map_base = AT91SAM9G45_BASE_MCI1,
.size = SZ_16K,
};
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
resource_size_t start;
struct device_d *dev;
char* clk_name;
if (!data)
return;
@ -277,6 +217,8 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_gpio_input(data->wp_pin, 1);
if (mmc_id == 0) { /* MCI0 */
start = AT91SAM9G45_BASE_MCI0;
clk_name = "mci0_clk";
/* CLK */
at91_set_A_periph(AT91_PIN_PA0, 0);
@ -296,12 +238,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA9, 1);
}
}
mci0_device.platform_data = data;
at91_clock_associate("mci0_clk", &mci0_device, "mci_clk");
register_device(&mci0_device);
} else { /* MCI1 */
start = AT91SAM9G45_BASE_MCI1;
clk_name = "mci1_clk";
/* CLK */
at91_set_A_periph(AT91_PIN_PA31, 0);
@ -321,11 +260,11 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
at91_set_A_periph(AT91_PIN_PA30, 1);
}
}
mci1_device.platform_data = data;
at91_clock_associate("mci1_clk", &mci1_device, "mci_clk");
register_device(&mci1_device);
}
dev = add_generic_device("atmel_mci", mmc_id, NULL, start, 4096,
IORESOURCE_MEM, data);
at91_clock_associate(clk_name, dev, "mci_clk");
}
#else
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}

60
arch/arm/mach-imx/Kconfig
View File

@ -19,6 +19,7 @@ config ARCH_TEXT_BASE
default 0x08f80000 if MACH_SCB9328
default 0xa7e00000 if MACH_NESO
default 0x97f00000 if MACH_MX51_PDK
default 0x7ff00000 if MACH_MX53_LOCO
default 0x87f00000 if MACH_GUF_CUPID
default 0x93d00000 if MACH_TX25
@ -38,6 +39,7 @@ config BOARDINFO
default "Synertronixx scb9328" if MACH_SCB9328
default "Garz+Fricke Neso" if MACH_NESO
default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK
default "Freescale i.MX53 LOCO" if MACH_FREESCALE_MX53_LOCO
default "Garz+Fricke Cupid" if MACH_GUF_CUPID
default "Ka-Ro tx25" if MACH_TX25
@ -50,8 +52,8 @@ choice
used to setup SDRAM. The internal ROM code then initializes SDRAM
using the register/value table, loads the whole barebox image to
SDRAM and starts it. The internal boot mode is available on newer
i.MX processors (i.MX25, i.MX35 and i.MX51). and supports booting
from NOR, NAND, MMC/SD and serial ROMs.
i.MX processors (i.MX25, i.MX35, i.MX51 and i.MX53). and supports
booting from NOR, NAND, MMC/SD and serial ROMs.
The external boot mode only supports booting from NAND and NOR. With
NOR flash the image is just started in NOR flash. With NAND flash
the NAND controller loads the first 2kbyte from NAND into the NAND
@ -62,7 +64,7 @@ choice
config ARCH_IMX_INTERNAL_BOOT
bool "support internal boot mode"
depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51
depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53
config ARCH_IMX_EXTERNAL_BOOT
bool "support external boot mode"
@ -154,6 +156,11 @@ config ARCH_IMX51
select CPU_V7
select ARCH_HAS_FEC_IMX
config ARCH_IMX53
bool "i.MX53"
select CPU_V7
select ARCH_HAS_FEC_IMX
endchoice
# ----------------------------------------------------------
@ -175,7 +182,6 @@ config MACH_SCB9328
select HAS_DM9000
select HAS_CFI
select MACH_HAS_LOWLEVEL_INIT
select HAVE_MMU
help
Say Y here if you are using the Synertronixx scb9328 board
@ -215,7 +221,6 @@ choice
config MACH_EUKREA_CPUIMX25
bool "Eukrea CPUIMX25"
select MACH_HAS_LOWLEVEL_INIT
select HAVE_MMU
help
Say Y here if you are using the Eukrea Electromatique's CPUIMX25
equipped with a Freescale i.MX25 Processor
@ -233,7 +238,6 @@ config MACH_FREESCALE_MX25_3STACK
config MACH_TX25
bool "Ka-Ro TX25"
select MACH_HAS_LOWLEVEL_INIT
select HAVE_MMU
help
Say Y here if you are using the Ka-Ro tx25 board
@ -252,7 +256,6 @@ choice
config MACH_EUKREA_CPUIMX27
bool "EUKREA CPUIMX27"
select HAS_CFI
select HAVE_MMU
select MACH_HAS_LOWLEVEL_INIT
help
Say Y here if you are using Eukrea's CPUIMX27 equipped
@ -269,7 +272,6 @@ config MACH_IMX27ADS
config MACH_PCA100
bool "phyCard-i.MX27"
select MACH_HAS_LOWLEVEL_INIT
select HAVE_MMU
help
Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
with a Freescale i.MX27 Processor
@ -281,7 +283,6 @@ config MACH_PCM038
select SPI
select DRIVER_SPI_IMX
select DRIVER_SPI_MC13783
select HAVE_MMU
help
Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
with a Freescale i.MX27 Processor
@ -289,7 +290,6 @@ config MACH_PCM038
config MACH_NESO
bool "Garz+Fricke Neso"
select MACH_HAS_LOWLEVEL_INIT
select HAVE_MMU
help
Say Y here if you are using the Garz+Fricke Neso board equipped
with a Freescale i.MX27 Processor
@ -309,7 +309,6 @@ choice
config MACH_PCM037
bool "phyCORE-i.MX31"
select MACH_HAS_LOWLEVEL_INIT
select HAVE_MMU
select USB_ISP1504 if USB
select ARCH_HAS_L2X0
help
@ -330,7 +329,6 @@ choice
config MACH_EUKREA_CPUIMX35
bool "EUKREA CPUIMX35"
select HAVE_MMU
select MACH_HAS_LOWLEVEL_INIT
select ARCH_HAS_L2X0
help
@ -350,21 +348,19 @@ config MACH_FREESCALE_MX35_3STACK
with a Freescale i.MX35 Processor
config MACH_PCM043
bool "phyCORE-i.MX35"
select HAS_CFI
select HAVE_MMU
bool "phyCORE-i.MX35"
select HAS_CFI
select MACH_HAS_LOWLEVEL_INIT
select ARCH_HAS_L2X0
help
Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
with a Freescale i.MX35 Processor
help
Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
with a Freescale i.MX35 Processor
config MACH_GUF_CUPID
bool "Garz+Fricke Cupid"
select HAVE_MMU
bool "Garz+Fricke Cupid"
select MACH_HAS_LOWLEVEL_INIT
select ARCH_HAS_L2X0
help
help
Say Y here if you are using the Garz+Fricke Neso board equipped
with a Freescale i.MX35 Processor
@ -382,12 +378,10 @@ choice
config MACH_FREESCALE_MX51_PDK
bool "Freescale i.MX51 PDK"
select HAVE_MMU
select MACH_HAS_LOWLEVEL_INIT
config MACH_EUKREA_CPUIMX51SD
bool "EUKREA CPUIMX51"
select HAVE_MMU
select MACH_HAS_LOWLEVEL_INIT
help
Say Y here if you are using Eukrea's CPUIMX51 equipped
@ -397,6 +391,24 @@ endchoice
endif
# ----------------------------------------------------------
if ARCH_IMX53
choice
prompt "i.MX53 Board Type"
config MACH_FREESCALE_MX53_LOCO
bool "Freescale i.MX53 LOCO"
select MACH_HAS_LOWLEVEL_INIT
endchoice
endif
# ----------------------------------------------------------
menu "Board specific settings "
if MACH_PCM043
@ -480,7 +492,7 @@ config IMX_CLKO
config IMX_IIM
tristate "IIM fusebox device"
depends on ARCH_IMX25 || ARCH_IMX35
depends on !ARCH_IMX21 && !ARCH_IMX21
help
Device driver for the IC Identification Module (IIM) fusebox. Use the
regular md/mw commands to program and read the fusebox.

1
arch/arm/mach-imx/Makefile
View File

@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o
obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o
obj-$(CONFIG_IMX_CLKO) += clko.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o

16
arch/arm/mach-imx/devices.c
View File

@ -2,20 +2,10 @@
#include <driver.h>
#include <mach/devices.h>
static struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata)
static inline struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata)
{
struct device_d *dev;
dev = xzalloc(sizeof(*dev));
strcpy(dev->name,name);
dev->id = id;
dev->map_base = (unsigned long)base;
dev->size = size;
dev->platform_data = pdata;
register_device(dev);
return 0;
return add_generic_device(name, id, NULL, (resource_size_t)base, size,
IORESOURCE_MEM, pdata);
}
struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata)

137
arch/arm/mach-imx/iim.c
View File

@ -22,6 +22,8 @@
#include <xfuncs.h>
#include <errno.h>
#include <param.h>
#include <fcntl.h>
#include <malloc.h>
#include <asm/io.h>
@ -31,7 +33,15 @@
static unsigned long mac_addr_base;
static int do_fuse_sense(unsigned long reg_base, unsigned int bank,
struct iim_priv {
struct cdev cdev;
void __iomem *base;
void __iomem *bankbase;
int bank;
int banksize;
};
static int do_fuse_sense(void __iomem *reg_base, unsigned int bank,
unsigned int row)
{
u8 err, stat;
@ -73,41 +83,38 @@ static int do_fuse_sense(unsigned long reg_base, unsigned int bank,
return readb(reg_base + IIM_SDAT);
}
static ssize_t imx_iim_read(struct cdev *cdev, void *buf, size_t count,
static ssize_t imx_iim_cdev_read(struct cdev *cdev, void *buf, size_t count,
ulong offset, ulong flags)
{
ulong size, i;
struct device_d *dev = cdev->dev;
struct iim_priv *priv = cdev->priv;
const char *sense_param;
unsigned long explicit_sense = 0;
if (dev == NULL)
return -EINVAL;
if ((sense_param = dev_get_param(dev, "explicit_sense_enable")))
if ((sense_param = dev_get_param(cdev->dev, "explicit_sense_enable")))
explicit_sense = simple_strtoul(sense_param, NULL, 0);
size = min((ulong)count, dev->size - offset);
size = min((ulong)count, priv->banksize - offset);
if (explicit_sense) {
for (i = 0; i < size; i++) {
int row_val;
row_val = do_fuse_sense(dev->parent->map_base,
dev->id, (offset+i)*4);
row_val = do_fuse_sense(priv->base,
priv->bank, (offset + i) * 4);
if (row_val < 0)
return row_val;
((u8 *)buf)[i] = (u8)row_val;
}
} else {
for (i = 0; i < size; i++)
((u8 *)buf)[i] = ((u8 *)dev->map_base)[(offset+i)*4];
((u8 *)buf)[i] = ((u8 *)priv->bankbase)[(offset+i)*4];
}
return size;
}
#ifdef CONFIG_IMX_IIM_FUSE_BLOW
static int do_fuse_blow(unsigned long reg_base, unsigned int bank,
static int do_fuse_blow(void __iomem *reg_base, unsigned int bank,
unsigned int row, u8 value)
{
int bit, ret = 0;
@ -168,28 +175,25 @@ out:
}
#endif /* CONFIG_IMX_IIM_FUSE_BLOW */
static ssize_t imx_iim_write(struct cdev *cdev, const void *buf, size_t count,
static ssize_t imx_iim_cdev_write(struct cdev *cdev, const void *buf, size_t count,
ulong offset, ulong flags)
{
ulong size, i;
struct device_d *dev = cdev->dev;
struct iim_priv *priv = cdev->priv;
const char *write_param;
unsigned int blow_enable = 0;
if (dev == NULL)
return -EINVAL;
if ((write_param = dev_get_param(dev, "permanent_write_enable")))
if ((write_param = dev_get_param(cdev->dev, "permanent_write_enable")))
blow_enable = simple_strtoul(write_param, NULL, 0);
size = min((ulong)count, dev->size - offset);
size = min((ulong)count, priv->banksize - offset);
#ifdef CONFIG_IMX_IIM_FUSE_BLOW
if (blow_enable) {
for (i = 0; i < size; i++) {
int ret;
ret = do_fuse_blow(dev->parent->map_base, dev->id,
(offset+i)*4, ((u8 *)buf)[i]);
ret = do_fuse_blow(priv->base, priv->bank,
(offset + i) * 4, ((u8 *)buf)[i]);
if (ret < 0)
return ret;
}
@ -197,15 +201,15 @@ static ssize_t imx_iim_write(struct cdev *cdev, const void *buf, size_t count,
#endif /* CONFIG_IMX_IIM_FUSE_BLOW */
{
for (i = 0; i < size; i++)
((u8 *)dev->map_base)[(offset+i)*4] = ((u8 *)buf)[i];
((u8 *)priv->bankbase)[(offset+i)*4] = ((u8 *)buf)[i];
}
return size;
}
static struct file_operations imx_iim_ops = {
.read = imx_iim_read,
.write = imx_iim_write,
.read = imx_iim_cdev_read,
.write = imx_iim_cdev_write,
.lseek = dev_lseek_default,
};
@ -224,38 +228,44 @@ static int imx_iim_blow_enable_set(struct device_d *dev, struct param_d *param,
return dev_param_set_generic(dev, param, blow_enable ? "1" : "0");
}
static int imx_iim_add_bank(struct device_d *dev, void __iomem *base, int num)
{
struct iim_priv *priv;
struct cdev *cdev;
priv = xzalloc(sizeof (*priv));
priv->base = base;
priv->bankbase = priv->base + 0x800 + 0x400 * num;
priv->bank = num;
priv->banksize = 32;
cdev = &priv->cdev;
cdev->dev = dev;
cdev->ops = &imx_iim_ops;
cdev->priv = priv;
cdev->size = 32;
cdev->name = asprintf(DRIVERNAME "_bank%d", num);
if (cdev->name == NULL)
return -ENOMEM;
return devfs_create(cdev);
}
static int imx_iim_probe(struct device_d *dev)
{
struct imx_iim_platform_data *pdata = dev->platform_data;
int err;
int i;
void __iomem *base;
base = dev_request_mem_region(dev, 0);
if (pdata)
mac_addr_base = pdata->mac_addr_base;
return 0;
}
static int imx_iim_bank_probe(struct device_d *dev)
{
struct cdev *cdev;
struct device_d *parent;
int err;
cdev = xzalloc(sizeof (struct cdev));
dev->priv = cdev;
cdev->dev = dev;
cdev->ops = &imx_iim_ops;
cdev->size = dev->size;
cdev->name = asprintf(DRIVERNAME "_bank%d", dev->id);
if (cdev->name == NULL)
return -ENOMEM;
parent = get_device_by_name(DRIVERNAME "0");
if (parent == NULL)
return -ENODEV;
err = dev_add_child(parent, dev);
if (err < 0)
return err;
for (i = 0; i < 8; i++) {
imx_iim_add_bank(dev, base, i);
}
#ifdef CONFIG_IMX_IIM_FUSE_BLOW
err = dev_add_param(dev, "permanent_write_enable",
@ -271,11 +281,11 @@ static int imx_iim_bank_probe(struct device_d *dev)
imx_iim_blow_enable_set, NULL, 0);
if (err < 0)
return err;
err = dev_set_param(dev, "explicit_sense_enable", "0");
err = dev_set_param(dev, "explicit_sense_enable", "1");
if (err < 0)
return err;
return devfs_create(cdev);
return 0;
}
static struct driver_d imx_iim_driver = {
@ -283,29 +293,28 @@ static struct driver_d imx_iim_driver = {
.probe = imx_iim_probe,
};
static struct driver_d imx_iim_bank_driver = {
.name = DRIVERNAME "_bank",
.probe = imx_iim_bank_probe,
};
static int imx_iim_init(void)
{
register_driver(&imx_iim_driver);
register_driver(&imx_iim_bank_driver);
return 0;
}
coredevice_initcall(imx_iim_init);
int imx_iim_get_mac(unsigned char *mac)
int imx_iim_read(unsigned int bank, int offset, void *buf, int count)
{
int i;
struct cdev *cdev;
char *name = asprintf(DRIVERNAME "_bank%d", bank);
int ret;
if (mac_addr_base == 0)
return -EINVAL;
cdev = cdev_open(name, O_RDONLY);
if (!cdev)
return -ENODEV;
for (i = 0; i < 6; i++)
mac[i] = readb(mac_addr_base + i*4);
ret = cdev_read(cdev, buf, count, offset, 0);
return 0;
cdev_close(cdev);
free(name);
return ret;
}

39
arch/arm/mach-imx/imx25.c
View File

@ -20,6 +20,7 @@
#include <mach/imx-regs.h>
#include <mach/iim.h>
#include <asm/io.h>
#include <sizes.h>
#include "gpio.h"
@ -53,41 +54,11 @@ static struct imx_iim_platform_data imx25_iim_pdata = {
.mac_addr_base = IIM_MAC_ADDR,
};
static struct device_d imx25_iim_dev = {
.id = -1,
.name = "imx_iim",
.map_base = IMX_IIM_BASE,
.platform_data = &imx25_iim_pdata,
};
static struct device_d imx25_iim_bank0_dev = {
.name = "imx_iim_bank",
.id = 0,
.map_base = IIM_BANK0_BASE,
.size = IIM_BANK_SIZE,
};
static struct device_d imx25_iim_bank1_dev = {
.name = "imx_iim_bank",
.id = 1,
.map_base = IIM_BANK1_BASE,
.size = IIM_BANK_SIZE,
};
static struct device_d imx25_iim_bank2_dev = {
.name = "imx_iim_bank",
.id = 2,
.map_base = IIM_BANK2_BASE,
.size = IIM_BANK_SIZE,
};
static int imx25_iim_init(void)
static int imx25_init(void)
{
register_device(&imx25_iim_dev);
register_device(&imx25_iim_bank0_dev);
register_device(&imx25_iim_bank1_dev);
register_device(&imx25_iim_bank2_dev);
add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
IORESOURCE_MEM, &imx25_iim_pdata);
return 0;
}
coredevice_initcall(imx25_iim_init);
coredevice_initcall(imx25_init);

10
arch/arm/mach-imx/imx27.c
View File

@ -17,6 +17,8 @@
#include <common.h>
#include <mach/imx-regs.h>
#include <sizes.h>
#include <init.h>
#include "gpio.h"
@ -36,3 +38,11 @@ void *imx_gpio_base[] = {
int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
static int imx27_init(void)
{
add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
IORESOURCE_MEM, NULL);
return 0;
}
coredevice_initcall(imx27_init);

11
arch/arm/mach-imx/imx31.c
View File

@ -16,6 +16,9 @@
*/
#include <common.h>
#include <init.h>
#include <sizes.h>
#include <mach/imx-regs.h>
#include "gpio.h"
@ -27,3 +30,11 @@ void *imx_gpio_base[] = {
int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
static int imx31_init(void)
{
add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
IORESOURCE_MEM, NULL);
return 0;
}
coredevice_initcall(imx31_init);

10
arch/arm/mach-imx/imx35.c
View File

@ -16,6 +16,7 @@
*/
#include <common.h>
#include <sizes.h>
#include <init.h>
#include <asm/io.h>
#include <mach/imx-regs.h>
@ -58,3 +59,12 @@ static int imx35_l2_fix(void)
return 0;
}
core_initcall(imx35_l2_fix);
static int imx35_init(void)
{
add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
IORESOURCE_MEM, NULL);
return 0;
}
coredevice_initcall(imx35_init);

10
arch/arm/mach-imx/imx51.c
View File

@ -17,6 +17,7 @@
#include <init.h>
#include <common.h>
#include <sizes.h>
#include <asm/io.h>
#include <mach/imx51-regs.h>
@ -79,3 +80,12 @@ static int imx51_print_silicon_rev(void)
return 0;
}
device_initcall(imx51_print_silicon_rev);
static int imx51_init(void)
{
add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
return 0;
}
coredevice_initcall(imx51_init);

37
arch/sandbox/include/asm/global_data.h → arch/arm/mach-imx/imx53.c
View File

@ -1,10 +1,4 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
@ -21,10 +15,31 @@
* MA 02111-1307 USA
*/
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
typedef struct global_data gd_t;
#include <init.h>
#include <common.h>
#include <asm/io.h>
#include <sizes.h>
#include <mach/imx53-regs.h>
#define DECLARE_GLOBAL_DATA_PTR
#include "gpio.h"
#endif /* __ASM_GBL_DATA_H */
void *imx_gpio_base[] = {
(void *)MX53_GPIO1_BASE_ADDR,
(void *)MX53_GPIO2_BASE_ADDR,
(void *)MX53_GPIO3_BASE_ADDR,
(void *)MX53_GPIO4_BASE_ADDR,
(void *)MX53_GPIO5_BASE_ADDR,
(void *)MX53_GPIO6_BASE_ADDR,
(void *)MX53_GPIO7_BASE_ADDR,
};
int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
static int imx53_init(void)
{
add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
IORESOURCE_MEM, NULL);
return 0;
}
coredevice_initcall(imx53_init);

696
arch/arm/mach-imx/include/mach/clock-imx51.h
View File

@ -1,696 +0,0 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
/* PLL Register Offsets */
#define MX51_PLL_DP_CTL 0x00
#define MX51_PLL_DP_CONFIG 0x04
#define MX51_PLL_DP_OP 0x08
#define MX51_PLL_DP_MFD 0x0C
#define MX51_PLL_DP_MFN 0x10
#define MX51_PLL_DP_MFNMINUS 0x14
#define MX51_PLL_DP_MFNPLUS 0x18
#define MX51_PLL_DP_HFS_OP 0x1C
#define MX51_PLL_DP_HFS_MFD 0x20
#define MX51_PLL_DP_HFS_MFN 0x24
#define MX51_PLL_DP_MFN_TOGC 0x28
#define MX51_PLL_DP_DESTAT 0x2c
/* PLL Register Bit definitions */
#define MX51_PLL_DP_CTL_MUL_CTRL 0x2000
#define MX51_PLL_DP_CTL_DPDCK0_2_EN 0x1000
#define MX51_PLL_DP_CTL_DPDCK0_2_OFFSET 12
#define MX51_PLL_DP_CTL_ADE 0x800
#define MX51_PLL_DP_CTL_REF_CLK_DIV 0x400
#define MX51_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
#define MX51_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
#define MX51_PLL_DP_CTL_HFSM 0x80
#define MX51_PLL_DP_CTL_PRE 0x40
#define MX51_PLL_DP_CTL_UPEN 0x20
#define MX51_PLL_DP_CTL_RST 0x10
#define MX51_PLL_DP_CTL_RCP 0x8
#define MX51_PLL_DP_CTL_PLM 0x4
#define MX51_PLL_DP_CTL_BRM0 0x2
#define MX51_PLL_DP_CTL_LRF 0x1
#define MX51_PLL_DP_CONFIG_BIST 0x8
#define MX51_PLL_DP_CONFIG_SJC_CE 0x4
#define MX51_PLL_DP_CONFIG_AREN 0x2
#define MX51_PLL_DP_CONFIG_LDREQ 0x1
#define MX51_PLL_DP_OP_MFI_OFFSET 4
#define MX51_PLL_DP_OP_MFI_MASK (0xF << 4)
#define MX51_PLL_DP_OP_PDF_OFFSET 0
#define MX51_PLL_DP_OP_PDF_MASK 0xF
#define MX51_PLL_DP_MFD_OFFSET 0
#define MX51_PLL_DP_MFD_MASK 0x07FFFFFF
#define MX51_PLL_DP_MFN_OFFSET 0x0
#define MX51_PLL_DP_MFN_MASK 0x07FFFFFF
#define MX51_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
#define MX51_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
#define MX51_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
#define MX51_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
#define MX51_PLL_DP_DESTAT_TOG_SEL (1 << 31)
#define MX51_PLL_DP_DESTAT_MFN 0x07FFFFFF
/* Assuming 24MHz input clock with doubler ON */
/* MFI PDF */
#define MX51_PLL_DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
#define MX51_PLL_DP_MFD_850 (48 - 1)
#define MX51_PLL_DP_MFN_850 41
#define MX51_PLL_DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
#define MX51_PLL_DP_MFD_800 (3 - 1)
#define MX51_PLL_DP_MFN_800 1
#define MX51_PLL_DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
#define MX51_PLL_DP_MFD_700 (24 - 1)
#define MX51_PLL_DP_MFN_700 7
#define MX51_PLL_DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
#define MX51_PLL_DP_MFD_665 (96 - 1)
#define MX51_PLL_DP_MFN_665 89
#define MX51_PLL_DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
#define MX51_PLL_DP_MFD_532 (24 - 1)
#define MX51_PLL_DP_MFN_532 13
#define MX51_PLL_DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
#define MX51_PLL_DP_MFD_400 (3 - 1)
#define MX51_PLL_DP_MFN_400 1
#define MX51_PLL_DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
#define MX51_PLL_DP_MFD_216 (4 - 1)
#define MX51_PLL_DP_MFN_216 3
/* Register addresses of CCM*/
#define MX51_CCM_CCR 0x00
#define MX51_CCM_CCDR 0x04
#define MX51_CCM_CSR 0x08
#define MX51_CCM_CCSR 0x0C
#define MX51_CCM_CACRR 0x10
#define MX51_CCM_CBCDR 0x14
#define MX51_CCM_CBCMR 0x18
#define MX51_CCM_CSCMR1 0x1C
#define MX51_CCM_CSCMR2 0x20
#define MX51_CCM_CSCDR1 0x24
#define MX51_CCM_CS1CDR 0x28
#define MX51_CCM_CS2CDR 0x2C
#define MX51_CCM_CDCDR 0x30
#define MX51_CCM_CHSCDR 0x34
#define MX51_CCM_CSCDR2 0x38
#define MX51_CCM_CSCDR3 0x3C
#define MX51_CCM_CSCDR4 0x40
#define MX51_CCM_CWDR 0x44
#define MX51_CCM_CDHIPR 0x48
#define MX51_CCM_CDCR 0x4C
#define MX51_CCM_CTOR 0x50
#define MX51_CCM_CLPCR 0x54
#define MX51_CCM_CISR 0x58
#define MX51_CCM_CIMR 0x5C
#define MX51_CCM_CCOSR 0x60
#define MX51_CCM_CGPR 0x64
#define MX51_CCM_CCGR0 0x68
#define MX51_CCM_CCGR1 0x6C
#define MX51_CCM_CCGR2 0x70
#define MX51_CCM_CCGR3 0x74
#define MX51_CCM_CCGR4 0x78
#define MX51_CCM_CCGR5 0x7C
#define MX51_CCM_CCGR6 0x80
#define MX51_CCM_CMEOR 0x84
/* Define the bits in register CCR */
#define MX51_CCM_CCR_COSC_EN (1 << 12)
#define MX51_CCM_CCR_FPM_MULT_MASK (1 << 11)
#define MX51_CCM_CCR_CAMP2_EN (1 << 10)
#define MX51_CCM_CCR_CAMP1_EN (1 << 9)
#define MX51_CCM_CCR_FPM_EN (1 << 8)
#define MX51_CCM_CCR_OSCNT_OFFSET (0)
#define MX51_CCM_CCR_OSCNT_MASK (0xFF)
/* Define the bits in register CCDR */
#define MX51_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
#define MX51_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
#define MX51_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
/* Define the bits in register CSR */
#define MX51_CCM_CSR_COSR_READY (1 << 5)
#define MX51_CCM_CSR_LVS_VALUE (1 << 4)
#define MX51_CCM_CSR_CAMP2_READY (1 << 3)
#define MX51_CCM_CSR_CAMP1_READY (1 << 2)
#define MX51_CCM_CSR_FPM_READY (1 << 1)
#define MX51_CCM_CSR_REF_EN_B (1 << 0)
/* Define the bits in register CCSR */
#define MX51_CCM_CCSR_LP_APM_SEL (0x1 << 9)
#define MX51_CCM_CCSR_STEP_SEL_OFFSET (7)
#define MX51_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
#define MX51_CCM_CCSR_PLL2_PODF_OFFSET (5)
#define MX51_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
#define MX51_CCM_CCSR_PLL3_PODF_OFFSET (3)
#define MX51_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
#define MX51_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
#define MX51_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
#define MX51_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
/* Define the bits in register CACRR */
#define MX51_CCM_CACRR_ARM_PODF_OFFSET (0)
#define MX51_CCM_CACRR_ARM_PODF_MASK (0x7)
/* Define the bits in register CBCDR */
#define MX51_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
#define MX51_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
#define MX51_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
#define MX51_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
#define MX51_CCM_CBCDR_DDR_PODF_OFFSET (27)
#define MX51_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
#define MX51_CCM_CBCDR_EMI_PODF_OFFSET (22)
#define MX51_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
#define MX51_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
#define MX51_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
#define MX51_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
#define MX51_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
#define MX51_CCM_CBCDR_NFC_PODF_OFFSET (13)
#define MX51_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
#define MX51_CCM_CBCDR_AHB_PODF_OFFSET (10)
#define MX51_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
#define MX51_CCM_CBCDR_IPG_PODF_OFFSET (8)
#define MX51_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
#define MX51_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
#define MX51_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
#define MX51_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
#define MX51_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
#define MX51_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
#define MX51_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
/* Define the bits in register CBCMR */
#define MX51_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
#define MX51_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
#define MX51_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
#define MX51_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
#define MX51_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
#define MX51_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
#define MX51_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
#define MX51_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
#define MX51_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
#define MX51_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
#define MX51_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
#define MX51_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
#define MX51_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
#define MX51_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
#define MX51_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
#define MX51_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
/* Define the bits in register CSCMR1 */
#define MX51_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
#define MX51_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
#define MX51_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
#define MX51_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
#define MX51_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
#define MX51_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
#define MX51_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
#define MX51_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
#define MX51_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
#define MX51_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
#define MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
#define MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
#define MX51_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
#define MX51_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
#define MX51_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
#define MX51_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
#define MX51_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
#define MX51_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
#define MX51_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
#define MX51_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
#define MX51_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
#define MX51_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
#define MX51_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
#define MX51_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
#define MX51_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
#define MX51_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
#define MX51_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
#define MX51_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
#define MX51_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
#define MX51_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
#define MX51_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MX51_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
/* Define the bits in register CSCMR2 */
#define MX51_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
#define MX51_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
#define MX51_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
#define MX51_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
#define MX51_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
#define MX51_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
#define MX51_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
#define MX51_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
#define MX51_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
#define MX51_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
#define MX51_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
#define MX51_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
#define MX51_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
#define MX51_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
#define MX51_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
#define MX51_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
#define MX51_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
#define MX51_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
#define MX51_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
#define MX51_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
#define MX51_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
#define MX51_CCM_CSCMR2_SPDIF1_COM (1 << 5)
#define MX51_CCM_CSCMR2_SPDIF0_COM (1 << 4)
#define MX51_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
#define MX51_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
#define MX51_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
#define MX51_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
/* Define the bits in register CSCDR1 */
#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
#define MX51_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
#define MX51_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
#define MX51_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
#define MX51_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
#define MX51_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
#define MX51_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
#define MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
#define MX51_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
#define MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
#define MX51_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
/* Define the bits in register CS1CDR and CS2CDR */
#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
#define MX51_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
#define MX51_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
#define MX51_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
#define MX51_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
#define MX51_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
#define MX51_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
#define MX51_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
#define MX51_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDCDR */
#define MX51_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
#define MX51_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
#define MX51_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
#define MX51_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
#define MX51_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
#define MX51_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
#define MX51_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
#define MX51_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
#define MX51_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
#define MX51_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
#define MX51_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
#define MX51_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
#define MX51_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
#define MX51_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
#define MX51_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
#define MX51_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
/* Define the bits in register CHSCCDR */
#define MX51_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
#define MX51_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
#define MX51_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
#define MX51_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
#define MX51_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
#define MX51_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
#define MX51_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
#define MX51_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
/* Define the bits in register CSCDR2 */
#define MX51_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
#define MX51_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
#define MX51_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
#define MX51_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
#define MX51_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
#define MX51_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
#define MX51_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
#define MX51_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
#define MX51_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
#define MX51_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
#define MX51_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
#define MX51_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
/* Define the bits in register CSCDR3 */
#define MX51_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
#define MX51_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
#define MX51_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
#define MX51_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
#define MX51_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
#define MX51_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
#define MX51_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
#define MX51_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
/* Define the bits in register CSCDR4 */
#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDHIPR */
#define MX51_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
#define MX51_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
#define MX51_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
#define MX51_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
#define MX51_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
#define MX51_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
#define MX51_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
#define MX51_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
#define MX51_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
#define MX51_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
/* Define the bits in register CDCR */
#define MX51_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
#define MX51_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
#define MX51_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
/* Define the bits in register CLPCR */
#define MX51_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
#define MX51_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
#define MX51_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
#define MX51_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
#define MX51_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#define MX51_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
#define MX51_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
#define MX51_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
#define MX51_CCM_CLPCR_STBY_COUNT_OFFSET (9)
#define MX51_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
#define MX51_CCM_CLPCR_VSTBY (0x1 << 8)
#define MX51_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
#define MX51_CCM_CLPCR_SBYOS (0x1 << 6)
#define MX51_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
#define MX51_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
#define MX51_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
#define MX51_CCM_CLPCR_LPM_OFFSET (0)
#define MX51_CCM_CLPCR_LPM_MASK (0x3)
/* Define the bits in register CISR */
#define MX51_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
#define MX51_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MX51_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
#define MX51_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
#define MX51_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
#define MX51_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
#define MX51_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
#define MX51_CCM_CISR_COSC_READY (0x1 << 6)
#define MX51_CCM_CISR_CKIH2_READY (0x1 << 5)
#define MX51_CCM_CISR_CKIH_READY (0x1 << 4)
#define MX51_CCM_CISR_FPM_READY (0x1 << 3)
#define MX51_CCM_CISR_LRF_PLL3 (0x1 << 2)
#define MX51_CCM_CISR_LRF_PLL2 (0x1 << 1)
#define MX51_CCM_CISR_LRF_PLL1 (0x1)
/* Define the bits in register CIMR */
#define MX51_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
#define MX51_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MX51_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
#define MX51_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
#define MX51_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
#define MX51_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
#define MX51_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
#define MX51_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
#define MX51_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
#define MX51_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
#define MX51_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
#define MX51_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
#define MX51_CCM_CIMR_MASK_LRF_PLL1 (0x1)
/* Define the bits in register CCOSR */
#define MX51_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
#define MX51_CCM_CCOSR_CKO2_DIV_OFFSET (21)
#define MX51_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
#define MX51_CCM_CCOSR_CKO2_SEL_OFFSET (16)
#define MX51_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
#define MX51_CCM_CCOSR_CKOL_EN (0x1 << 7)
#define MX51_CCM_CCOSR_CKOL_DIV_OFFSET (4)
#define MX51_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
#define MX51_CCM_CCOSR_CKOL_SEL_OFFSET (0)
#define MX51_CCM_CCOSR_CKOL_SEL_MASK (0xF)
/* Define the bits in registers CGPR */
#define MX51_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
#define MX51_CCM_CGPR_FPM_SEL (0x1 << 3)
#define MX51_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
#define MX51_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
/* Define the bits in registers CCGRx */
#define MX51_CCM_CCGR_CG_MASK 0x3
#define MX51_CCM_CCGR_MOD_OFF 0x0
#define MX51_CCM_CCGR_MOD_ON 0x3
#define MX51_CCM_CCGR_MOD_IDLE 0x1
#define MX51_CCM_CCGR0_CG15_OFFSET 30
#define MX51_CCM_CCGR0_CG15_MASK (0x3 << 30)
#define MX51_CCM_CCGR0_CG14_OFFSET 28
#define MX51_CCM_CCGR0_CG14_MASK (0x3 << 28)
#define MX51_CCM_CCGR0_CG13_OFFSET 26
#define MX51_CCM_CCGR0_CG13_MASK (0x3 << 26)
#define MX51_CCM_CCGR0_CG12_OFFSET 24
#define MX51_CCM_CCGR0_CG12_MASK (0x3 << 24)
#define MX51_CCM_CCGR0_CG11_OFFSET 22
#define MX51_CCM_CCGR0_CG11_MASK (0x3 << 22)
#define MX51_CCM_CCGR0_CG10_OFFSET 20
#define MX51_CCM_CCGR0_CG10_MASK (0x3 << 20)
#define MX51_CCM_CCGR0_CG9_OFFSET 18
#define MX51_CCM_CCGR0_CG9_MASK (0x3 << 18)
#define MX51_CCM_CCGR0_CG8_OFFSET 16
#define MX51_CCM_CCGR0_CG8_MASK (0x3 << 16)
#define MX51_CCM_CCGR0_CG7_OFFSET 14
#define MX51_CCM_CCGR0_CG6_OFFSET 12
#define MX51_CCM_CCGR0_CG5_OFFSET 10
#define MX51_CCM_CCGR0_CG5_MASK (0x3 << 10)
#define MX51_CCM_CCGR0_CG4_OFFSET 8
#define MX51_CCM_CCGR0_CG4_MASK (0x3 << 8)
#define MX51_CCM_CCGR0_CG3_OFFSET 6
#define MX51_CCM_CCGR0_CG3_MASK (0x3 << 6)
#define MX51_CCM_CCGR0_CG2_OFFSET 4
#define MX51_CCM_CCGR0_CG2_MASK (0x3 << 4)
#define MX51_CCM_CCGR0_CG1_OFFSET 2
#define MX51_CCM_CCGR0_CG1_MASK (0x3 << 2)
#define MX51_CCM_CCGR0_CG0_OFFSET 0
#define MX51_CCM_CCGR0_CG0_MASK 0x3
#define MX51_CCM_CCGR1_CG15_OFFSET 30
#define MX51_CCM_CCGR1_CG14_OFFSET 28
#define MX51_CCM_CCGR1_CG13_OFFSET 26
#define MX51_CCM_CCGR1_CG12_OFFSET 24
#define MX51_CCM_CCGR1_CG11_OFFSET 22
#define MX51_CCM_CCGR1_CG10_OFFSET 20
#define MX51_CCM_CCGR1_CG9_OFFSET 18
#define MX51_CCM_CCGR1_CG8_OFFSET 16
#define MX51_CCM_CCGR1_CG7_OFFSET 14
#define MX51_CCM_CCGR1_CG6_OFFSET 12
#define MX51_CCM_CCGR1_CG5_OFFSET 10
#define MX51_CCM_CCGR1_CG4_OFFSET 8
#define MX51_CCM_CCGR1_CG3_OFFSET 6
#define MX51_CCM_CCGR1_CG2_OFFSET 4
#define MX51_CCM_CCGR1_CG1_OFFSET 2
#define MX51_CCM_CCGR1_CG0_OFFSET 0
#define MX51_CCM_CCGR2_CG15_OFFSET 30
#define MX51_CCM_CCGR2_CG14_OFFSET 28
#define MX51_CCM_CCGR2_CG13_OFFSET 26
#define MX51_CCM_CCGR2_CG12_OFFSET 24
#define MX51_CCM_CCGR2_CG11_OFFSET 22
#define MX51_CCM_CCGR2_CG10_OFFSET 20
#define MX51_CCM_CCGR2_CG9_OFFSET 18
#define MX51_CCM_CCGR2_CG8_OFFSET 16
#define MX51_CCM_CCGR2_CG7_OFFSET 14
#define MX51_CCM_CCGR2_CG6_OFFSET 12
#define MX51_CCM_CCGR2_CG5_OFFSET 10
#define MX51_CCM_CCGR2_CG4_OFFSET 8
#define MX51_CCM_CCGR2_CG3_OFFSET 6
#define MX51_CCM_CCGR2_CG2_OFFSET 4
#define MX51_CCM_CCGR2_CG1_OFFSET 2
#define MX51_CCM_CCGR2_CG0_OFFSET 0
#define MX51_CCM_CCGR3_CG15_OFFSET 30
#define MX51_CCM_CCGR3_CG14_OFFSET 28
#define MX51_CCM_CCGR3_CG13_OFFSET 26
#define MX51_CCM_CCGR3_CG12_OFFSET 24
#define MX51_CCM_CCGR3_CG11_OFFSET 22
#define MX51_CCM_CCGR3_CG10_OFFSET 20
#define MX51_CCM_CCGR3_CG9_OFFSET 18
#define MX51_CCM_CCGR3_CG8_OFFSET 16
#define MX51_CCM_CCGR3_CG7_OFFSET 14
#define MX51_CCM_CCGR3_CG6_OFFSET 12
#define MX51_CCM_CCGR3_CG5_OFFSET 10
#define MX51_CCM_CCGR3_CG4_OFFSET 8
#define MX51_CCM_CCGR3_CG3_OFFSET 6
#define MX51_CCM_CCGR3_CG2_OFFSET 4
#define MX51_CCM_CCGR3_CG1_OFFSET 2
#define MX51_CCM_CCGR3_CG0_OFFSET 0
#define MX51_CCM_CCGR4_CG15_OFFSET 30
#define MX51_CCM_CCGR4_CG14_OFFSET 28
#define MX51_CCM_CCGR4_CG13_OFFSET 26
#define MX51_CCM_CCGR4_CG12_OFFSET 24
#define MX51_CCM_CCGR4_CG11_OFFSET 22
#define MX51_CCM_CCGR4_CG10_OFFSET 20
#define MX51_CCM_CCGR4_CG9_OFFSET 18
#define MX51_CCM_CCGR4_CG8_OFFSET 16
#define MX51_CCM_CCGR4_CG7_OFFSET 14
#define MX51_CCM_CCGR4_CG6_OFFSET 12
#define MX51_CCM_CCGR4_CG5_OFFSET 10
#define MX51_CCM_CCGR4_CG4_OFFSET 8
#define MX51_CCM_CCGR4_CG3_OFFSET 6
#define MX51_CCM_CCGR4_CG2_OFFSET 4
#define MX51_CCM_CCGR4_CG1_OFFSET 2
#define MX51_CCM_CCGR4_CG0_OFFSET 0
#define MX51_CCM_CCGR5_CG15_OFFSET 30
#define MX51_CCM_CCGR5_CG14_OFFSET 28
#define MX51_CCM_CCGR5_CG14_MASK (0x3 << 28)
#define MX51_CCM_CCGR5_CG13_OFFSET 26
#define MX51_CCM_CCGR5_CG13_MASK (0x3 << 26)
#define MX51_CCM_CCGR5_CG12_OFFSET 24
#define MX51_CCM_CCGR5_CG12_MASK (0x3 << 24)
#define MX51_CCM_CCGR5_CG11_OFFSET 22
#define MX51_CCM_CCGR5_CG11_MASK (0x3 << 22)
#define MX51_CCM_CCGR5_CG10_OFFSET 20
#define MX51_CCM_CCGR5_CG10_MASK (0x3 << 20)
#define MX51_CCM_CCGR5_CG9_OFFSET 18
#define MX51_CCM_CCGR5_CG9_MASK (0x3 << 18)
#define MX51_CCM_CCGR5_CG8_OFFSET 16
#define MX51_CCM_CCGR5_CG8_MASK (0x3 << 16)
#define MX51_CCM_CCGR5_CG7_OFFSET 14
#define MX51_CCM_CCGR5_CG7_MASK (0x3 << 14)
#define MX51_CCM_CCGR5_CG6_OFFSET 12
#define MX51_CCM_CCGR5_CG5_OFFSET 10
#define MX51_CCM_CCGR5_CG4_OFFSET 8
#define MX51_CCM_CCGR5_CG3_OFFSET 6
#define MX51_CCM_CCGR5_CG2_OFFSET 4
#define MX51_CCM_CCGR5_CG2_MASK (0x3 << 4)
#define MX51_CCM_CCGR5_CG1_OFFSET 2
#define MX51_CCM_CCGR5_CG0_OFFSET 0
#define MX51_CCM_CCGR6_CG7_OFFSET 14
#define MX51_CCM_CCGR6_CG7_MASK (0x3 << 14)
#define MX51_CCM_CCGR6_CG6_OFFSET 12
#define MX51_CCM_CCGR6_CG6_MASK (0x3 << 12)
#define MX51_CCM_CCGR6_CG5_OFFSET 10
#define MX51_CCM_CCGR6_CG5_MASK (0x3 << 10)
#define MX51_CCM_CCGR6_CG4_OFFSET 8
#define MX51_CCM_CCGR6_CG4_MASK (0x3 << 8)
#define MX51_CCM_CCGR6_CG3_OFFSET 6
#define MX51_CCM_CCGR6_CG2_OFFSET 4
#define MX51_CCM_CCGR6_CG1_OFFSET 2
#define MX51_CCM_CCGR6_CG0_OFFSET 0
/* CORTEXA8 platform */
#define MX51_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
#define MX51_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
#define MX51_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
#define MX51_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
#define MX51_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
#define MX51_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
#define MX51_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
#define MX51_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
#define MX51_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
/* DVFS CORE */
#define MX51_DVFSTHRS (MX51_DVFS_CORE_BASE + 0x00)
#define MX51_DVFSCOUN (MX51_DVFS_CORE_BASE + 0x04)
#define MX51_DVFSSIG1 (MX51_DVFS_CORE_BASE + 0x08)
#define MX51_DVFSSIG0 (MX51_DVFS_CORE_BASE + 0x0C)
#define MX51_DVFSGPC0 (MX51_DVFS_CORE_BASE + 0x10)
#define MX51_DVFSGPC1 (MX51_DVFS_CORE_BASE + 0x14)
#define MX51_DVFSGPBT (MX51_DVFS_CORE_BASE + 0x18)
#define MX51_DVFSEMAC (MX51_DVFS_CORE_BASE + 0x1C)
#define MX51_DVFSCNTR (MX51_DVFS_CORE_BASE + 0x20)
#define MX51_DVFSLTR0_0 (MX51_DVFS_CORE_BASE + 0x24)
#define MX51_DVFSLTR0_1 (MX51_DVFS_CORE_BASE + 0x28)
#define MX51_DVFSLTR1_0 (MX51_DVFS_CORE_BASE + 0x2C)
#define MX51_DVFSLTR1_1 (MX51_DVFS_CORE_BASE + 0x30)
#define MX51_DVFSPT0 (MX51_DVFS_CORE_BASE + 0x34)
#define MX51_DVFSPT1 (MX51_DVFS_CORE_BASE + 0x38)
#define MX51_DVFSPT2 (MX51_DVFS_CORE_BASE + 0x3C)
#define MX51_DVFSPT3 (MX51_DVFS_CORE_BASE + 0x40)
/* GPC */
#define MX51_GPC_CNTR (MX51_GPC_BASE + 0x0)
#define MX51_GPC_PGR (MX51_GPC_BASE + 0x4)
#define MX51_GPC_VCR (MX51_GPC_BASE + 0x8)
#define MX51_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
#define MX51_GPC_NEON (MX51_GPC_BASE + 0x10)
#define MX51_GPC_PGR_ARMPG_OFFSET 8
#define MX51_GPC_PGR_ARMPG_MASK (3 << 8)
/* PGC */
#define MX51_PGC_IPU_PGCR (MX51_PGC_IPU_BASE + 0x0)
#define MX51_PGC_IPU_PGSR (MX51_PGC_IPU_BASE + 0xC)
#define MX51_PGC_VPU_PGCR (MX51_PGC_VPU_BASE + 0x0)
#define MX51_PGC_VPU_PGSR (MX51_PGC_VPU_BASE + 0xC)
#define MX51_PGC_GPU_PGCR (MX51_PGC_GPU_BASE + 0x0)
#define MX51_PGC_GPU_PGSR (MX51_PGC_GPU_BASE + 0xC)
#define MX51_PGCR_PCR 1
#define MX51_SRPGCR_PCR 1
#define MX51_EMPGCR_PCR 1
#define MX51_PGSR_PSR 1
#define MX51_CORTEXA8_PLAT_LPC_DSM (1 << 0)
#define MX51_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
/* SRPG */
#define MX51_SRPG_NEON_SRPGCR (MX51_SRPG_NEON_BASE + 0x0)
#define MX51_SRPG_NEON_PUPSCR (MX51_SRPG_NEON_BASE + 0x4)
#define MX51_SRPG_NEON_PDNSCR (MX51_SRPG_NEON_BASE + 0x8)
#define MX51_SRPG_ARM_SRPGCR (MX51_SRPG_ARM_BASE + 0x0)
#define MX51_SRPG_ARM_PUPSCR (MX51_SRPG_ARM_BASE + 0x4)
#define MX51_SRPG_ARM_PDNSCR (MX51_SRPG_ARM_BASE + 0x8)
#define MX51_SRPG_EMPGC0_SRPGCR (MX51_SRPG_EMPGC0_BASE + 0x0)
#define MX51_SRPG_EMPGC0_PUPSCR (MX51_SRPG_EMPGC0_BASE + 0x4)
#define MX51_SRPG_EMPGC0_PDNSCR (MX51_SRPG_EMPGC0_BASE + 0x8)
#define MX51_SRPG_EMPGC1_SRPGCR (MX51_SRPG_EMPGC1_BASE + 0x0)
#define MX51_SRPG_EMPGC1_PUPSCR (MX51_SRPG_EMPGC1_BASE + 0x4)
#define MX51_SRPG_EMPGC1_PDNSCR (MX51_SRPG_EMPGC1_BASE + 0x8)
#define MX51_SRPG_MEGAMIX_SRPGCR (MX51_SRPG_MEGAMIX_BASE + 0x0)
#define MX51_SRPG_MEGAMIX_PUPSCR (MX51_SRPG_MEGAMIX_BASE + 0x4)
#define MX51_SRPG_MEGAMIX_PDNSCR (MX51_SRPG_MEGAMIX_BASE + 0x8)
#define MX51_SRPGC_EMI_SRPGCR (MX51_SRPGC_EMI_BASE + 0x0)
#define MX51_SRPGC_EMI_PUPSCR (MX51_SRPGC_EMI_BASE + 0x4)
#define MX51_SRPGC_EMI_PDNSCR (MX51_SRPGC_EMI_BASE + 0x8)
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */

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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
/* PLL Register Offsets */
#define MX5_PLL_DP_CTL 0x00
#define MX5_PLL_DP_CONFIG 0x04
#define MX5_PLL_DP_OP 0x08
#define MX5_PLL_DP_MFD 0x0C
#define MX5_PLL_DP_MFN 0x10
#define MX5_PLL_DP_MFNMINUS 0x14
#define MX5_PLL_DP_MFNPLUS 0x18
#define MX5_PLL_DP_HFS_OP 0x1C
#define MX5_PLL_DP_HFS_MFD 0x20
#define MX5_PLL_DP_HFS_MFN 0x24
#define MX5_PLL_DP_MFN_TOGC 0x28
#define MX5_PLL_DP_DESTAT 0x2c
/* PLL Register Bit definitions */
#define MX5_PLL_DP_CTL_MUL_CTRL 0x2000
#define MX5_PLL_DP_CTL_DPDCK0_2_EN 0x1000
#define MX5_PLL_DP_CTL_DPDCK0_2_OFFSET 12
#define MX5_PLL_DP_CTL_ADE 0x800
#define MX5_PLL_DP_CTL_REF_CLK_DIV 0x400
#define MX5_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
#define MX5_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
#define MX5_PLL_DP_CTL_HFSM 0x80
#define MX5_PLL_DP_CTL_PRE 0x40
#define MX5_PLL_DP_CTL_UPEN 0x20
#define MX5_PLL_DP_CTL_RST 0x10
#define MX5_PLL_DP_CTL_RCP 0x8
#define MX5_PLL_DP_CTL_PLM 0x4
#define MX5_PLL_DP_CTL_BRM0 0x2
#define MX5_PLL_DP_CTL_LRF 0x1
#define MX5_PLL_DP_CONFIG_BIST 0x8
#define MX5_PLL_DP_CONFIG_SJC_CE 0x4
#define MX5_PLL_DP_CONFIG_AREN 0x2
#define MX5_PLL_DP_CONFIG_LDREQ 0x1
#define MX5_PLL_DP_OP_MFI_OFFSET 4
#define MX5_PLL_DP_OP_MFI_MASK (0xF << 4)
#define MX5_PLL_DP_OP_PDF_OFFSET 0
#define MX5_PLL_DP_OP_PDF_MASK 0xF
#define MX5_PLL_DP_MFD_OFFSET 0
#define MX5_PLL_DP_MFD_MASK 0x07FFFFFF
#define MX5_PLL_DP_MFN_OFFSET 0x0
#define MX5_PLL_DP_MFN_MASK 0x07FFFFFF
#define MX5_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
#define MX5_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
#define MX5_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
#define MX5_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
#define MX5_PLL_DxP_DESTAT_TOG_SEL (1 << 31)
#define MX5_PLL_DP_DESTAT_MFN 0x07FFFFFF
/* Register addresses of CCM */
#define MX5_CCM_CCR 0x00
#define MX5_CCM_CCDR 0x04
#define MX5_CCM_CSR 0x08
#define MX5_CCM_CCSR 0x0C
#define MX5_CCM_CACRR 0x10
#define MX5_CCM_CBCDR 0x14
#define MX5_CCM_CBCMR 0x18
#define MX5_CCM_CSCMR1 0x1C
#define MX5_CCM_CSCMR2 0x20
#define MX5_CCM_CSCDR1 0x24
#define MX5_CCM_CS1CDR 0x28
#define MX5_CCM_CS2CDR 0x2C
#define MX5_CCM_CDCDR 0x30
#define MX5_CCM_CHSCDR 0x34
#define MX5_CCM_CSCDR2 0x38
#define MX5_CCM_CSCDR3 0x3C
#define MX5_CCM_CSCDR4 0x40
#define MX5_CCM_CWDR 0x44
#define MX5_CCM_CDHIPR 0x48
#define MX5_CCM_CDCR 0x4C
#define MX5_CCM_CTOR 0x50
#define MX5_CCM_CLPCR 0x54
#define MX5_CCM_CISR 0x58
#define MX5_CCM_CIMR 0x5C
#define MX5_CCM_CCOSR 0x60
#define MX5_CCM_CGPR 0x64
#define MX5_CCM_CCGR0 0x68
#define MX5_CCM_CCGR1 0x6C
#define MX5_CCM_CCGR2 0x70
#define MX5_CCM_CCGR3 0x74
#define MX5_CCM_CCGR4 0x78
#define MX5_CCM_CCGR5 0x7C
#define MX5_CCM_CCGR6 0x80
#define MX5_CCM_CMEOR 0x84
/* Define the bits in register CCR */
#define MX5_CCM_CCR_COSC_EN (1 << 12)
#define MX5_CCM_CCR_FPM_MULT_MASK (1 << 11)
#define MX5_CCM_CCR_CAMP2_EN (1 << 10)
#define MX5_CCM_CCR_CAMP1_EN (1 << 9)
#define MX5_CCM_CCR_FPM_EN (1 << 8)
#define MX5_CCM_CCR_OSCNT_OFFSET (0)
#define MX5_CCM_CCR_OSCNT_MASK (0xFF)
/* Define the bits in register CCDR */
#define MX5_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
#define MX5_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
#define MX5_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
/* Define the bits in register CSR */
#define MX5_CCM_CSR_COSR_READY (1 << 5)
#define MX5_CCM_CSR_LVS_VALUE (1 << 4)
#define MX5_CCM_CSR_CAMP2_READY (1 << 3)
#define MX5_CCM_CSR_CAMP1_READY (1 << 2)
#define MX5_CCM_CSR_FPM_READY (1 << 1)
#define MX5_CCM_CSR_REF_EN_B (1 << 0)
/* Define the bits in register CCSR */
#define MX5_CCM_CCSR_LP_APM_SEL (0x1 << 9)
#define MX5_CCM_CCSR_STEP_SEL_OFFSET (7)
#define MX5_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
#define MX5_CCM_CCSR_STEP_SEL_LP_APM 0
#define MX5_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
#define MX5_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
#define MX5_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
#define MX5_CCM_CCSR_PLL2_PODF_OFFSET (5)
#define MX5_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
#define MX5_CCM_CCSR_PLL3_PODF_OFFSET (3)
#define MX5_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
#define MX5_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
1: step_clk */
#define MX5_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
#define MX5_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
/* Define the bits in register CACRR */
#define MX5_CCM_CACRR_ARM_PODF_OFFSET (0)
#define MX5_CCM_CACRR_ARM_PODF_MASK (0x7)
/* Define the bits in register CBCDR */
#define MX5_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
#define MX5_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
#define MX5_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
#define MX5_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
#define MX5_CCM_CBCDR_DDR_PODF_OFFSET (27)
#define MX5_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
#define MX5_CCM_CBCDR_EMI_PODF_OFFSET (22)
#define MX5_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
#define MX5_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
#define MX5_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
#define MX5_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
#define MX5_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
#define MX5_CCM_CBCDR_NFC_PODF_OFFSET (13)
#define MX5_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
#define MX5_CCM_CBCDR_AHB_PODF_OFFSET (10)
#define MX5_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
#define MX5_CCM_CBCDR_IPG_PODF_OFFSET (8)
#define MX5_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
#define MX5_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
#define MX5_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
#define MX5_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
#define MX5_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
#define MX5_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
#define MX5_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
/* Define the bits in register CBCMR */
#define MX5_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
#define MX5_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
#define MX5_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
#define MX5_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
#define MX5_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
#define MX5_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
#define MX5_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
#define MX5_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
#define MX5_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
#define MX5_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
#define MX5_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
#define MX5_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
#define MX5_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
#define MX5_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
#define MX5_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
#define MX5_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
/* Define the bits in register CSCMR1 */
#define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
#define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
#define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
#define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
#define MX5_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
#define MX5_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
#define MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
#define MX5_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
#define MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
#define MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
#define MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
#define MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
#define MX5_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
#define MX5_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
#define MX5_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
#define MX5_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
#define MX5_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
#define MX5_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
#define MX5_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
#define MX5_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
#define MX5_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
#define MX5_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
#define MX5_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
#define MX5_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
#define MX5_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
#define MX5_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
#define MX5_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
#define MX5_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
#define MX5_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
#define MX5_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
#define MX5_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MX5_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
/* Define the bits in register CSCMR2 */
#define MX5_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
#define MX5_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
#define MX5_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
#define MX5_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
#define MX5_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
#define MX5_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
#define MX5_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
#define MX5_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
#define MX5_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
#define MX5_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
#define MX5_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
#define MX5_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
#define MX5_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
#define MX5_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
#define MX5_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
#define MX5_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
#define MX5_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
#define MX5_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
#define MX5_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
#define MX5_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
#define MX5_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
#define MX5_CCM_CSCMR2_SPDIF1_COM (1 << 5)
#define MX5_CCM_CSCMR2_SPDIF0_COM (1 << 4)
#define MX5_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
#define MX5_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
#define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
#define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
/* Define the bits in register CSCDR1 */
#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
#define MX5_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
#define MX5_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
#define MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
#define MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
#define MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
#define MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
#define MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
#define MX5_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
#define MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
#define MX5_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
/* Define the bits in register CS1CDR and CS2CDR */
#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
#define MX5_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
#define MX5_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
#define MX5_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
#define MX5_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
#define MX5_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
#define MX5_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
#define MX5_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
#define MX5_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDCDR */
#define MX5_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
#define MX5_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
#define MX5_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
#define MX5_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
#define MX5_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
#define MX5_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
#define MX5_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
#define MX5_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
#define MX5_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
#define MX5_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
#define MX5_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
#define MX5_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
#define MX5_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
#define MX5_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
#define MX5_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
#define MX5_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
/* Define the bits in register CHSCCDR */
#define MX5_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
#define MX5_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
#define MX5_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
#define MX5_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
#define MX5_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
#define MX5_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
#define MX5_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
#define MX5_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
/* Define the bits in register CSCDR2 */
#define MX5_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
#define MX5_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
#define MX5_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
#define MX5_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
#define MX5_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
#define MX5_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
#define MX5_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
#define MX5_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
#define MX5_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
#define MX5_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
#define MX5_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
#define MX5_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
/* Define the bits in register CSCDR3 */
#define MX5_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
#define MX5_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
#define MX5_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
#define MX5_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
#define MX5_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
#define MX5_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
#define MX5_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
#define MX5_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
/* Define the bits in register CSCDR4 */
#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDHIPR */
#define MX5_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
#define MX5_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
#define MX5_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
#define MX5_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
#define MX5_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
#define MX5_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
#define MX5_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
#define MX5_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
#define MX5_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
#define MX5_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
/* Define the bits in register CDCR */
#define MX5_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
#define MX5_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
#define MX5_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
/* Define the bits in register CLPCR */
#define MX5_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
#define MX5_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
#define MX5_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
#define MX5_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
#define MX5_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#define MX5_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
#define MX5_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
#define MX5_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
#define MX5_CCM_CLPCR_STBY_COUNT_OFFSET (9)
#define MX5_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
#define MX5_CCM_CLPCR_VSTBY (0x1 << 8)
#define MX5_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
#define MX5_CCM_CLPCR_SBYOS (0x1 << 6)
#define MX5_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
#define MX5_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
#define MX5_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
#define MX5_CCM_CLPCR_LPM_OFFSET (0)
#define MX5_CCM_CLPCR_LPM_MASK (0x3)
/* Define the bits in register CISR */
#define MX5_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
#define MX5_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MX5_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
#define MX5_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
#define MX5_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
#define MX5_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
#define MX5_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
#define MX5_CCM_CISR_COSC_READY (0x1 << 6)
#define MX5_CCM_CISR_CKIH2_READY (0x1 << 5)
#define MX5_CCM_CISR_CKIH_READY (0x1 << 4)
#define MX5_CCM_CISR_FPM_READY (0x1 << 3)
#define MX5_CCM_CISR_LRF_PLL3 (0x1 << 2)
#define MX5_CCM_CISR_LRF_PLL2 (0x1 << 1)
#define MX5_CCM_CISR_LRF_PLL1 (0x1)
/* Define the bits in register CIMR */
#define MX5_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
#define MX5_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MX5_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
#define MX5_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
#define MX5_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
#define MX5_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
#define MX5_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
#define MX5_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
#define MX5_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
#define MX5_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
#define MX5_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
#define MX5_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
#define MX5_CCM_CIMR_MASK_LRF_PLL1 (0x1)
/* Define the bits in register CCOSR */
#define MX5_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
#define MX5_CCM_CCOSR_CKO2_DIV_OFFSET (21)
#define MX5_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
#define MX5_CCM_CCOSR_CKO2_SEL_OFFSET (16)
#define MX5_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
#define MX5_CCM_CCOSR_CKOL_EN (0x1 << 7)
#define MX5_CCM_CCOSR_CKOL_DIV_OFFSET (4)
#define MX5_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
#define MX5_CCM_CCOSR_CKOL_SEL_OFFSET (0)
#define MX5_CCM_CCOSR_CKOL_SEL_MASK (0xF)
/* Define the bits in registers CGPR */
#define MX5_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
#define MX5_CCM_CGPR_FPM_SEL (0x1 << 3)
#define MX5_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
#define MX5_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
/* Define the bits in registers CCGRx */
#define MX5_CCM_CCGRx_CG_MASK 0x3
#define MX5_CCM_CCGRx_MOD_OFF 0x0
#define MX5_CCM_CCGRx_MOD_ON 0x3
#define MX5_CCM_CCGRx_MOD_IDLE 0x1
#define MX5_CCM_CCGRx_CG15_MASK (0x3 << 30)
#define MX5_CCM_CCGRx_CG14_MASK (0x3 << 28)
#define MX5_CCM_CCGRx_CG13_MASK (0x3 << 26)
#define MX5_CCM_CCGRx_CG12_MASK (0x3 << 24)
#define MX5_CCM_CCGRx_CG11_MASK (0x3 << 22)
#define MX5_CCM_CCGRx_CG10_MASK (0x3 << 20)
#define MX5_CCM_CCGRx_CG9_MASK (0x3 << 18)
#define MX5_CCM_CCGRx_CG8_MASK (0x3 << 16)
#define MX5_CCM_CCGRx_CG5_MASK (0x3 << 10)
#define MX5_CCM_CCGRx_CG4_MASK (0x3 << 8)
#define MX5_CCM_CCGRx_CG3_MASK (0x3 << 6)
#define MX5_CCM_CCGRx_CG2_MASK (0x3 << 4)
#define MX5_CCM_CCGRx_CG1_MASK (0x3 << 2)
#define MX5_CCM_CCGRx_CG0_MASK (0x3 << 0)
#define MX5_CCM_CCGRx_CG15_OFFSET 30
#define MX5_CCM_CCGRx_CG14_OFFSET 28
#define MX5_CCM_CCGRx_CG13_OFFSET 26
#define MX5_CCM_CCGRx_CG12_OFFSET 24
#define MX5_CCM_CCGRx_CG11_OFFSET 22
#define MX5_CCM_CCGRx_CG10_OFFSET 20
#define MX5_CCM_CCGRx_CG9_OFFSET 18
#define MX5_CCM_CCGRx_CG8_OFFSET 16
#define MX5_CCM_CCGRx_CG7_OFFSET 14
#define MX5_CCM_CCGRx_CG6_OFFSET 12
#define MX5_CCM_CCGRx_CG5_OFFSET 10
#define MX5_CCM_CCGRx_CG4_OFFSET 8
#define MX5_CCM_CCGRx_CG3_OFFSET 6
#define MX5_CCM_CCGRx_CG2_OFFSET 4
#define MX5_CCM_CCGRx_CG1_OFFSET 2
#define MX5_CCM_CCGRx_CG0_OFFSET 0
#define MX5_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
#define MX5_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
#define MX5_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
#define MX5_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
#define MX5_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
#define MX5_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
#define MX5_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
#define MX5_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
#define MX5_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
#define MX5_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
#define MX5_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
#define MX5_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
#define MX5_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
/* CORTEXA8 platform */
#define MX5_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
#define MX5_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
#define MX5_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
#define MX5_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
#define MX5_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
#define MX5_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
#define MX5_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
#define MX5_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
#define MX5_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
/* DVFS CORE */
#define MX5_DVFSTHRS (MX5_DVFS_CORE_BASE + 0x00)
#define MX5_DVFSCOUN (MX5_DVFS_CORE_BASE + 0x04)
#define MX5_DVFSSIG1 (MX5_DVFS_CORE_BASE + 0x08)
#define MX5_DVFSSIG0 (MX5_DVFS_CORE_BASE + 0x0C)
#define MX5_DVFSGPC0 (MX5_DVFS_CORE_BASE + 0x10)
#define MX5_DVFSGPC1 (MX5_DVFS_CORE_BASE + 0x14)
#define MX5_DVFSGPBT (MX5_DVFS_CORE_BASE + 0x18)
#define MX5_DVFSEMAC (MX5_DVFS_CORE_BASE + 0x1C)
#define MX5_DVFSCNTR (MX5_DVFS_CORE_BASE + 0x20)
#define MX5_DVFSLTR0_0 (MX5_DVFS_CORE_BASE + 0x24)
#define MX5_DVFSLTR0_1 (MX5_DVFS_CORE_BASE + 0x28)
#define MX5_DVFSLTR1_0 (MX5_DVFS_CORE_BASE + 0x2C)
#define MX5_DVFSLTR1_1 (MX5_DVFS_CORE_BASE + 0x30)
#define MX5_DVFSPT0 (MX5_DVFS_CORE_BASE + 0x34)
#define MX5_DVFSPT1 (MX5_DVFS_CORE_BASE + 0x38)
#define MX5_DVFSPT2 (MX5_DVFS_CORE_BASE + 0x3C)
#define MX5_DVFSPT3 (MX5_DVFS_CORE_BASE + 0x40)
/* GPC */
#define MX5_GPC_CNTR (MX51_GPC_BASE + 0x0)
#define MX5_GPC_PGR (MX51_GPC_BASE + 0x4)
#define MX5_GPC_VCR (MX51_GPC_BASE + 0x8)
#define MX5_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
#define MX5_GPC_NEON (MX51_GPC_BASE + 0x10)
#define MX5_GPC_PGR_ARMPG_OFFSET 8
#define MX5_GPC_PGR_ARMPG_MASK (3 << 8)
/* PGC */
#define MX5_PGC_IPU_PGCR (MX5_PGC_IPU_BASE + 0x0)
#define MX5_PGC_IPU_PGSR (MX5_PGC_IPU_BASE + 0xC)
#define MX5_PGC_VPU_PGCR (MX5_PGC_VPU_BASE + 0x0)
#define MX5_PGC_VPU_PGSR (MX5_PGC_VPU_BASE + 0xC)
#define MX5_PGC_GPU_PGCR (MX5_PGC_GPU_BASE + 0x0)
#define MX5_PGC_GPU_PGSR (MX5_PGC_GPU_BASE + 0xC)
#define MX5_PGCR_PCR 1
#define MX5_SRPGCR_PCR 1
#define MX5_EMPGCR_PCR 1
#define MX5_PGSR_PSR 1
#define MX5_CORTEXA8_PLAT_LPC_DSM (1 << 0)
#define MX5_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
/* SRPG */
#define MX5_SRPG_NEON_SRPGCR (MX5_SRPG_NEON_BASE + 0x0)
#define MX5_SRPG_NEON_PUPSCR (MX5_SRPG_NEON_BASE + 0x4)
#define MX5_SRPG_NEON_PDNSCR (MX5_SRPG_NEON_BASE + 0x8)
#define MX5_SRPG_ARM_SRPGCR (MX5_SRPG_ARM_BASE + 0x0)
#define MX5_SRPG_ARM_PUPSCR (MX5_SRPG_ARM_BASE + 0x4)
#define MX5_SRPG_ARM_PDNSCR (MX5_SRPG_ARM_BASE + 0x8)
#define MX5_SRPG_EMPGC0_SRPGCR (MX5_SRPG_EMPGC0_BASE + 0x0)
#define MX5_SRPG_EMPGC0_PUPSCR (MX5_SRPG_EMPGC0_BASE + 0x4)
#define MX5_SRPG_EMPGC0_PDNSCR (MX5_SRPG_EMPGC0_BASE + 0x8)
#define MX5_SRPG_EMPGC1_SRPGCR (MX5_SRPG_EMPGC1_BASE + 0x0)
#define MX5_SRPG_EMPGC1_PUPSCR (MX5_SRPG_EMPGC1_BASE + 0x4)
#define MX5_SRPG_EMPGC1_PDNSCR (MX5_SRPG_EMPGC1_BASE + 0x8)
#define MX5_SRPG_MEGAMIX_SRPGCR (MX5_SRPG_MEGAMIX_BASE + 0x0)
#define MX5_SRPG_MEGAMIX_PUPSCR (MX5_SRPG_MEGAMIX_BASE + 0x4)
#define MX5_SRPG_MEGAMIX_PDNSCR (MX5_SRPG_MEGAMIX_BASE + 0x8)
#define MX5_SRPGC_EMI_SRPGCR (MX5_SRPGC_EMI_BASE + 0x0)
#define MX5_SRPGC_EMI_PUPSCR (MX5_SRPGC_EMI_BASE + 0x4)
#define MX5_SRPGC_EMI_PDNSCR (MX5_SRPGC_EMI_BASE + 0x8)
/* Assuming 24MHz input clock with doubler ON */
/* MFI PDF */
#define MX5_PLL_DP_OP_1000 ((10 << 4) + ((1 - 1) << 0))
#define MX5_PLL_DP_MFD_1000 (12 - 1)
#define MX5_PLL_DP_MFN_1000 5
#define MX5_PLL_DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
#define MX5_PLL_DP_MFD_850 (48 - 1)
#define MX5_PLL_DP_MFN_850 41
#define MX5_PLL_DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
#define MX5_PLL_DP_MFD_800 (3 - 1)
#define MX5_PLL_DP_MFN_800 1
#define MX5_PLL_DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
#define MX5_PLL_DP_MFD_700 (24 - 1)
#define MX5_PLL_DP_MFN_700 7
#define MX5_PLL_DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
#define MX5_PLL_DP_MFD_665 (96 - 1)
#define MX5_PLL_DP_MFN_665 89
#define MX5_PLL_DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
#define MX5_PLL_DP_MFD_532 (24 - 1)
#define MX5_PLL_DP_MFN_532 13
#define MX5_PLL_DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
#define MX5_PLL_DP_MFD_400 (3 - 1)
#define MX5_PLL_DP_MFN_400 1
#define MX5_PLL_DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
#define MX5_PLL_DP_MFD_216 (4 - 1)
#define MX5_PLL_DP_MFN_216 3
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */

11
arch/arm/mach-imx/include/mach/devices-imx1.h Normal file
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@ -0,0 +1,11 @@
#include <mach/devices.h>
static inline struct device_d *imx1_add_uart0(void)
{
return imx_add_uart((void *)IMX_UART1_BASE, 0);
}
static inline struct device_d *imx1_add_uart1(void)
{
return imx_add_uart((void *)IMX_UART2_BASE, 1);
}

58
arch/arm/mach-imx/include/mach/devices-imx53.h Normal file
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@ -0,0 +1,58 @@
#include <mach/devices.h>
static inline struct device_d *imx53_add_spi0(struct spi_imx_master *pdata)
{
return imx_add_spi((void *)MX53_ECSPI1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx53_add_spi1(struct spi_imx_master *pdata)
{
return imx_add_spi((void *)MX53_ECSPI2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx53_add_i2c0(struct i2c_platform_data *pdata)
{
return imx_add_i2c((void *)MX53_I2C1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx53_add_i2c1(struct i2c_platform_data *pdata)
{
return imx_add_i2c((void *)MX53_I2C2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx53_add_uart0(void)
{
return imx_add_uart((void *)MX53_UART1_BASE_ADDR, 0);
}
static inline struct device_d *imx53_add_uart1(void)
{
return imx_add_uart((void *)MX53_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata)
{
return imx_add_fec((void *)MX53_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx53_add_mmc0(void *pdata)
{
return imx_add_esdhc((void *)MX53_ESDHC1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx53_add_mmc1(void *pdata)
{
return imx_add_esdhc((void *)MX53_ESDHC2_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx53_add_mmc2(void *pdata)
{
return imx_add_esdhc((void *)MX53_ESDHC3_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pdata)
{
return imx_add_nand((void *)MX53_NFC_AXI_BASE_ADDR, pdata);
}

6
arch/arm/mach-imx/include/mach/generic.h
View File

@ -51,5 +51,11 @@ u64 imx_uid(void);
#define cpu_is_mx51() (0)
#endif
#ifdef CONFIG_ARCH_IMX53
#define cpu_is_mx53() (1)
#else
#define cpu_is_mx53() (0)
#endif
#define cpu_is_mx23() (0)
#define cpu_is_mx28() (0)

38
arch/arm/mach-imx/include/mach/iim.h
View File

@ -24,6 +24,7 @@
#define __MACH_IMX_IIM_H
#include <errno.h>
#include <net.h>
#define IIM_STAT 0x0000
#define IIM_STATM 0x0004
@ -46,12 +47,47 @@ struct imx_iim_platform_data {
};
#ifdef CONFIG_IMX_IIM
int imx_iim_read(unsigned int bank, int offset, void *buf, int count);
int imx_iim_get_mac(unsigned char *mac);
#else
static inline int imx_iim_get_mac(unsigned char *mac)
static inline int imx_iim_read(unsigned int bank, int offset, void *buf,
int count)
{
return -EINVAL;
}
#endif /* CONFIG_IMX_IIM */
static inline int imx51_iim_register_fec_ethaddr(void)
{
int ret;
u8 buf[6];
ret = imx_iim_read(1, 9, buf, 6);
if (ret != 6)
return -EINVAL;
eth_register_ethaddr(0, buf);
return 0;
}
static inline int imx53_iim_register_fec_ethaddr(void)
{
return imx51_iim_register_fec_ethaddr();
}
static inline int imx25_iim_register_fec_ethaddr(void)
{
int ret;
u8 buf[6];
ret = imx_iim_read(0, 26, buf, 6);
if (ret != 6)
return -EINVAL;
eth_register_ethaddr(0, buf);
return 0;
}
#endif /* __MACH_IMX_IIM_H */

52
arch/arm/mach-imx/include/mach/imx-flash-header.h
View File

@ -49,6 +49,11 @@ struct imx_dcd_entry {
unsigned long val;
};
struct imx_dcd_v2_entry {
__be32 addr;
__be32 val;
};
#define DCD_BARKER 0xb17219e9
struct imx_rsa_public_key {
@ -73,4 +78,51 @@ struct imx_flash_header {
unsigned long dcd_block_len;
};
#define IVT_HEADER_TAG 0xd1
#define IVT_VERSION 0x40
#define DCD_HEADER_TAG 0xd2
#define DCD_VERSION 0x40
#define DCD_COMMAND_WRITE_TAG 0xcc
#define DCD_COMMAND_WRITE_PARAM 0x04
struct imx_ivt_header {
uint8_t tag;
__be16 length;
uint8_t version;
} __attribute__((packed));
struct imx_dcd_command {
uint8_t tag;
__be16 length;
uint8_t param;
} __attribute__((packed));
struct imx_dcd {
struct imx_ivt_header header;
struct imx_dcd_command command;
};
struct imx_boot_data {
uint32_t start;
uint32_t size;
uint32_t plugin;
};
struct imx_flash_header_v2 {
struct imx_ivt_header header;
uint32_t entry;
uint32_t reserved1;
uint32_t dcd_ptr;
uint32_t boot_data_ptr;
uint32_t self;
uint32_t csf;
uint32_t reserved2;
struct imx_boot_data boot_data;
struct imx_dcd dcd;
};
#endif /* __MACH_FLASH_HEADER_H */

4
arch/arm/mach-imx/include/mach/imx-regs.h
View File

@ -52,7 +52,9 @@
#elif defined CONFIG_ARCH_IMX25
# include <mach/imx25-regs.h>
#elif defined CONFIG_ARCH_IMX51
#include <mach/imx51-regs.h>
# include <mach/imx51-regs.h>
#elif defined CONFIG_ARCH_IMX53
# include <mach/imx53-regs.h>
#else
# error "unknown i.MX soc type"
#endif

1
arch/arm/mach-imx/include/mach/imx27-regs.h
View File

@ -29,6 +29,7 @@
#define IMX_FB_BASE (0x21000 + IMX_IO_BASE)
#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
#define IMX_OTG_BASE (0x24000 + IMX_IO_BASE)
#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)

139
arch/arm/mach-imx/include/mach/imx53-regs.h Normal file
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@ -0,0 +1,139 @@
#ifndef __MACH_IMX53_REGS_H
#define __MACH_IMX53_REGS_H
#define IMX_TIM1_BASE 0X53FA0000
#define IMX_WDT_BASE 0X53F98000
#define IMX_IOMUXC_BASE 0X53FA8000
#define GPT_TCTL 0x00
#define GPT_TPRER 0x04
#define GPT_TCMP 0x10
#define GPT_TCR 0x1c
#define GPT_TCN 0x24
#define GPT_TSTAT 0x08
/* Part 2: Bitfields */
#define TCTL_SWR (1<<15) /* Software reset */
#define TCTL_FRR (1<<9) /* Freerun / restart */
#define TCTL_CAP (3<<6) /* Capture Edge */
#define TCTL_OM (1<<5) /* output mode */
#define TCTL_IRQEN (1<<4) /* interrupt enable */
#define TCTL_CLKSOURCE (6) /* Clock source bit position */
#define TCTL_TEN (1) /* Timer enable */
#define TPRER_PRES (0xff) /* Prescale */
#define TSTAT_CAPT (1<<1) /* Capture event */
#define TSTAT_COMP (1) /* Compare event */
#define MX53_IROM_BASE_ADDR 0x0
/*
* SPBA global module enabled #0
*/
#define MX53_SPBA0_BASE_ADDR 0x50000000
#define MX53_SPBA0_SIZE SZ_1M
#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
/*
* AIPS 1
*/
#define MX53_AIPS1_BASE_ADDR 0x53F00000
#define MX53_AIPS1_SIZE SZ_1M
#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
/*
* AIPS 2
*/
#define MX53_AIPS2_BASE_ADDR 0x63F00000
#define MX53_AIPS2_SIZE SZ_1M
#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000
/*
* Memory regions and CS
*/
#define MX53_CSD0_BASE_ADDR 0x70000000
#define MX53_CSD1_BASE_ADDR 0xB0000000
#define MX53_CS0_BASE_ADDR 0xF0000000
#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
#define MX53_CS3_BASE_ADDR 0xF6000000
#endif /* __MACH_IMX53_REGS_H */

1203
arch/arm/mach-imx/include/mach/iomux-mx53.h Normal file
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File diff suppressed because it is too large Load Diff

60
arch/arm/mach-imx/speed-imx51.c
View File

@ -2,7 +2,7 @@
#include <asm/io.h>
#include <asm-generic/div64.h>
#include <mach/imx51-regs.h>
#include "mach/clock-imx51.h"
#include <mach/clock-imx51_53.h>
static u32 ccm_readl(u32 ofs)
{
@ -31,30 +31,30 @@ static unsigned long pll_get_rate(void __iomem *pllbase)
u64 temp;
unsigned long parent_rate;
dp_ctl = readl(pllbase + MX51_PLL_DP_CTL);
dp_ctl = readl(pllbase + MX5_PLL_DP_CTL);
if ((dp_ctl & MX51_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
parent_rate = fpm_get_rate();
else
parent_rate = osc_get_rate();
pll_hfsm = dp_ctl & MX51_PLL_DP_CTL_HFSM;
dbl = dp_ctl & MX51_PLL_DP_CTL_DPDCK0_2_EN;
pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM;
dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN;
if (pll_hfsm == 0) {
dp_op = readl(pllbase + MX51_PLL_DP_OP);
dp_mfd = readl(pllbase + MX51_PLL_DP_MFD);
dp_mfn = readl(pllbase + MX51_PLL_DP_MFN);
dp_op = readl(pllbase + MX5_PLL_DP_OP);
dp_mfd = readl(pllbase + MX5_PLL_DP_MFD);
dp_mfn = readl(pllbase + MX5_PLL_DP_MFN);
} else {
dp_op = readl(pllbase + MX51_PLL_DP_HFS_OP);
dp_mfd = readl(pllbase + MX51_PLL_DP_HFS_MFD);
dp_mfn = readl(pllbase + MX51_PLL_DP_HFS_MFN);
dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP);
dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD);
dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN);
}
pdf = dp_op & MX51_PLL_DP_OP_PDF_MASK;
mfi = (dp_op & MX51_PLL_DP_OP_MFI_MASK) >> MX51_PLL_DP_OP_MFI_OFFSET;
pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK;
mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET;
mfi = (mfi <= 5) ? 5 : mfi;
mfd = dp_mfd & MX51_PLL_DP_MFD_MASK;
mfn = mfn_abs = dp_mfn & MX51_PLL_DP_MFN_MASK;
mfd = dp_mfd & MX5_PLL_DP_MFD_MASK;
mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK;
/* Sign extend to 32-bits */
if (mfn >= 0x04000000) {
mfn |= 0xFC000000;
@ -117,11 +117,11 @@ unsigned long imx_get_uartclk(void)
parent_rate = pll2_sw_get_rate();
reg = ccm_readl(MX51_CCM_CSCDR1);
prediv = ((reg & MX51_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
podf = ((reg & MX51_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
reg = ccm_readl(MX5_CCM_CSCDR1);
prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
return parent_rate / (prediv * podf);
}
@ -130,7 +130,7 @@ static unsigned long imx_get_ahbclk(void)
{
u32 reg, div;
reg = ccm_readl(MX51_CCM_CBCDR);
reg = ccm_readl(MX5_CCM_CBCDR);
div = ((reg >> 10) & 0x7) + 1;
return pll2_sw_get_rate() / div;
@ -140,7 +140,7 @@ unsigned long imx_get_ipgclk(void)
{
u32 reg, div;
reg = ccm_readl(MX51_CCM_CBCDR);
reg = ccm_readl(MX5_CCM_CBCDR);
div = ((reg >> 8) & 0x3) + 1;
return imx_get_ahbclk() / div;
@ -160,20 +160,20 @@ unsigned long imx_get_mmcclk(void)
{
u32 reg, prediv, podf, rate;
reg = ccm_readl(MX51_CCM_CSCMR1);
reg &= MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
reg >>= MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
reg = ccm_readl(MX5_CCM_CSCMR1);
reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
rate = get_rate_select(reg,
pll1_main_get_rate,
pll2_sw_get_rate,
pll3_sw_get_rate,
NULL);
reg = ccm_readl(MX51_CCM_CSCDR1);
prediv = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
podf = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
reg = ccm_readl(MX5_CCM_CSCDR1);
prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
return rate / (prediv * podf);
}

204
arch/arm/mach-imx/speed-imx53.c Normal file
View File

@ -0,0 +1,204 @@
#include <common.h>
#include <asm/io.h>
#include <asm-generic/div64.h>
#include <mach/imx-regs.h>
#include "mach/clock-imx51_53.h"
static u32 ccm_readl(u32 ofs)
{
return readl(MX53_CCM_BASE_ADDR + ofs);
}
static unsigned long ckil_get_rate(void)
{
return 32768;
}
static unsigned long osc_get_rate(void)
{
return 24000000;
}
static unsigned long fpm_get_rate(void)
{
return ckil_get_rate() * 512;
}
static unsigned long pll_get_rate(void __iomem *pllbase)
{
long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
u64 temp;
unsigned long parent_rate;
dp_ctl = readl(pllbase + MX5_PLL_DP_CTL);
if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
parent_rate = fpm_get_rate();
else
parent_rate = osc_get_rate();
pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM;
dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN;
if (pll_hfsm == 0) {
dp_op = readl(pllbase + MX5_PLL_DP_OP);
dp_mfd = readl(pllbase + MX5_PLL_DP_MFD);
dp_mfn = readl(pllbase + MX5_PLL_DP_MFN);
} else {
dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP);
dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD);
dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN);
}
pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK;
mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET;
mfi = (mfi <= 5) ? 5 : mfi;
mfd = dp_mfd & MX5_PLL_DP_MFD_MASK;
mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK;
/* Sign extend to 32-bits */
if (mfn >= 0x04000000) {
mfn |= 0xFC000000;
mfn_abs = -mfn;
}
ref_clk = 2 * parent_rate;
if (dbl != 0)
ref_clk *= 2;
ref_clk /= (pdf + 1);
temp = (u64)ref_clk * mfn_abs;
do_div(temp, mfd + 1);
if (mfn < 0)
temp = -temp;
temp = (ref_clk * mfi) + temp;
return temp;
}
static unsigned long pll1_main_get_rate(void)
{
return pll_get_rate((void __iomem *)MX53_PLL1_BASE_ADDR);
}
static unsigned long pll2_sw_get_rate(void)
{
return pll_get_rate((void __iomem *)MX53_PLL2_BASE_ADDR);
}
static unsigned long pll3_sw_get_rate(void)
{
return pll_get_rate((void __iomem *)MX53_PLL3_BASE_ADDR);
}
static unsigned long pll4_sw_get_rate(void)
{
return pll_get_rate((void __iomem *)MX53_PLL4_BASE_ADDR);
}
static unsigned long get_rate_select(int select,
unsigned long (* get_rate1)(void),
unsigned long (* get_rate2)(void),
unsigned long (* get_rate3)(void),
unsigned long (* get_rate4)(void))
{
switch (select) {
case 0:
return get_rate1() ? get_rate1() : 0;
case 1:
return get_rate2() ? get_rate2() : 0;
case 2:
return get_rate3 ? get_rate3() : 0;
case 3:
return get_rate4 ? get_rate4() : 0;
}
return 0;
}
unsigned long imx_get_uartclk(void)
{
u32 reg, prediv, podf;
unsigned long parent_rate;
reg = ccm_readl(MX5_CCM_CSCMR1);
reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
parent_rate = get_rate_select(reg,
pll1_main_get_rate,
pll2_sw_get_rate,
pll3_sw_get_rate,
pll4_sw_get_rate);
reg = ccm_readl(MX5_CCM_CSCDR1);
prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
return parent_rate / (prediv * podf);
}
static unsigned long imx_get_ahbclk(void)
{
u32 reg, div;
reg = ccm_readl(MX5_CCM_CBCDR);
div = ((reg >> 10) & 0x7) + 1;
return pll2_sw_get_rate() / div;
}
unsigned long imx_get_ipgclk(void)
{
u32 reg, div;
reg = ccm_readl(MX5_CCM_CBCDR);
div = ((reg >> 8) & 0x3) + 1;
return imx_get_ahbclk() / div;
}
unsigned long imx_get_gptclk(void)
{
return imx_get_ipgclk();
}
unsigned long imx_get_fecclk(void)
{
return imx_get_ipgclk();
}
unsigned long imx_get_mmcclk(void)
{
u32 reg, prediv, podf, rate;
reg = ccm_readl(MX5_CCM_CSCMR1);
reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
rate = get_rate_select(reg,
pll1_main_get_rate,
pll2_sw_get_rate,
pll3_sw_get_rate,
pll4_sw_get_rate);
reg = ccm_readl(MX5_CCM_CSCDR1);
prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
return rate / (prediv * podf);
}
void imx_dump_clocks(void)
{
printf("pll1: %ld\n", pll1_main_get_rate());
printf("pll2: %ld\n", pll2_sw_get_rate());
printf("pll3: %ld\n", pll3_sw_get_rate());
printf("pll4: %ld\n", pll4_sw_get_rate());
printf("uart: %ld\n", imx_get_uartclk());
printf("ipg: %ld\n", imx_get_ipgclk());
printf("fec: %ld\n", imx_get_fecclk());
printf("gpt: %ld\n", imx_get_gptclk());
}

2
arch/arm/mach-mxs/Kconfig
View File

@ -39,7 +39,6 @@ config MACH_MX23EVK
config MACH_CHUMBY
bool "Chumby Falconwing"
select HAVE_MMU
help
Say Y here if you are using the "chumby one" aka falconwing from
Chumby Industries
@ -55,7 +54,6 @@ choice
config MACH_TX28
bool "KARO tx28"
select HAVE_MMU
help
Say Y here if you are using the KARO TX28 CPU module.

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