clk: tegra: add Tegra124 driver
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach
Sascha Hauer
parent
89b062b430
commit
dc726ec5b5
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@ -6,3 +6,4 @@ obj-y += clk-pll-out.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
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@ -0,0 +1,349 @@
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/*
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* Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* Based on the Linux Tegra clock code
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <dt-bindings/clock/tegra124-car.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/lowlevel.h>
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#include <mach/tegra20-car.h>
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#include <mach/tegra30-car.h>
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#include "clk.h"
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static void __iomem *car_base;
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static struct clk *clks[TEGRA124_CLK_CLK_MAX];
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static struct clk_onecell_data clk_data;
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static unsigned int get_pll_ref_div(void)
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{
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u32 osc_ctrl = readl(car_base + CRC_OSC_CTRL);
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return 1U << ((osc_ctrl & CRC_OSC_CTRL_PLL_REF_DIV_MASK) >>
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CRC_OSC_CTRL_PLL_REF_DIV_SHIFT);
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}
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static void tegra124_osc_clk_init(void)
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{
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clks[TEGRA124_CLK_CLK_M] = clk_fixed("clk_m", tegra_get_osc_clock());
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clks[TEGRA124_CLK_CLK_32K] = clk_fixed("clk_32k", 32768);
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clks[TEGRA124_CLK_PLL_REF] = clk_fixed_factor("pll_ref", "clk_m", 1,
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get_pll_ref_div(), 0);
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}
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/* PLL frequency tables */
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static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
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{ 12000000, 624000000, 104, 1, 2},
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{ 12000000, 600000000, 100, 1, 2},
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{ 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
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{ 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
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{ 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
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{ 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
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{12000000, 408000000, 408, 12, 0, 8},
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{13000000, 408000000, 408, 13, 0, 8},
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{16800000, 408000000, 340, 14, 0, 8},
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{19200000, 408000000, 340, 16, 0, 8},
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{26000000, 408000000, 408, 26, 0, 8},
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{0, 0, 0, 0, 0, 0},
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};
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static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
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{12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
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{13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
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{16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
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{19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
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{26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
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{0, 0, 0, 0, 0, 0},
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};
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static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
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/* 1 GHz */
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{12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
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{13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
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{16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
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{19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
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{26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
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{0, 0, 0, 0, 0, 0},
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};
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static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
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{12000000, 480000000, 960, 12, 2, 12},
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{13000000, 480000000, 960, 13, 2, 12},
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{16800000, 480000000, 400, 7, 2, 5},
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{19200000, 480000000, 200, 4, 2, 3},
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{26000000, 480000000, 960, 26, 2, 12},
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{0, 0, 0, 0, 0, 0},
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};
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/* PLL parameters */
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static struct tegra_clk_pll_params pll_c_params = {
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.input_min = 12000000,
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.input_max = 800000000,
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.cf_min = 12000000,
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.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
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.vco_min = 600000000,
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.vco_max = 1400000000,
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.base_reg = CRC_PLLC_BASE,
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.misc_reg = CRC_PLLC_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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static struct tegra_clk_pll_params pll_p_params = {
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.input_min = 2000000,
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.input_max = 31000000,
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.cf_min = 1000000,
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.cf_max = 6000000,
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.vco_min = 200000000,
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.vco_max = 700000000,
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.base_reg = CRC_PLLP_BASE,
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.misc_reg = CRC_PLLP_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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static struct tegra_clk_pll_params pll_m_params = {
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.input_min = 12000000,
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.input_max = 500000000,
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.cf_min = 12000000,
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.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
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.vco_min = 400000000,
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.vco_max = 1066000000,
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.base_reg = CRC_PLLM_BASE,
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.misc_reg = CRC_PLLM_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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static struct tegra_clk_pll_params pll_x_params = {
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.input_min = 12000000,
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.input_max = 800000000,
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.cf_min = 12000000,
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.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
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.vco_min = 700000000,
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.vco_max = 3000000000UL,
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.base_reg = CRC_PLLX_BASE,
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.misc_reg = CRC_PLLX_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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static struct tegra_clk_pll_params pll_u_params = {
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.input_min = 2000000,
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.input_max = 40000000,
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.cf_min = 1000000,
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.cf_max = 6000000,
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.vco_min = 48000000,
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.vco_max = 960000000,
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.base_reg = CRC_PLLU_BASE,
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.misc_reg = CRC_PLLU_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLLDU_MISC_LOCK_ENABLE,
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.lock_delay = 1000,
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};
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static void tegra124_pll_init(void)
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{
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/* PLLC */
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clks[TEGRA124_CLK_PLL_C] = tegra_clk_register_pll("pll_c", "pll_ref",
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car_base, 0, 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
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pll_c_freq_table);
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clks[TEGRA124_CLK_PLL_C_OUT1] = tegra_clk_register_pll_out("pll_c_out1",
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"pll_c", car_base + CRC_PLLC_OUT, 0,
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TEGRA_DIVIDER_ROUND_UP);
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/* PLLP */
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clks[TEGRA124_CLK_PLL_P] = tegra_clk_register_pll("pll_p", "pll_ref",
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car_base, 0, 408000000, &pll_p_params, TEGRA_PLL_FIXED |
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TEGRA_PLL_HAS_CPCON, pll_p_freq_table);
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clks[TEGRA124_CLK_PLL_P_OUT1] = tegra_clk_register_pll_out("pll_p_out1",
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"pll_p", car_base + CRC_PLLP_OUTA, 0,
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TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
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clks[TEGRA124_CLK_PLL_P_OUT2] = tegra_clk_register_pll_out("pll_p_out2",
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"pll_p", car_base + CRC_PLLP_OUTA, 16,
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TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
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clks[TEGRA124_CLK_PLL_P_OUT3] = tegra_clk_register_pll_out("pll_p_out3",
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"pll_p", car_base + CRC_PLLP_OUTB, 0,
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TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
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clks[TEGRA124_CLK_PLL_P_OUT4] = tegra_clk_register_pll_out("pll_p_out4",
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"pll_p", car_base + CRC_PLLP_OUTB, 16,
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TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
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/* PLLM */
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clks[TEGRA124_CLK_PLL_M] = tegra_clk_register_pll("pll_m", "pll_ref",
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car_base, 0, 0, &pll_m_params, TEGRA_PLL_HAS_CPCON,
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pll_m_freq_table);
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clks[TEGRA124_CLK_PLL_M_OUT1] = tegra_clk_register_pll_out("pll_m_out1",
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"pll_m", car_base + CRC_PLLM_OUT, 0,
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TEGRA_DIVIDER_ROUND_UP);
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/* PLLX */
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clks[TEGRA124_CLK_PLL_X] = tegra_clk_register_pll("pll_x", "pll_ref",
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car_base, 0, 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
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pll_x_freq_table);
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/* PLLU */
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clks[TEGRA124_CLK_PLL_U] = tegra_clk_register_pll("pll_u", "pll_ref",
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car_base, 0, 0, &pll_u_params, TEGRA_PLLU |
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TEGRA_PLL_HAS_CPCON, pll_u_freq_table);
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}
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static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c2", "pll_c", "pll_c3",
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"pll_m", "rsvd", "clk_m"};
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static void tegra124_periph_init(void)
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{
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/* peripheral clocks without a divider */
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clks[TEGRA124_CLK_UARTA] = tegra_clk_register_periph_nodiv("uarta",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTA, TEGRA124_CLK_UARTA,
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TEGRA_PERIPH_ON_APB);
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clks[TEGRA124_CLK_UARTB] = tegra_clk_register_periph_nodiv("uartb",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTB, 7,
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TEGRA_PERIPH_ON_APB);
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clks[TEGRA124_CLK_UARTC] = tegra_clk_register_periph_nodiv("uartc",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTC, TEGRA124_CLK_UARTC,
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TEGRA_PERIPH_ON_APB);
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clks[TEGRA124_CLK_UARTD] = tegra_clk_register_periph_nodiv("uartd",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTD, TEGRA124_CLK_UARTD,
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TEGRA_PERIPH_ON_APB);
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/* peripheral clocks with a divider */
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clks[TEGRA124_CLK_MSELECT] = tegra_clk_register_periph("mselect",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_MSEL, TEGRA124_CLK_MSELECT, 1);
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clks[TEGRA124_CLK_SDMMC1] = tegra_clk_register_periph("sdmmc1",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_SDMMC1, TEGRA124_CLK_SDMMC1, 1);
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clks[TEGRA124_CLK_SDMMC2] = tegra_clk_register_periph("sdmmc2",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_SDMMC2, TEGRA124_CLK_SDMMC2, 1);
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clks[TEGRA124_CLK_SDMMC3] = tegra_clk_register_periph("sdmmc3",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_SDMMC3, TEGRA124_CLK_SDMMC3, 1);
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clks[TEGRA124_CLK_SDMMC4] = tegra_clk_register_periph("sdmmc4",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_SDMMC4, TEGRA124_CLK_SDMMC4, 1);
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clks[TEGRA124_CLK_I2C1] = tegra_clk_register_periph_div16("i2c1",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_I2C1, TEGRA124_CLK_I2C1, 1);
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clks[TEGRA124_CLK_I2C2] = tegra_clk_register_periph_div16("i2c2",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_I2C2, TEGRA124_CLK_I2C2, 1);
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clks[TEGRA124_CLK_I2C3] = tegra_clk_register_periph_div16("i2c3",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_I2C3, TEGRA124_CLK_I2C3, 1);
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clks[TEGRA124_CLK_I2C4] = tegra_clk_register_periph_div16("i2c4",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_I2C4, TEGRA124_CLK_I2C4, 1);
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clks[TEGRA124_CLK_I2C5] = tegra_clk_register_periph_div16("i2c5",
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mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_DVC, TEGRA124_CLK_I2C5, 1);
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}
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static struct tegra_clk_init_table init_table[] = {
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//{TEGRA124_CLK_PLL_P, TEGRA124_CLK_CLK_MAX, 408000000, 1},
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{TEGRA124_CLK_PLL_P_OUT1, TEGRA124_CLK_CLK_MAX, 9600000, 1},
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{TEGRA124_CLK_PLL_P_OUT2, TEGRA124_CLK_CLK_MAX, 48000000, 1},
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{TEGRA124_CLK_PLL_P_OUT3, TEGRA124_CLK_CLK_MAX, 102000000, 1},
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{TEGRA124_CLK_PLL_P_OUT4, TEGRA124_CLK_CLK_MAX, 204000000, 1},
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{TEGRA124_CLK_MSELECT, TEGRA124_CLK_PLL_P, 204000000, 1},
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{TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 0, 1},
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{TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 0, 1},
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{TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 0, 1},
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{TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 0, 1},
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{TEGRA124_CLK_SDMMC1, TEGRA124_CLK_PLL_P, 48000000, 0},
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{TEGRA124_CLK_SDMMC2, TEGRA124_CLK_PLL_P, 48000000, 0},
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{TEGRA124_CLK_SDMMC3, TEGRA124_CLK_PLL_P, 48000000, 0},
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{TEGRA124_CLK_SDMMC4, TEGRA124_CLK_PLL_P, 48000000, 0},
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{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, /* sentinel */
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};
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static int tegra124_car_probe(struct device_d *dev)
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{
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car_base = dev_request_mem_region(dev, 0);
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if (!car_base)
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return -EBUSY;
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tegra124_osc_clk_init();
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tegra124_pll_init();
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tegra124_periph_init();
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tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX);
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/* speed up system bus */
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writel(CRC_SCLK_BURST_POLICY_SYS_STATE_RUN <<
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CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT |
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CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT4 <<
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CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT,
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car_base + CRC_SCLK_BURST_POLICY);
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clk_data.clks = clks;
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clk_data.clk_num = ARRAY_SIZE(clks);
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of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
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&clk_data);
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tegra_clk_init_rst_controller(car_base, dev->device_node, 6 * 32);
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tegra_clk_reset_uarts();
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return 0;
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}
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static __maybe_unused struct of_device_id tegra124_car_dt_ids[] = {
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{
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.compatible = "nvidia,tegra124-car",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d tegra124_car_driver = {
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.probe = tegra124_car_probe,
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.name = "tegra124-car",
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.of_compatible = DRV_OF_COMPAT(tegra124_car_dt_ids),
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};
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static int tegra124_car_init(void)
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{
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return platform_driver_register(&tegra124_car_driver);
|
||||
}
|
||||
postcore_initcall(tegra124_car_init);
|
||||
Loading…
Reference in New Issue