diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c index 9cd9722ee..59b9acb2f 100644 --- a/board/evb64260/pci.c +++ b/board/evb64260/pci.c @@ -629,6 +629,7 @@ static void gt_setup_ide (struct pci_controller *hose, } } +#ifndef CONFIG_P3G4 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) { unsigned char pin, irq; @@ -642,6 +643,7 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); } } +#endif struct pci_config_table gt_config_table[] = { {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, @@ -651,12 +653,16 @@ struct pci_config_table gt_config_table[] = { }; struct pci_controller pci0_hose = { +#ifndef CONFIG_P3G4 fixup_irq:gt_fixup_irq, +#endif config_table:gt_config_table, }; struct pci_controller pci1_hose = { +#ifndef CONFIG_P3G4 fixup_irq:gt_fixup_irq, +#endif config_table:gt_config_table, }; @@ -692,8 +698,10 @@ void pci_init_board (void) pci_register_hose (&pci0_hose); +#ifndef CONFIG_P3G4 pciArbiterEnable (PCI_HOST0); pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); +#endif command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); command |= PCI_COMMAND_MASTER; @@ -735,8 +743,10 @@ void pci_init_board (void) pci_register_hose (&pci1_hose); +#ifndef CONFIG_P3G4 pciArbiterEnable (PCI_HOST1); pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); +#endif command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); command |= PCI_COMMAND_MASTER; diff --git a/common/cmd_universe.c b/common/cmd_universe.c index a8febff02..8d7b6fee1 100644 --- a/common/cmd_universe.c +++ b/common/cmd_universe.c @@ -72,6 +72,9 @@ int universe_init(void) dev->busdevfn = busdevfn; pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_1, &val); + if (val & 1) { + pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val); + } val &= ~0xf; dev->uregs = (UNIVERSE *)val; @@ -102,7 +105,13 @@ int universe_init(void) * Arbitration Mode * DTACK Enable */ - writel(0x15060000, &dev->uregs->misc_ctl); + writel(0x15040000 | (readl(&dev->uregs->misc_ctl) & 0x00020000), &dev->uregs->misc_ctl); + + if (readl(&dev->uregs->misc_ctl) & 0x00020000) { + debug ("System Controller!\n"); /* test-only */ + } else { + debug ("Not System Controller!\n"); /* test-only */ + } /* * Lets turn off interrupts @@ -114,12 +123,14 @@ int universe_init(void) writel(0x0000, &dev->uregs->lint_map1); /* Map all ints to 0 */ eieio(); + return 0; + break_30: free(dev); break_20: lastError = result; - return 0; + return result; } @@ -193,13 +204,13 @@ int universe_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int si switch (pms & PCI_MS_Mxx) { case PCI_MS_MEM: - ctl = 0x00000000; + ctl |= 0x00000000; break; case PCI_MS_IO: - ctl = 0x00000001; + ctl |= 0x00000001; break; case PCI_MS_CONFIG: - ctl = 0x00000002; + ctl |= 0x00000002; break; } @@ -278,13 +289,13 @@ int universe_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int si switch (pms & PCI_MS_Mxx) { case PCI_MS_MEM: - ctl = 0x00000000; + ctl |= 0x00000000; break; case PCI_MS_IO: - ctl = 0x00000001; + ctl |= 0x00000001; break; case PCI_MS_CONFIG: - ctl = 0x00000002; + ctl |= 0x00000002; break; } diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index c56ad11b9..7d6bbf51d 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -28,8 +28,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include - #ifndef __ASSEMBLY__ #include #endif @@ -66,7 +64,7 @@ * mpsc channel, change CONFIG_MPSC_PORT to the desired value. */ #define CONFIG_MPSC -#define CONFIG_MPSC_PORT 1 +#define CONFIG_MPSC_PORT 0 #define CONFIG_NET_MULTI /* attempt all available adapters */ @@ -75,20 +73,46 @@ #undef CONFIG_ETHER_PORT_MII /* use RMII */ -#if 1 +#if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif #define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + #undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none;" \ - "bootm" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=p3g4\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_74xx\0" \ + "bootfile=/tftpboot/p3g4/uImage\0" \ + "kernel_addr=ff000000\0" \ + "ramdisk_addr=ff010000\0" \ + "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ + "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ + "cp.b 100000 fff00000 $(filesize);" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ @@ -101,7 +125,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_UNIVERSE| \ + CFG_CMD_BSP ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -271,21 +303,20 @@ /* PCI MEMORY MAP section */ #define CFG_PCI0_MEM_BASE 0x80000000 #define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) + #define CFG_PCI1_MEM_BASE 0x88000000 #define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - /* PCI I/O MAP section */ #define CFG_PCI0_IO_BASE 0xfa000000 #define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) #define CFG_PCI0_IO_SPACE_PCI 0x00000000 + +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) #define CFG_PCI1_IO_SPACE_PCI 0x00000000