ARM i.MX: Add support for the Freescale i.MX6 sabrelite board
This adds support for the Freescale i.MX6 sabrelite board with: - FEC - SD2/3 - SPI flash Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
e3040756e6
commit
e58ca031f6
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@ -137,6 +137,7 @@ board-$(CONFIG_MACH_TX51) := karo-tx51
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board-$(CONFIG_MACH_MX6Q_ARM2) := freescale-mx6-arm2
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board-$(CONFIG_MACH_TOSHIBA_AC100) := toshiba-ac100
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board-$(CONFIG_MACH_CCMX51) := ccxmx51
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board-$(CONFIG_MACH_SABRELITE) := freescale-mx6-sabrelite
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machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
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@ -0,0 +1 @@
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obj-y += board.o flash_header.o
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@ -0,0 +1,265 @@
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/*
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* Copyright (C) 2012 Steffen Trumtrar, Pengutronix
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*
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* based on arch/arm/boards/freescale-mx6-arm2/board.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <fec.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <miidev.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <mach/generic.h>
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#include <sizes.h>
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#include <net.h>
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#include <mach/imx6.h>
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#include <mach/devices-imx6.h>
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#include <mach/iomux-mx6.h>
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#include <mach/gpio.h>
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#include <spi/spi.h>
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#include <mach/spi.h>
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#define SABRELITE_SD3_WP IMX_GPIO_NR(7, 1)
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#define SABRELITE_SD3_CD IMX_GPIO_NR(7, 0)
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#define SABRELITE_SD4_CD IMX_GPIO_NR(2, 6)
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static iomux_v3_cfg_t sabrelite_pads[] = {
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/* UART1 */
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MX6Q_PAD_SD3_DAT6__UART1_RXD,
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MX6Q_PAD_SD3_DAT7__UART1_TXD,
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MX6Q_PAD_EIM_D26__UART2_TXD,
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MX6Q_PAD_EIM_D27__UART2_RXD,
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/* SD3 (bottom) */
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MX6Q_PAD_SD3_CMD__USDHC3_CMD,
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MX6Q_PAD_SD3_CLK__USDHC3_CLK,
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
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MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
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MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
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MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
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MX6Q_PAD_SD3_DAT4__GPIO_7_1, /* WP */
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MX6Q_PAD_SD3_DAT5__GPIO_7_0, /* CD */
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/* SD4 (top) */
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MX6Q_PAD_SD4_CLK__USDHC4_CLK,
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MX6Q_PAD_SD4_CMD__USDHC4_CMD,
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MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
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MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
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MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
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MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
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MX6Q_PAD_NANDF_D6__GPIO_2_6, /* CD */
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/* ECSPI */
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MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
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MX6Q_PAD_EIM_D17__ECSPI1_MISO,
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MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
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MX6Q_PAD_EIM_D19__GPIO_3_19, /* CS1 */
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};
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static iomux_v3_cfg_t sabrelite_enet_pads[] = {
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/* Ethernet */
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MX6Q_PAD_ENET_MDC__ENET_MDC,
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MX6Q_PAD_ENET_MDIO__ENET_MDIO,
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MX6Q_PAD_ENET_REF_CLK__GPIO_1_23, // LED mode
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MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
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MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
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MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
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MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
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MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
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MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
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MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
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MX6Q_PAD_EIM_D23__GPIO_3_23, /* RGMII_nRST */
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MX6Q_PAD_RGMII_RXC__GPIO_6_30, /* PHYAD */
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MX6Q_PAD_RGMII_RD0__GPIO_6_25, /* MODE0 */
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MX6Q_PAD_RGMII_RD1__GPIO_6_27, /* MODE1 */
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MX6Q_PAD_RGMII_RD2__GPIO_6_28, /* MODE2 */
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MX6Q_PAD_RGMII_RD3__GPIO_6_29, /* MODE3 */
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MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24,
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};
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static iomux_v3_cfg_t sabrelite_enet2_pads[] = {
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MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
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MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
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MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
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MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
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MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
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MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
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MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
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};
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static int sabrelite_mem_init(void)
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{
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arm_add_mem_device("ram0", 0x10000000, SZ_1G);
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return 0;
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}
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mem_initcall(sabrelite_mem_init);
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static struct fec_platform_data fec_info = {
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.xcv_type = RGMII,
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.phy_addr = 6,
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};
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int mx6_rgmii_rework(void)
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{
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struct mii_device *mdev;
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mdev = mii_open("phy0");
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if (!mdev) {
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printf("unable to open phy0\n");
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return -ENODEV;
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}
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mii_write(mdev, mdev->address, 0x09, 0x0f00);
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/* do same as linux kernel */
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/* min rx data delay */
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mii_write(mdev, mdev->address, 0x0b, 0x8105);
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mii_write(mdev, mdev->address, 0x0c, 0x0000);
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/* max rx/tx clock delay, min rx/tx control delay */
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mii_write(mdev, mdev->address, 0x0b, 0x8104);
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mii_write(mdev, mdev->address, 0x0c, 0xf0f0);
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mii_write(mdev, mdev->address, 0x0b, 0x104);
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mii_close(mdev);
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return 0;
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}
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static int sabrelite_ksz9021rn_setup(void)
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{
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mxc_iomux_v3_setup_multiple_pads(sabrelite_enet_pads, ARRAY_SIZE(sabrelite_enet_pads));
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gpio_direction_output(87, 0); /* GPIO 3-23 */
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gpio_direction_output(190, 1); /* GPIO 6-30: PHYAD2 */
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/* LED-Mode: Tri-Color Dual LED Mode */
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gpio_direction_output(23 , 0); /* GPIO 1-23 */
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/* MODE strap-in pins: advertise all capabilities */
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gpio_direction_output(185, 1); /* GPIO 6-25 */
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gpio_direction_output(187, 1); /* GPIO 6-27 */
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gpio_direction_output(188, 1); /* GPIO 6-28*/
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gpio_direction_output(189, 1); /* GPIO 6-29 */
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/* Enable 125 MHz clock output */
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gpio_direction_output(184, 1); /* GPIO 6-24 */
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mdelay(10);
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gpio_set_value(87, 1);
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mxc_iomux_v3_setup_multiple_pads(sabrelite_enet2_pads, ARRAY_SIZE(sabrelite_enet2_pads));
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return 0;
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}
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static inline int imx6_iim_register_fec_ethaddr(void)
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{
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u32 value;
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u8 buf[6];
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value = readl(MX6_OCOTP_BASE_ADDR + 0x630);
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buf[0] = (value >> 8);
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buf[1] = value;
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value = readl(MX6_OCOTP_BASE_ADDR + 0x620);
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buf[2] = value >> 24;
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buf[3] = value >> 16;
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buf[4] = value >> 8;
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buf[5] = value;
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eth_register_ethaddr(0, buf);
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return 0;
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}
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static int sabrelite_spi_cs[] = {GPIO_PORTC + 19};
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static struct spi_imx_master sabrelite_spi_0_data = {
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.chipselect = sabrelite_spi_cs,
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.num_chipselect = ARRAY_SIZE(sabrelite_spi_cs),
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};
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static const struct spi_board_info sabrelite_spi_board_info[] = {
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{
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.name = "m25p",
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.max_speed_hz = 40000000,
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.bus_num = 0,
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.chip_select = 0,
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}
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};
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static struct esdhc_platform_data sabrelite_sd3_data = {
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.cd_gpio = SABRELITE_SD3_CD,
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.cd_type = ESDHC_CD_GPIO,
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.wp_gpio = SABRELITE_SD3_WP,
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.wp_type = ESDHC_WP_GPIO,
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};
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static struct esdhc_platform_data sabrelite_sd4_data = {
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.cd_gpio = SABRELITE_SD4_CD,
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.cd_type = ESDHC_CD_GPIO,
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.wp_type = ESDHC_WP_NONE,
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};
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static int sabrelite_devices_init(void)
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{
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imx6_add_mmc2(&sabrelite_sd3_data);
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imx6_add_mmc3(&sabrelite_sd4_data);
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sabrelite_ksz9021rn_setup();
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imx6_iim_register_fec_ethaddr();
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imx6_add_fec(&fec_info);
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mx6_rgmii_rework();
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spi_register_board_info(sabrelite_spi_board_info,
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ARRAY_SIZE(sabrelite_spi_board_info));
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imx6_add_spi0(&sabrelite_spi_0_data);
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armlinux_set_bootparams((void *)0x10000100);
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armlinux_set_architecture(3769);
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devfs_add_partition("m25p0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("m25p0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
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return 0;
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}
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device_initcall(sabrelite_devices_init);
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static int sabrelite_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(sabrelite_pads, ARRAY_SIZE(sabrelite_pads));
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imx6_init_lowlevel();
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imx6_add_uart1();
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return 0;
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}
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console_initcall(sabrelite_console_init);
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@ -0,0 +1,4 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#endif /* __CONFIG_H */
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@ -0,0 +1,8 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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init-menu-add-entry "$0" "Base bootargs"
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exit
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fi
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global.linux.bootargs.base="console=ttymxc1,115200"
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@ -0,0 +1,8 @@
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#!/bin/sh
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if [ "$1" = menu ]; then
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init-menu-add-entry "$0" "hostname"
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exit
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fi
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global.hostname=SabreLite
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@ -0,0 +1,178 @@
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/*
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* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <asm/byteorder.h>
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#include <mach/imx-flash-header.h>
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#include <mach/imx6-regs.h>
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#include <asm/barebox-arm-head.h>
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void __naked __flash_header_start go(void)
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{
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barebox_arm_head();
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}
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#define DCD(a, v) { .addr = cpu_to_be32(a), .val = cpu_to_be32(v), }
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struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5a8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x524, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x51c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x518, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x50c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5c0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5ac, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b4, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x528, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x520, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x514, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x510, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5bc, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5c4, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x56c, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x578, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x588, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x594, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x57c, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x590, 0x00003000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x598, 0x00003000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x58c, 0x00000000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x59c, 0x00003030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5a0, 0x00003030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x784, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x788, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x794, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x79c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a4, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x748, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x74c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x750, 0x00020000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x758, 0x00000000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x774, 0x00020000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x78c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x798, 0x000C0000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x81c, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x820, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x824, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x828, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x81c, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x820, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x824, 0x33333333),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x828, 0x33333333),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x018, 0x00081740),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008000),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x008, 0x09444040),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x004, 0x00025576),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x040, 0x00000027),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x000, 0x831A0000),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04088032),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008033),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428031),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428039),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408030),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408038),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008040),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008048),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x800, 0xA1380003),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x800, 0xA1380003),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x020, 0x00005800),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x818, 0x00022227),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x818, 0x00022227),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x840, 0x034C0359),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x840, 0x03650348),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x848, 0x4436383B),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x848, 0x39393341),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x850, 0x35373933),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x850, 0x48254A36),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x810, 0x001F001F),
|
||||
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x80c, 0x00440044),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x810, 0x00440044),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800),
|
||||
DCD(MX6_MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800),
|
||||
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00000000),
|
||||
DCD(MX6_MMDC_P0_BASE_ADDR + 0x404, 0x00011006),
|
||||
|
||||
DCD(MX6_CCM_BASE_ADDR + 0x068, 0x00c03f3f),
|
||||
DCD(MX6_CCM_BASE_ADDR + 0x06c, 0x0030fc03),
|
||||
DCD(MX6_CCM_BASE_ADDR + 0x070, 0x0fffc000),
|
||||
DCD(MX6_CCM_BASE_ADDR + 0x074, 0x3ff00000),
|
||||
DCD(MX6_CCM_BASE_ADDR + 0x078, 0x00fff300),
|
||||
DCD(MX6_CCM_BASE_ADDR + 0x07c, 0x0f0000c3),
|
||||
DCD(MX6_CCM_BASE_ADDR + 0x080, 0x000003ff),
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DCD(MX6_IOMUXC_BASE_ADDR + 0x010, 0xf00000cf),
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
DCD(MX6_IOMUXC_BASE_ADDR + 0x018, 0x007f007f),
|
||||
DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
|
||||
};
|
||||
|
||||
#define APP_DEST CONFIG_TEXT_BASE
|
||||
|
||||
struct imx_flash_header_v2 __flash_header_section flash_header = {
|
||||
.header.tag = IVT_HEADER_TAG,
|
||||
.header.length = cpu_to_be16(32),
|
||||
.header.version = IVT_VERSION,
|
||||
.entry = (u32)_stext,
|
||||
.dcd_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, dcd),
|
||||
.boot_data_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, boot_data),
|
||||
.self = APP_DEST + FLASH_HEADER_OFFSET,
|
||||
|
||||
.boot_data.start = APP_DEST,
|
||||
.boot_data.size = barebox_image_size,
|
||||
|
||||
.dcd.header.tag = DCD_HEADER_TAG,
|
||||
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
|
||||
.dcd.header.version = DCD_VERSION,
|
||||
|
||||
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
|
||||
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
|
||||
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
|
||||
};
|
||||
|
|
@ -27,6 +27,7 @@ config ARCH_TEXT_BASE
|
|||
default 0x97f00000 if MACH_TX51
|
||||
default 0x4fc00000 if MACH_MX6Q_ARM2
|
||||
default 0x97f00000 if MACH_CCMX51
|
||||
default 0x4fc00000 if MACH_SABRELITE
|
||||
|
||||
config BOARDINFO
|
||||
default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
|
||||
|
|
@ -52,6 +53,7 @@ config BOARDINFO
|
|||
default "Ka-Ro tx51" if MACH_TX51
|
||||
default "Freescale i.MX6q armadillo2" if MACH_MX6Q_ARM2
|
||||
default "ConnectCore i.MX51" if MACH_CCMX51
|
||||
default "Sabre Lite" if MACH_SABRELITE
|
||||
|
||||
choice
|
||||
prompt "Select boot mode"
|
||||
|
|
@ -475,6 +477,9 @@ choice
|
|||
config MACH_MX6Q_ARM2
|
||||
bool "Freescale i.MX6q Armadillo2"
|
||||
|
||||
config MACH_SABRELITE
|
||||
bool "Freescale i.MX6 Sabre Lite"
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue