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wdenk 2002-04-01 14:29:03 +00:00
parent a6b6b68640
commit e85390dc1d
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46
board/esd/adciop/Makefile Normal file
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#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o ../common/pci.o
$(LIB): $(OBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

46
board/esd/dasa_sim/Makefile Normal file
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#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
$(LIB): $(OBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

44
board/evb64260/Makefile Normal file
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#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
SOBJS = misc.o
OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \
eth.o eth_addrtbl.o mpsc.o i2c.o \
sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $^
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

40
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#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o m48t59y.o pci.o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

41
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#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
SOBJS =
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $^
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

45
board/pcippc2/Makefile Normal file
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#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \
fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o
AOBJS =
OBJS = $(COBJS) $(AOBJS)
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
#########################################################################
.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
sinclude .depend
#########################################################################

51
board/pcippc2/cpc710_pci.h Normal file
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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CPC710_PCI_H_
#define _CPC710_PCI_H_
#define PCI_MEMORY_PHYS 0x00000000
#define PCI_MEMORY_BUS 0x80000000
#define PCI_MEMORY_MAXSIZE 0x20000000
#define BRIDGE_CPCI_PHYS 0xff500000
#define BRIDGE_CPCI_MEM_SIZE 0x08000000
#define BRIDGE_CPCI_MEM_PHYS 0xf0000000
#define BRIDGE_CPCI_MEM_BUS 0x00000000
#define BRIDGE_CPCI_IO_SIZE 0x02000000
#define BRIDGE_CPCI_IO_PHYS 0xfc000000
#define BRIDGE_CPCI_IO_BUS 0x00000000
#define BRIDGE_LOCAL_PHYS 0xff400000
#define BRIDGE_LOCAL_MEM_SIZE 0x04000000
#define BRIDGE_LOCAL_MEM_PHYS 0xf8000000
#define BRIDGE_LOCAL_MEM_BUS 0x40000000
#define BRIDGE_LOCAL_IO_SIZE 0x01000000
#define BRIDGE_LOCAL_IO_PHYS 0xfe000000
#define BRIDGE_LOCAL_IO_BUS 0x04000000
#define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x)
#define PCI_LATENCY_TIMER_VAL 0xff
#endif

40
board/sandpoint/Makefile Normal file
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#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

44
cpu/mpc824x/Makefile Normal file
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#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.S drivers/i2c/i2c2.o
OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \
drivers/epic/epic1.o drivers/i2c/i2c1.o pci.o
all: .depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS) drivers/i2c/i2c2.o
#########################################################################
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

56
drivers/ns16550.c Normal file
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/*
* COM1 NS16550 support
* originally from linux source (arch/ppc/boot/ns16550.c)
* modified to use CFG_ISA_MEM and new defines
*/
#include <config.h>
#ifdef CFG_NS16550
#include <ns16550.h>
#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */
void NS16550_init (NS16550_t com_port, int baud_divisor)
{
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE | LCRVAL;
com_port->dll = baud_divisor & 0xff;
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCRVAL;
com_port->mcr = MCRVAL;
com_port->fcr = FCRVAL;
}
void NS16550_reinit (NS16550_t com_port, int baud_divisor)
{
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE;
com_port->dll = baud_divisor & 0xff;
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCRVAL;
com_port->mcr = MCRVAL;
com_port->fcr = FCRVAL;
}
void NS16550_putc (NS16550_t com_port, char c)
{
while ((com_port->lsr & LSR_THRE) == 0);
com_port->thr = c;
}
char NS16550_getc (NS16550_t com_port)
{
while ((com_port->lsr & LSR_DR) == 0);
return (com_port->rbr);
}
int NS16550_tstc (NS16550_t com_port)
{
return ((com_port->lsr & LSR_DR) != 0);
}
#endif

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#ifndef _405GP_PCI_H
#define _405GP_PCI_H
/*----------------------------------------------------------------------------+
| 405GP PCI core memory map defines.
+----------------------------------------------------------------------------*/
#define MIN_PCI_MEMADDR1 0x80000000
#define MIN_PCI_MEMADDR2 0x00000000
#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */
#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */
#define MAX_PCI_DEVICES 32
/*----------------------------------------------------------------------------+
| Defines for the 405GP PCI Config address and data registers followed by
| defines for the standard PCI device configuration header.
+----------------------------------------------------------------------------*/
#define PCICFGADR 0xEEC00000
#define PCICFGDATA 0xEEC00004
#define PCIBUSNUM 0x40 /* 405GP specific parameters */
#define PCISUBBUSNUM 0x41
#define PCIDISCOUNT 0x42
#define PCIBRDGOPT1 0x4A
#define PCIBRDGOPT2 0x60
/*----------------------------------------------------------------------------+
| Defines for 405GP PCI Master local configuration regs.
+----------------------------------------------------------------------------*/
#define PMM0LA 0xEF400000
#define PMM0MA 0xEF400004
#define PMM0PCILA 0xEF400008
#define PMM0PCIHA 0xEF40000C
#define PMM1LA 0xEF400010
#define PMM1MA 0xEF400014
#define PMM1PCILA 0xEF400018
#define PMM1PCIHA 0xEF40001C
#define PMM2LA 0xEF400020
#define PMM2MA 0xEF400024
#define PMM2PCILA 0xEF400028
#define PMM2PCIHA 0xEF40002C
/*----------------------------------------------------------------------------+
| Defines for 405GP PCI Target local configuration regs.
+----------------------------------------------------------------------------*/
#define PTM1MS 0xEF400030
#define PTM1LA 0xEF400034
#define PTM2MS 0xEF400038
#define PTM2LA 0xEF40003C
#define PCIDEVID_405GP 0x0
#endif

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/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _NS87308_H_
#define _NS87308_H_
#include <asm/pci_io.h>
/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
void initialise_ns87308(void);
/*
* The following struct represents the GPIO registers on the NS87308/NS97307
*/
struct GPIO
{
unsigned char dta1; /* 0 data port 1 */
unsigned char dir1; /* 1 direction port 1 */
unsigned char out1; /* 2 output type port 1 */
unsigned char puc1; /* 3 pull-up control port 1 */
unsigned char dta2; /* 4 data port 2 */
unsigned char dir2; /* 5 direction port 2 */
unsigned char out2; /* 6 output type port 2 */
unsigned char puc2; /* 7 pull-up control port 2 */
};
/*
* The following represents the power management registers on the NS87308/NS97307
*/
#define PWM_FER1 0 /* 0 function enable reg. 1 */
#define PWM_FER2 1 /* 1 function enable reg. 2 */
#define PWM_PMC1 2 /* 2 power mgmt. control 1 */
#define PWM_PMC2 3 /* 3 power mgmt. control 2 */
#define PWM_PMC3 4 /* 4 power mgmt. control 3 */
#define PWM_WDTO 5 /* 5 watchdog time-out */
#define PWM_WDCF 6 /* 6 watchdog config. */
#define PWM_WDST 7 /* 7 watchdog status */
/*PNP config registers:
* these depend on the stated of BADDR1 and BADDR0 on startup
* so there's three versions here with the last two digits indicating
* for which configuration their valid
* the 1st of the two digits indicates the state of BADDR1
* the 2st of the two digits indicates the state of BADDR0
*/
#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */
#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */
#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */
#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */
#if defined(CFG_NS87308_BADDR_0x)
#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_0x)
#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_0x)
#elif defined(CFG_NS87308_BADDR_10)
#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_10)
#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_10)
#elif defined(CFG_NS87308_BADDR_11)
#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_11)
#define IO_DATA (CFG_ISA_IO + IO_DATA_OFFSET_11)
#endif
/* PnP register definitions */
#define SET_RD_DATA_PORT 0x00
#define SERIAL_ISOLATION 0x01
#define CONFIG_CONTROL 0x02
#define WAKE_CSN 0x03
#define RES_DATA 0x04
#define STATUS 0x05
#define SET_CSN 0x06
#define LOGICAL_DEVICE 0x07
/*vendor defined values */
#define SID_REG 0x20
#define SUPOERIO_CONF1 0x21
#define SUPOERIO_CONF2 0x22
#define PGCS_INDEX 0x23
#define PGCS_DATA 0x24
/* values above 30 are different for each logical device
but I can't be arsed to enter them all. the ones here
are pretty consistent between all logical devices
feel free to correct the situation if you want.. ;)
*/
#define ACTIVATE 0x30
#define ACTIVATE_OFF 0x00
#define ACTIVATE_ON 0x01
#define BASE_ADDR_HIGH 0x60
#define BASE_ADDR_LOW 0x61
#define LUN_CONFIG_REG 0xF0
#define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
#define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
#define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
#define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
/* the logical devices*/
#define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/
#define LDEV_KBC2 0x01
#define LDEV_MOUSE 0x01
#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
#define LDEV_FDC 0x03 /*floppy disk controller*/
#define LDEV_PARP 0x04 /*Parallel port*/
#define LDEV_UART2 0x05
#define LDEV_UART1 0x06
#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
#define LDEV_POWRMAN 0x08 /*Power Managment*/
#define CFG_NS87308_KBC1 (1 << LDEV_KBC1)
#define CFG_NS87308_KBC2 (1 << LDEV_KBC2)
#define CFG_NS87308_MOUSE (1 << LDEV_MOUSE)
#define CFG_NS87308_RTC_APC (1 << LDEV_RTC_APC)
#define CFG_NS87308_FDC (1 << LDEV_FDC)
#define CFG_NS87308_PARP (1 << LDEV_PARP)
#define CFG_NS87308_UART2 (1 << LDEV_UART2)
#define CFG_NS87308_UART1 (1 << LDEV_UART1)
#define CFG_NS87308_GPIO (1 << LDEV_GPIO)
#define CFG_NS87308_POWRMAN (1 << LDEV_POWRMAN)
/*some functions and macro's for doing configuration */
static inline void read_pnp_config(unsigned char index, unsigned char *data)
{
pci_writeb(index,IO_INDEX);
pci_readb(IO_DATA, *data);
}
static inline void write_pnp_config(unsigned char index, unsigned char data)
{
pci_writeb(index,IO_INDEX);
pci_writeb(data, IO_DATA);
}
static inline void pnp_set_device(unsigned char dev)
{
write_pnp_config(LOGICAL_DEVICE, dev);
}
static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
{
pci_writeb(index, CFG_ISA_IO + base);
eieio();
pci_writeb(data, CFG_ISA_IO + base + 1);
}
/*void write_pnp_config(unsigned char index, unsigned char data);
void pnp_set_device(unsigned char dev);
*/
#define PNP_SET_DEVICE_BASE(dev,base) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
write_pnp_config(ACTIVATE, ACTIVATE_ON);
#define PNP_ACTIVATE_DEVICE(dev) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_ON);
#define PNP_DEACTIVATE_DEVICE(dev) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_OFF);
static inline void write_pgcs_config(unsigned char index, unsigned char data)
{
write_pnp_config(PGCS_INDEX, index);
write_pnp_config(PGCS_DATA, data);
}
/* these macrose configure the 3 CS lines
on the sandpoint board these controll NVRAM
CS0 is connected to NVRAMCS
CS1 is connected to NVRAMAS0
CS2 is connected to NVRAMAS1
*/
#define PGCS_CS_ASSERT_ON_WRITE 0x10
#define PGCS_CS_ASSERT_ON_READ 0x20
#define PNP_PGCS_CSLINE_BASE(cs, base) \
write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
#define PNP_PGCS_CSLINE_CONF(cs, conf) \
write_pgcs_config(((cs) << 2) + 2, (conf) );
/* The following sections are for 87308 extensions to the standard compoents it emulates */
/* extensions to 16550*/
#define MCR_MDSL_MSK 0xe0 /*mode select mask*/
#define MCR_MDSL_UART 0x00 /*uart, default*/
#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
#define MCR_MDSL_SIR 0x03 /*SIR*/
#define MCR_MDSL_CIR 0x06 /*Consumer IR*/
#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */
#define FCR_TXFTH1 0x20 /* for interrupt trigger */
/*
* Default NS87308 configuration
*/
#ifndef CFG_NS87308_KBC1_BASE
#define CFG_NS87308_KBC1_BASE 0x0060
#endif
#ifndef CFG_NS87308_RTC_BASE
#define CFG_NS87308_RTC_BASE 0x0070
#endif
#ifndef CFG_NS87308_FDC_BASE
#define CFG_NS87308_FDC_BASE 0x03F0
#endif
#ifndef CFG_NS87308_LPT_BASE
#define CFG_NS87308_LPT_BASE 0x0278
#endif
#ifndef CFG_NS87308_UART1_BASE
#define CFG_NS87308_UART1_BASE 0x03F8
#endif
#ifndef CFG_NS87308_UART2_BASE
#define CFG_NS87308_UART2_BASE 0x02F8
#endif
#endif /*_NS87308_H_*/

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/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _SCSI_H
#define _SCSI_H
typedef struct SCSI_cmd_block{
unsigned char cmd[16]; /* command */
unsigned char sense_buf[64]; /* for request sense */
unsigned char status; /* SCSI Status */
unsigned char target; /* Target ID */
unsigned char lun; /* Target LUN */
unsigned char cmdlen; /* command len */
unsigned long datalen; /* Total data length */
unsigned char * pdata; /* pointer to data */
unsigned char msgout[12]; /* Messge out buffer (NOT USED) */
unsigned char msgin[12]; /* Message in buffer */
unsigned char sensecmdlen; /* Sense command len */
unsigned long sensedatalen; /* Sense data len */
unsigned char sensecmd[6]; /* Sense command */
unsigned long contr_stat; /* Controller Status */
unsigned long trans_bytes; /* tranfered bytes */
unsigned int priv;
}ccb;
/*-----------------------------------------------------------
**
** SCSI constants.
**
**-----------------------------------------------------------
*/
/*
** Messages
*/
#define M_COMPLETE (0x00)
#define M_EXTENDED (0x01)
#define M_SAVE_DP (0x02)
#define M_RESTORE_DP (0x03)
#define M_DISCONNECT (0x04)
#define M_ID_ERROR (0x05)
#define M_ABORT (0x06)
#define M_REJECT (0x07)
#define M_NOOP (0x08)
#define M_PARITY (0x09)
#define M_LCOMPLETE (0x0a)
#define M_FCOMPLETE (0x0b)
#define M_RESET (0x0c)
#define M_ABORT_TAG (0x0d)
#define M_CLEAR_QUEUE (0x0e)
#define M_INIT_REC (0x0f)
#define M_REL_REC (0x10)
#define M_TERMINATE (0x11)
#define M_SIMPLE_TAG (0x20)
#define M_HEAD_TAG (0x21)
#define M_ORDERED_TAG (0x22)
#define M_IGN_RESIDUE (0x23)
#define M_IDENTIFY (0x80)
#define M_X_MODIFY_DP (0x00)
#define M_X_SYNC_REQ (0x01)
#define M_X_WIDE_REQ (0x03)
#define M_X_PPR_REQ (0x04)
/*
** Status
*/
#define S_GOOD (0x00)
#define S_CHECK_COND (0x02)
#define S_COND_MET (0x04)
#define S_BUSY (0x08)
#define S_INT (0x10)
#define S_INT_COND_MET (0x14)
#define S_CONFLICT (0x18)
#define S_TERMINATED (0x20)
#define S_QUEUE_FULL (0x28)
#define S_ILLEGAL (0xff)
#define S_SENSE (0x80)
/*
* Sense_keys
*/
#define SENSE_NO_SENSE 0x0
#define SENSE_RECOVERED_ERROR 0x1
#define SENSE_NOT_READY 0x2
#define SENSE_MEDIUM_ERROR 0x3
#define SENSE_HARDWARE_ERROR 0x4
#define SENSE_ILLEGAL_REQUEST 0x5
#define SENSE_UNIT_ATTENTION 0x6
#define SENSE_DATA_PROTECT 0x7
#define SENSE_BLANK_CHECK 0x8
#define SENSE_VENDOR_SPECIFIC 0x9
#define SENSE_COPY_ABORTED 0xA
#define SENSE_ABORTED_COMMAND 0xB
#define SENSE_VOLUME_OVERFLOW 0xD
#define SENSE_MISCOMPARE 0xE
#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */
#define SCSI_COMPARE 0x39 /* Compare (O) */
#define SCSI_COPY 0x18 /* Copy (O) */
#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */
#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */
#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */
#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */
#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */
#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */
#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */
#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */
#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */
#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */
#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */
#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */
#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */
/***************************************************************************
* %%% Commands Unique to Direct Access Devices %%%
***************************************************************************/
#define SCSI_COMPARE 0x39 /* Compare (O) */
#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */
#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */
#define SCSI_PREFETCH 0x34 /* Prefetch (O) */
#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */
#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */
#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */
#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */
#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */
#define SCSI_READ_LONG 0x3E /* Read Long (O) */
#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */
#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */
#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */
#define SCSI_REZERO 0x01 /* Rezero Unit (O) */
#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */
#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */
#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */
#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */
#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */
#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */
#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */
#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */
#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */
#define SCSI_VERIFY 0x2F /* Verify (O) */
#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */
#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */
#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */
#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */
#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
/****************************************************************************
* decleration of functions which have to reside in the LowLevel Part Driver
*/
void scsi_print_error(ccb *pccb);
int scsi_exec(ccb *pccb);
void scsi_bus_reset(void);
void scsi_low_level_init(int busdevfunc);
/***************************************************************************
* functions residing inside cmd_scsi.c
*/
void scsi_init(void);
#define SCSI_IDENTIFY 0xC0 /* not used */
/* Hardware errors */
#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */
#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */
#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */
#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */
#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif /* _SCSI_H */

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/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
* Most of these definitions are derived from
* linux/drivers/scsi/sym53c8xx_defs.h
*
*/
#ifndef _SYM53C8XX_DEFS_H
#define _SYM53C8XX_DEFS_H
#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
#define SCNTL1 0x01 /* no reset */
#define ISCON 0x10 /* connected to scsi */
#define CRST 0x08 /* force reset */
#define IARB 0x02 /* immediate arbitration */
#define SCNTL2 0x02 /* no disconnect expected */
#define SDU 0x80 /* cmd: disconnect will raise error */
#define CHM 0x40 /* sta: chained mode */
#define WSS 0x08 /* sta: wide scsi send [W]*/
#define WSR 0x01 /* sta: wide scsi received [W]*/
#define SCNTL3 0x03 /* cnf system clock dependent */
#define EWS 0x08 /* cmd: enable wide scsi [W]*/
#define ULTRA 0x80 /* cmd: ULTRA enable */
/* bits 0-2, 7 rsvd for C1010 */
#define SCID 0x04 /* cnf host adapter scsi address */
#define RRE 0x40 /* r/w:e enable response to resel. */
#define SRE 0x20 /* r/w:e enable response to select */
#define SXFER 0x05 /* ### Sync speed and count */
/* bits 6-7 rsvd for C1010 */
#define SDID 0x06 /* ### Destination-ID */
#define GPREG 0x07 /* ??? IO-Pins */
#define SFBR 0x08 /* ### First byte in phase */
#define SOCL 0x09
#define CREQ 0x80 /* r/w: SCSI-REQ */
#define CACK 0x40 /* r/w: SCSI-ACK */
#define CBSY 0x20 /* r/w: SCSI-BSY */
#define CSEL 0x10 /* r/w: SCSI-SEL */
#define CATN 0x08 /* r/w: SCSI-ATN */
#define CMSG 0x04 /* r/w: SCSI-MSG */
#define CC_D 0x02 /* r/w: SCSI-C_D */
#define CI_O 0x01 /* r/w: SCSI-I_O */
#define SSID 0x0a
#define SBCL 0x0b
#define DSTAT 0x0c
#define DFE 0x80 /* sta: dma fifo empty */
#define MDPE 0x40 /* int: master data parity error */
#define BF 0x20 /* int: script: bus fault */
#define ABRT 0x10 /* int: script: command aborted */
#define SSI 0x08 /* int: script: single step */
#define SIR 0x04 /* int: script: interrupt instruct. */
#define IID 0x01 /* int: script: illegal instruct. */
#define SSTAT0 0x0d
#define ILF 0x80 /* sta: data in SIDL register lsb */
#define ORF 0x40 /* sta: data in SODR register lsb */
#define OLF 0x20 /* sta: data in SODL register lsb */
#define AIP 0x10 /* sta: arbitration in progress */
#define LOA 0x08 /* sta: arbitration lost */
#define WOA 0x04 /* sta: arbitration won */
#define IRST 0x02 /* sta: scsi reset signal */
#define SDP 0x01 /* sta: scsi parity signal */
#define SSTAT1 0x0e
#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
#define SSTAT2 0x0f
#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
#define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
#define LDSC 0x02 /* sta: disconnect & reconnect */
#define DSA 0x10 /* --> Base page */
#define DSA1 0x11
#define DSA2 0x12
#define DSA3 0x13
#define ISTAT 0x14 /* --> Main Command and status */
#define CABRT 0x80 /* cmd: abort current operation */
#define SRST 0x40 /* mod: reset chip */
#define SIGP 0x20 /* r/w: message from host to ncr */
#define SEM 0x10 /* r/w: message between host + ncr */
#define CON 0x08 /* sta: connected to scsi */
#define INTF 0x04 /* sta: int on the fly (reset by wr)*/
#define SIP 0x02 /* sta: scsi-interrupt */
#define DIP 0x01 /* sta: host/script interrupt */
#define CTEST0 0x18
#define CTEST1 0x19
#define CTEST2 0x1a
#define CSIGP 0x40
/* bits 0-2,7 rsvd for C1010 */
#define CTEST3 0x1b
#define FLF 0x08 /* cmd: flush dma fifo */
#define CLF 0x04 /* cmd: clear dma fifo */
#define FM 0x02 /* mod: fetch pin mode */
#define WRIE 0x01 /* mod: write and invalidate enable */
/* bits 4-7 rsvd for C1010 */
#define DFIFO 0x20
#define CTEST4 0x21
#define BDIS 0x80 /* mod: burst disable */
#define MPEE 0x08 /* mod: master parity error enable */
#define CTEST5 0x22
#define DFS 0x20 /* mod: dma fifo size */
/* bits 0-1, 3-7 rsvd for C1010 */
#define CTEST6 0x23
#define DBC 0x24 /* ### Byte count and command */
#define DNAD 0x28 /* ### Next command register */
#define DSP 0x2c /* --> Script Pointer */
#define DSPS 0x30 /* --> Script pointer save/opcode#2 */
#define SCRATCHA 0x34 /* Temporary register a */
#define SCRATCHA1 0x35
#define SCRATCHA2 0x36
#define SCRATCHA3 0x37
#define DMODE 0x38
#define BL_2 0x80 /* mod: burst length shift value +2 */
#define BL_1 0x40 /* mod: burst length shift value +1 */
#define ERL 0x08 /* mod: enable read line */
#define ERMP 0x04 /* mod: enable read multiple */
#define BOF 0x02 /* mod: burst op code fetch */
#define MAN 0x01 /* mod: manual start */
#define DIEN 0x39
#define SBR 0x3a
#define DCNTL 0x3b /* --> Script execution control */
#define CLSE 0x80 /* mod: cache line size enable */
#define PFF 0x40 /* cmd: pre-fetch flush */
#define PFEN 0x20 /* mod: pre-fetch enable */
#define SSM 0x10 /* mod: single step mode */
#define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
#define STD 0x04 /* cmd: start dma mode */
#define IRQD 0x02 /* mod: irq disable */
#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
/* bits 0-1 rsvd for C1010 */
#define ADDER 0x3c
#define SIEN 0x40 /* -->: interrupt enable */
#define SIST 0x42 /* <--: interrupt status */
#define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
#define STO 0x0400/* sta: timeout (select) */
#define GEN 0x0200/* sta: timeout (general) */
#define HTH 0x0100/* sta: timeout (handshake) */
#define MA 0x80 /* sta: phase mismatch */
#define CMP 0x40 /* sta: arbitration complete */
#define SEL 0x20 /* sta: selected by another device */
#define RSL 0x10 /* sta: reselected by another device*/
#define SGE 0x08 /* sta: gross error (over/underflow)*/
#define UDC 0x04 /* sta: unexpected disconnect */
#define RST 0x02 /* sta: scsi bus reset detected */
#define PAR 0x01 /* sta: scsi parity error */
#define SLPAR 0x44
#define SWIDE 0x45
#define MACNTL 0x46
#define GPCNTL 0x47
#define STIME0 0x48 /* cmd: timeout for select&handshake*/
#define STIME1 0x49 /* cmd: timeout user defined */
#define RESPID 0x4a /* sta: Reselect-IDs */
#define STEST0 0x4c
#define STEST1 0x4d
#define SCLK 0x80 /* Use the PCI clock as SCSI clock */
#define DBLEN 0x08 /* clock doubler running */
#define DBLSEL 0x04 /* clock doubler selected */
#define STEST2 0x4e
#define ROF 0x40 /* reset scsi offset (after gross error!) */
#define EXT 0x02 /* extended filtering */
#define STEST3 0x4f
#define TE 0x80 /* c: tolerAnt enable */
#define HSC 0x20 /* c: Halt SCSI Clock */
#define CSF 0x02 /* c: clear scsi fifo */
#define SIDL 0x50 /* Lowlevel: latched from scsi data */
#define STEST4 0x52
#define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
#define SMODE_HVD 0x40 /* High Voltage Differential */
#define SMODE_SE 0x80 /* Single Ended */
#define SMODE_LVD 0xc0 /* Low Voltage Differential */
#define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
/* bits 0-5 rsvd for C1010 */
#define SODL 0x54 /* Lowlevel: data out to scsi data */
#define SBDL 0x58 /* Lowlevel: data from scsi data */
/*-----------------------------------------------------------
**
** Utility macros for the script.
**
**-----------------------------------------------------------
*/
#define REG(r) (r)
/*-----------------------------------------------------------
**
** SCSI phases
**
** DT phases illegal for ncr driver.
**
**-----------------------------------------------------------
*/
#define SCR_DATA_OUT 0x00000000
#define SCR_DATA_IN 0x01000000
#define SCR_COMMAND 0x02000000
#define SCR_STATUS 0x03000000
#define SCR_DT_DATA_OUT 0x04000000
#define SCR_DT_DATA_IN 0x05000000
#define SCR_MSG_OUT 0x06000000
#define SCR_MSG_IN 0x07000000
#define SCR_ILG_OUT 0x04000000
#define SCR_ILG_IN 0x05000000
/*-----------------------------------------------------------
**
** Data transfer via SCSI.
**
**-----------------------------------------------------------
**
** MOVE_ABS (LEN)
** <<start address>>
**
** MOVE_IND (LEN)
** <<dnad_offset>>
**
** MOVE_TBL
** <<dnad_offset>>
**
**-----------------------------------------------------------
*/
#define OPC_MOVE 0x08000000
#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
#define SCR_CHMOV_TBL (0x10000000)
/*-----------------------------------------------------------
**
** Selection
**
**-----------------------------------------------------------
**
** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
** <<alternate_address>>
**
** SEL_TBL | << dnad_offset>> [ | REL_JMP]
** <<alternate_address>>
**
**-----------------------------------------------------------
*/
#define SCR_SEL_ABS 0x40000000
#define SCR_SEL_ABS_ATN 0x41000000
#define SCR_SEL_TBL 0x42000000
#define SCR_SEL_TBL_ATN 0x43000000
#define SCR_JMP_REL 0x04000000
#define SCR_ID(id) (((unsigned long)(id)) << 16)
/*-----------------------------------------------------------
**
** Waiting for Disconnect or Reselect
**
**-----------------------------------------------------------
**
** WAIT_DISC
** dummy: <<alternate_address>>
**
** WAIT_RESEL
** <<alternate_address>>
**
**-----------------------------------------------------------
*/
#define SCR_WAIT_DISC 0x48000000
#define SCR_WAIT_RESEL 0x50000000
/*-----------------------------------------------------------
**
** Bit Set / Reset
**
**-----------------------------------------------------------
**
** SET (flags {|.. })
**
** CLR (flags {|.. })
**
**-----------------------------------------------------------
*/
#define SCR_SET(f) (0x58000000 | (f))
#define SCR_CLR(f) (0x60000000 | (f))
#define SCR_CARRY 0x00000400
#define SCR_TRG 0x00000200
#define SCR_ACK 0x00000040
#define SCR_ATN 0x00000008
/*-----------------------------------------------------------
**
** Memory to memory move
**
**-----------------------------------------------------------
**
** COPY (bytecount)
** << source_address >>
** << destination_address >>
**
** SCR_COPY sets the NO FLUSH option by default.
** SCR_COPY_F does not set this option.
**
** For chips which do not support this option,
** ncr_copy_and_bind() will remove this bit.
**-----------------------------------------------------------
*/
#define SCR_NO_FLUSH 0x01000000
#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
#define SCR_COPY_F(n) (0xc0000000 | (n))
/*-----------------------------------------------------------
**
** Register move and binary operations
**
**-----------------------------------------------------------
**
** SFBR_REG (reg, op, data) reg = SFBR op data
** << 0 >>
**
** REG_SFBR (reg, op, data) SFBR = reg op data
** << 0 >>
**
** REG_REG (reg, op, data) reg = reg op data
** << 0 >>
**
**-----------------------------------------------------------
** On 810A, 860, 825A, 875, 895 and 896 chips the content
** of SFBR register can be used as data (SCR_SFBR_DATA).
** The 896 has additionnal IO registers starting at
** offset 0x80. Bit 7 of register offset is stored in
** bit 7 of the SCRIPTS instruction first DWORD.
**-----------------------------------------------------------
*/
#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
#define SCR_SFBR_REG(reg,op,data) \
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
#define SCR_REG_SFBR(reg,op,data) \
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
#define SCR_REG_REG(reg,op,data) \
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
#define SCR_LOAD 0x00000000
#define SCR_SHL 0x01000000
#define SCR_OR 0x02000000
#define SCR_XOR 0x03000000
#define SCR_AND 0x04000000
#define SCR_SHR 0x05000000
#define SCR_ADD 0x06000000
#define SCR_ADDC 0x07000000
#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
/*-----------------------------------------------------------
**
** FROM_REG (reg) SFBR = reg
** << 0 >>
**
** TO_REG (reg) reg = SFBR
** << 0 >>
**
** LOAD_REG (reg, data) reg = <data>
** << 0 >>
**
** LOAD_SFBR(data) SFBR = <data>
** << 0 >>
**
**-----------------------------------------------------------
*/
#define SCR_FROM_REG(reg) \
SCR_REG_SFBR(reg,SCR_OR,0)
#define SCR_TO_REG(reg) \
SCR_SFBR_REG(reg,SCR_OR,0)
#define SCR_LOAD_REG(reg,data) \
SCR_REG_REG(reg,SCR_LOAD,data)
#define SCR_LOAD_SFBR(data) \
(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
/*-----------------------------------------------------------
**
** LOAD from memory to register.
** STORE from register to memory.
**
** Only supported by 810A, 860, 825A, 875, 895 and 896.
**
**-----------------------------------------------------------
**
** LOAD_ABS (LEN)
** <<start address>>
**
** LOAD_REL (LEN) (DSA relative)
** <<dsa_offset>>
**
**-----------------------------------------------------------
*/
#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
#define SCR_NO_FLUSH2 0x02000000
#define SCR_DSA_REL2 0x10000000
#define SCR_LOAD_R(reg, how, n) \
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
#define SCR_STORE_R(reg, how, n) \
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
/*-----------------------------------------------------------
**
** Waiting for Disconnect or Reselect
**
**-----------------------------------------------------------
**
** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
** <<address>>
**
** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
** <<distance>>
**
** CALL [ | IFTRUE/IFFALSE ( ... ) ]
** <<address>>
**
** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
** <<distance>>
**
** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
** <<dummy>>
**
** INT [ | IFTRUE/IFFALSE ( ... ) ]
** <<ident>>
**
** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
** <<ident>>
**
** Conditions:
** WHEN (phase)
** IF (phase)
** CARRYSET
** DATA (data, mask)
**
**-----------------------------------------------------------
*/
#define SCR_NO_OP 0x80000000
#define SCR_JUMP 0x80080000
#define SCR_JUMP64 0x80480000
#define SCR_JUMPR 0x80880000
#define SCR_CALL 0x88080000
#define SCR_CALLR 0x88880000
#define SCR_RETURN 0x90080000
#define SCR_INT 0x98080000
#define SCR_INT_FLY 0x98180000
#define IFFALSE(arg) (0x00080000 | (arg))
#define IFTRUE(arg) (0x00000000 | (arg))
#define WHEN(phase) (0x00030000 | (phase))
#define IF(phase) (0x00020000 | (phase))
#define DATA(D) (0x00040000 | ((D) & 0xff))
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
#define CARRYSET (0x00200000)
#define SIR_COMPLETE 0x10000000
/* script errors */
#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
#define SIR_CMD_OUT_ILL_PH 0x00000002
#define SIR_STATUS_ILL_PH 0x00000003
#define SIR_MSG_RECEIVED 0x00000004
#define SIR_DATA_IN_ERR 0x00000005
#define SIR_DATA_OUT_ERR 0x00000006
#define SIR_SCRIPT_ERROR 0x00000007
#define SIR_MSG_OUT_NO_CMD 0x00000008
#define SIR_MSG_OVER7 0x00000009
/* Fly interrupt */
#define INT_ON_FY 0x00000080
/* Hardware errors are defined in scsi.h */
#define SCSI_IDENTIFY 0xC0
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif