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ARM i.MX5: move pll setup defines to header file 

The pll setup function is exported, so it makes sense to export
the convenience wrappers for specific frequencies aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2012-11-27 09:07:08 +01:00
parent a32d081d6d
commit e8fa8b5ccf
3 changed files with 22 additions and 25 deletions
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17
arch/arm/mach-imx/imx51.c
View File

@ -94,13 +94,6 @@ postcore_initcall(imx51_init);
* power up.
*/
#define setup_pll_800(base) imx5_setup_pll((base), 800, (( 8 << 4) + ((1 - 1) << 0)), ( 3 - 1), 1)
#define setup_pll_665(base) imx5_setup_pll((base), 665, (( 6 << 4) + ((1 - 1) << 0)), (96 - 1), 89)
#define setup_pll_600(base) imx5_setup_pll((base), 600, (( 6 << 4) + ((1 - 1) << 0)), ( 4 - 1), 1)
#define setup_pll_400(base) imx5_setup_pll((base), 400, (( 8 << 4) + ((2 - 1) << 0)), ( 3 - 1), 1)
#define setup_pll_455(base) imx5_setup_pll((base), 455, (( 9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
#define setup_pll_216(base) imx5_setup_pll((base), 216, (( 6 << 4) + ((3 - 1) << 0)), ( 4 - 1), 3)
void imx51_init_lowlevel(unsigned int cpufreq_mhz)
{
void __iomem *ccm = (void __iomem *)MX51_CCM_BASE_ADDR;
@ -137,27 +130,27 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz)
switch (cpufreq_mhz) {
case 600:
setup_pll_600((void __iomem *)MX51_PLL1_BASE_ADDR);
imx5_setup_pll_600((void __iomem *)MX51_PLL1_BASE_ADDR);
break;
default:
/* Default maximum 800MHz */
setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR);
imx5_setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR);
break;
}
setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR);
imx5_setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR);
/* Switch peripheral to PLL 3 */
writel(0x000010C0, ccm + MX5_CCM_CBCMR);
writel(0x13239145, ccm + MX5_CCM_CBCDR);
setup_pll_665((void __iomem *)MX51_PLL2_BASE_ADDR);
imx5_setup_pll_665((void __iomem *)MX51_PLL2_BASE_ADDR);
/* Switch peripheral to PLL2 */
writel(0x19239145, ccm + MX5_CCM_CBCDR);
writel(0x000020C0, ccm + MX5_CCM_CBCMR);
setup_pll_216((void __iomem *)MX51_PLL3_BASE_ADDR);
imx51_setup_pll_216((void __iomem *)MX51_PLL3_BASE_ADDR);
/* Set the platform clock dividers */
writel(0x00000124, MX51_ARM_BASE_ADDR + 0x14);

18
arch/arm/mach-imx/imx53.c
View File

@ -75,12 +75,6 @@ static int imx53_init(void)
}
postcore_initcall(imx53_init);
#define setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
#define setup_pll_800(base) imx5_setup_pll((base), 800, ((8 << 4) + ((1 - 1) << 0)), (3 - 1), 1)
#define setup_pll_400(base) imx5_setup_pll((base), 400, ((8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
#define setup_pll_455(base) imx5_setup_pll((base), 455, ((9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
#define setup_pll_216(base) imx5_setup_pll((base), 216, ((8 << 4) + ((2 - 1) << 0)), (1 - 1), 1)
void imx53_init_lowlevel(unsigned int cpufreq_mhz)
{
void __iomem *ccm = (void __iomem *)MX53_CCM_BASE_ADDR;
@ -113,11 +107,11 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz)
writel(0x4, ccm + MX5_CCM_CCSR);
if (cpufreq_mhz == 1000)
setup_pll_1000((void __iomem *)MX53_PLL1_BASE_ADDR);
imx5_setup_pll_1000((void __iomem *)MX53_PLL1_BASE_ADDR);
else
setup_pll_800((void __iomem *)MX53_PLL1_BASE_ADDR);
imx5_setup_pll_800((void __iomem *)MX53_PLL1_BASE_ADDR);
setup_pll_400((void __iomem *)MX53_PLL3_BASE_ADDR);
imx5_setup_pll_400((void __iomem *)MX53_PLL3_BASE_ADDR);
/* Switch peripheral to PLL3 */
writel(0x00015154, ccm + MX5_CCM_CBCMR);
@ -126,7 +120,7 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz)
/* make sure change is effective */
while (readl(ccm + MX5_CCM_CDHIPR));
setup_pll_400((void __iomem *)MX53_PLL2_BASE_ADDR);
imx5_setup_pll_400((void __iomem *)MX53_PLL2_BASE_ADDR);
/* Switch peripheral to PLL2 */
r = 0x00808145 |
@ -152,8 +146,8 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz)
/* make sure change is effective */
while (readl(ccm + MX5_CCM_CDHIPR));
setup_pll_216((void __iomem *)MX53_PLL3_BASE_ADDR);
setup_pll_455((void __iomem *)MX53_PLL4_BASE_ADDR);
imx53_setup_pll_216((void __iomem *)MX53_PLL3_BASE_ADDR);
imx5_setup_pll_455((void __iomem *)MX53_PLL4_BASE_ADDR);
/* Set the platform clock dividers */
writel(0x00000124, MX53_ARM_BASE_ADDR + 0x14);

12
arch/arm/mach-imx/include/mach/imx5.h
View File

@ -3,7 +3,17 @@
void imx51_init_lowlevel(unsigned int cpufreq_mhz);
void imx53_init_lowlevel(unsigned int cpufreq_mhz);
void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn);
void imx5_init_lowlevel(void);
void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn);
#define imx5_setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
#define imx5_setup_pll_800(base) imx5_setup_pll((base), 800, (( 8 << 4) + ((1 - 1) << 0)), (3 - 1), 1)
#define imx5_setup_pll_665(base) imx5_setup_pll((base), 665, (( 6 << 4) + ((1 - 1) << 0)), (96 - 1), 89)
#define imx5_setup_pll_600(base) imx5_setup_pll((base), 600, (( 6 << 4) + ((1 - 1) << 0)), ( 4 - 1), 1)
#define imx5_setup_pll_455(base) imx5_setup_pll((base), 455, (( 9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
#define imx5_setup_pll_400(base) imx5_setup_pll((base), 400, (( 8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
#define imx53_setup_pll_216(base) imx5_setup_pll((base), 216, (( 8 << 4) + ((2 - 1) << 0)), (1 - 1), 1)
#define imx51_setup_pll_216(base) imx5_setup_pll((base), 216, (( 6 << 4) + ((3 - 1) << 0)), (4 - 1), 3)
#endif /* __MACH_MX53_H */