From e9557be0c13b2e11ee9c274edf7dd768fbc72ef5 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Sat, 10 Dec 2011 12:06:36 +0100 Subject: [PATCH] ARM cache-armv7: use thumb-2 instructions where necessary Copied from the Kernel Signed-off-by: Sascha Hauer --- arch/arm/cpu/cache-armv7.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 5b8491efc..f25dcfaa5 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -84,8 +84,12 @@ loop1: loop2: mov r9, r4 @ create working copy of max way size loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 +ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 +ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 +THUMB( lsl r6, r9, r5 ) +THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 +THUMB( lsl r6, r7, r2 ) +THUMB( orr r11, r11, r6 ) @ factor index number into r11 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way subs r9, r9, #1 @ decrement the way bge loop3