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barebox
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Merge branch 'for-next/compressed-prepare'

This commit is contained in:
Sascha Hauer 2012-08-01 17:49:27 +02:00
parent 363a134369 991e1caf2f
commit e986897cd0
56 changed files with 197 additions and 178 deletions
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12
arch/arm/Kconfig
View File

@ -1,15 +1,3 @@
#
#
#
config BOARD_LINKER_SCRIPT
bool
default n
config GENERIC_LINKER_SCRIPT
bool
default y
depends on !BOARD_LINKER_SCRIPT
config ARM
bool
select HAS_KALLSYMS

3
arch/arm/Makefile
View File

@ -208,7 +208,6 @@ endif
common-y += $(BOARD) $(MACH)
common-y += arch/arm/lib/ arch/arm/cpu/
lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/arm/lib/barebox.lds
lds-$(CONFIG_BOARD_LINKER_SCRIPT) := $(BOARD)/barebox.lds
lds-y := arch/arm/lib/barebox.lds
CLEAN_FILES += include/generated/mach-types.h arch/arm/lib/barebox.lds

3
arch/arm/boards/a9m2410/a9m2410.c
View File

@ -29,6 +29,7 @@
#include <init.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <asm-generic/sections.h>
#include <partition.h>
#include <nand.h>
#include <io.h>
@ -139,7 +140,7 @@ device_initcall(a9m2410_devices_init);
#ifdef CONFIG_S3C_NAND_BOOT
void __bare_init nand_boot(void)
{
s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
s3c24x0_nand_load_image(_text, 256 * 1024, 0);
}
#endif

3
arch/arm/boards/a9m2440/a9m2440.c
View File

@ -28,6 +28,7 @@
#include <driver.h>
#include <init.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <generated/mach-types.h>
#include <partition.h>
#include <nand.h>
@ -158,7 +159,7 @@ device_initcall(a9m2440_devices_init);
#ifdef CONFIG_S3C_NAND_BOOT
void __bare_init nand_boot(void)
{
s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
s3c24x0_nand_load_image(_text, 256 * 1024, 0);
}
#endif

7
arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
View File

@ -28,6 +28,7 @@
#include <environment.h>
#include <mach/imx-regs.h>
#include <asm/armlinux.h>
#include <asm/barebox-arm.h>
#include <asm-generic/sections.h>
#include <mach/gpio.h>
#include <io.h>
@ -49,8 +50,6 @@
#include <mach/devices-imx25.h>
#include <asm/barebox-arm-head.h>
extern void exception_vectors(void);
void __naked __flash_header_start go(void)
{
barebox_arm_head();
@ -72,7 +71,7 @@ struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
};
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE),
.app_code_jump_vector = DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
@ -286,7 +285,7 @@ console_initcall(eukrea_cpuimx25_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
}
#endif

4
arch/arm/boards/eukrea_cpuimx25/lowlevel.c
View File

@ -42,7 +42,7 @@ static void __bare_init __naked insdram(void)
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
@ -154,7 +154,7 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)

4
arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
View File

@ -31,6 +31,7 @@
#include <mach/gpio.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
#include <generated/mach-types.h>
#include <partition.h>
#include <fs.h>
@ -264,7 +265,8 @@ late_initcall(eukrea_cpuimx27_late_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

11
arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
View File

@ -1,4 +1,5 @@
#include <config.h>
#include <asm-generic/memory_layout.h>
#include <mach/imx-regs.h>
#define writel(val, reg) \
@ -107,7 +108,7 @@ board_init_lowlevel:
sdram_init
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
@ -119,7 +120,7 @@ board_init_lowlevel:
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =TEXT_BASE
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
@ -129,12 +130,8 @@ copy_loop:
ldr pc, =1f /* Jump to SDRAM */
1:
bl nand_boot /* Load barebox from NAND Flash */
ldr r1, =IMX_NFC_BASE - TEXT_BASE
sub r10, r10, r1 /* adjust return address from NFC SRAM */
b nand_boot /* Load barebox from NAND Flash */
/* to SDRAM */
#endif /* CONFIG_NAND_IMX_BOOT */
ret:

2
arch/arm/boards/eukrea_cpuimx35/flash_header.c
View File

@ -3,8 +3,6 @@
#include <mach/imx-regs.h>
#include <asm/barebox-arm-head.h>
extern void exception_vectors(void);
void __naked __flash_header_start go(void)
{
barebox_arm_head();

4
arch/arm/boards/eukrea_cpuimx35/lowlevel.c
View File

@ -53,7 +53,7 @@ static void __bare_init __naked insdram(void)
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
@ -163,7 +163,7 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)

8
arch/arm/boards/freescale-mx25-3-stack/3stack.c
View File

@ -28,6 +28,7 @@
#include <mach/imx-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
#include <mach/gpio.h>
#include <io.h>
#include <partition.h>
@ -45,8 +46,6 @@
#include <mach/devices-imx25.h>
#include <asm/barebox-arm-head.h>
extern void exception_vectors(void);
void __naked __flash_header_start go(void)
{
barebox_arm_head();
@ -95,7 +94,7 @@ struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
};
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE),
.app_code_jump_vector = DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
@ -296,7 +295,8 @@ console_initcall(imx25_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

11
arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
View File

@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
#include <asm-generic/memory_layout.h>
#include <mach/imx-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
@ -100,7 +101,7 @@ board_init_lowlevel:
str r3, [r0, #0x30]
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
@ -112,7 +113,7 @@ board_init_lowlevel:
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =TEXT_BASE
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
@ -122,11 +123,7 @@ copy_loop:
ldr pc, =1f /* Jump to SDRAM */
1:
bl nand_boot /* Load barebox from NAND Flash */
ldr r1, =IMX_NFC_BASE - TEXT_BASE
sub r10, r10, r1 /* adjust return address from NFC SRAM */
/* to SDRAM */
b nand_boot /* Load barebox from NAND Flash */
#endif /* CONFIG_NAND_IMX_BOOT */

4
arch/arm/boards/freescale-mx35-3-stack/3stack.c
View File

@ -38,6 +38,7 @@
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
#include <io.h>
#include <generated/mach-types.h>
@ -450,6 +451,7 @@ void __bare_init nand_boot(void)
* The driver is able to detect NAND's pagesize by CPU internal
* fuses or external pull ups. But not the blocksize...
*/
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

4
arch/arm/boards/freescale-mx35-3-stack/flash_header.c
View File

@ -3,8 +3,6 @@
#include <mach/imx-regs.h>
#include <asm/barebox-arm-head.h>
extern void exception_vectors(void);
void __naked __flash_header_start go(void)
{
barebox_arm_head();
@ -59,7 +57,7 @@ struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE),
.app_code_jump_vector = DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),

11
arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
View File

@ -25,6 +25,7 @@
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
#include <asm-generic/memory_layout.h>
#include "board-mx35_3stack.h"
#define CSD0_BASE_ADDR 0x80000000
@ -156,7 +157,7 @@ board_init_lowlevel:
str r3, [r0, #0x30]
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =TEXT_BASE - 4 /* Setup a temporary stack in SDRAM */
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */
@ -168,7 +169,7 @@ board_init_lowlevel:
bhs ret
/* Move ourselves out of NFC SRAM */
ldr r1, =TEXT_BASE
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
@ -178,11 +179,7 @@ copy_loop:
ldr pc, =1f /* Jump to SDRAM */
1:
bl nand_boot /* Load barebox from NAND Flash */
/* rebase the return address */
ldr r1, =IMX_NFC_BASE - TEXT_BASE
sub r10, r10, r1 /* adjust return address from NFC SRAM */
b nand_boot /* Load barebox from NAND Flash */
ret:
#endif /* CONFIG_NAND_IMX_BOOT */

2
arch/arm/boards/freescale-mx53-loco/flash_header.c
View File

@ -77,7 +77,7 @@ struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
};
#define APP_DEST CONFIG_TEXT_BASE
#define APP_DEST 0x70000000
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,

2
arch/arm/boards/freescale-mx53-smd/flash_header.c
View File

@ -77,7 +77,7 @@ struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
};
#define APP_DEST CONFIG_TEXT_BASE
#define APP_DEST 0x70000000
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,

5
arch/arm/boards/freescale-mx6-arm2/flash_header.c
View File

@ -15,12 +15,13 @@
#include <common.h>
#include <asm/byteorder.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx-flash-header.h>
#include <mach/imx6-regs.h>
void __naked __flash_header_start go(void)
{
__asm__ __volatile__("b exception_vectors\n");
barebox_arm_head();
}
#define DCD(a, v) { .addr = cpu_to_be32(a), .val = cpu_to_be32(v), }
@ -145,7 +146,7 @@ struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
};
#define APP_DEST CONFIG_TEXT_BASE
#define APP_DEST 0x10000000
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,

4
arch/arm/boards/guf-cupid/lowlevel.c
View File

@ -60,7 +60,7 @@ static void __bare_init __naked insdram(void)
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
@ -334,7 +334,7 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)

4
arch/arm/boards/guf-neso/lowlevel.c
View File

@ -44,7 +44,7 @@ static void __bare_init __naked insdram(void)
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
@ -105,7 +105,7 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)

4
arch/arm/boards/imx21ads/imx21ads.c
View File

@ -28,6 +28,7 @@
#include <mach/imx-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
#include <io.h>
#include <mach/gpio.h>
#include <partition.h>
@ -204,7 +205,8 @@ console_initcall(mx21ads_console_init);
void __bare_init nand_boot(void)
{
PCCR0 |= PCCR0_NFC_EN;
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

10
arch/arm/boards/imx21ads/lowlevel_init.S
View File

@ -18,6 +18,7 @@
*/
#include <config.h>
#include <asm-generic/memory_layout.h>
#include <mach/imx-regs.h>
.section ".text_bare_init","ax"
@ -121,7 +122,7 @@ board_init_lowlevel:
str r1, [r0]
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =TEXT_BASE - 4 /* Setup a temporary stack in SDRAM */
ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
ldr r2, =IMX_NFC_BASE + 0x800 /* end of NFC SRAM */
@ -133,7 +134,7 @@ board_init_lowlevel:
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =TEXT_BASE
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
@ -143,10 +144,7 @@ copy_loop:
ldr pc, =1f /* Jump to SDRAM */
1:
bl nand_boot /* Load barebox from NAND Flash */
ldr r1, =IMX_NFC_BASE - TEXT_BASE
sub r10, r10, r1 /* adjust return address from NFC */
b nand_boot /* Load barebox from NAND Flash */
/* SRAM to SDRAM */
#endif /* CONFIG_NAND_IMX_BOOT */

3
arch/arm/boards/karo-tx25/board.c
View File

@ -28,6 +28,7 @@
#include <mach/imx-regs.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <asm/barebox-arm.h>
#include <mach/gpio.h>
#include <io.h>
#include <partition.h>
@ -168,7 +169,7 @@ console_initcall(tx25_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
}
#endif

4
arch/arm/boards/karo-tx25/lowlevel.c
View File

@ -40,7 +40,7 @@ static void __bare_init __naked insdram(void)
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
@ -158,7 +158,7 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)

2
arch/arm/boards/karo-tx51/flash_header.c
View File

@ -39,7 +39,7 @@ struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
};
#define APP_DEST CONFIG_ARCH_TEXT_BASE
#define APP_DEST 0x90000000
struct imx_flash_header __flash_header_section flash_header = {
.app_code_jump_vector = APP_DEST + 0x1000,

3
arch/arm/boards/mini2440/mini2440.c
View File

@ -36,6 +36,7 @@
#include <mci.h>
#include <fb.h>
#include <asm/armlinux.h>
#include <asm-generic/sections.h>
#include <io.h>
#include <mach/gpio.h>
#include <mach/s3c-iomap.h>
@ -326,7 +327,7 @@ device_initcall(mini2440_devices_init);
#ifdef CONFIG_S3C_NAND_BOOT
void __bare_init nand_boot(void)
{
s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
s3c24x0_nand_load_image(_text, 256 * 1024, 0);
}
#endif

7
arch/arm/boards/pcm037/lowlevel_init.S
View File

@ -146,7 +146,7 @@ clear_iomux:
bhs ret
/* Move ourselves out of NFC SRAM */
ldr r1, =TEXT_BASE
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
@ -156,10 +156,7 @@ copy_loop:
ldr pc, =1f /* Jump to SDRAM */
1:
bl nand_boot /* Load barebox from NAND Flash */
ldr r1, =IMX_NFC_BASE - TEXT_BASE
sub r10, r10, r1 /* adjust return address from NFC SRAM */
b nand_boot /* Load barebox from NAND Flash */
ret:
#endif /* CONFIG_NAND_IMX_BOOT */

4
arch/arm/boards/pcm037/pcm037.c
View File

@ -37,6 +37,7 @@
#include <asm/mmu.h>
#include <partition.h>
#include <generated/mach-types.h>
#include <asm/barebox-arm.h>
#include <mach/imx-nand.h>
#include <mach/devices-imx31.h>
@ -246,6 +247,7 @@ console_initcall(imx31_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
#endif

4
arch/arm/boards/pcm038/lowlevel.c
View File

@ -45,7 +45,7 @@ static void __bare_init __naked insdram(void)
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
@ -111,7 +111,7 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)

4
arch/arm/boards/pcm043/lowlevel.c
View File

@ -58,7 +58,7 @@ static void __bare_init __naked insdram(void)
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
board_init_lowlevel_return();
}
@ -213,7 +213,7 @@ void __bare_init __naked board_init_lowlevel(void)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
trg = (unsigned int *)_text;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)

8
arch/arm/boards/phycard-i.MX27/lowlevel_init.S
View File

@ -106,7 +106,7 @@ board_init_lowlevel:
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =TEXT_BASE
ldr r1, =_text
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
@ -116,11 +116,7 @@ copy_loop:
ldr pc, =1f /* Jump to SDRAM */
1:
bl nand_boot /* Load barebox from NAND Flash */
ldr r1, =IMX_NFC_BASE - TEXT_BASE
sub r10, r10, r1 /* adjust return address from NFC SRAM */
/* to SDRAM */
b nand_boot /* Load barebox from NAND Flash */
#endif /* CONFIG_NAND_IMX_BOOT */

2
arch/arm/boards/phycard-i.MX27/pca100.c
View File

@ -328,7 +328,7 @@ console_initcall(pca100_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image((void *)TEXT_BASE, barebox_image_size);
imx_nand_load_image(_text, barebox_image_size);
}
#endif

5
arch/arm/boards/tqma53/flash_header.c
View File

@ -15,11 +15,12 @@
#include <common.h>
#include <asm/byteorder.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx-flash-header.h>
void __naked __flash_header_start go(void)
{
__asm__ __volatile__("b exception_vectors\n");
barebox_arm_head();
}
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
@ -84,7 +85,7 @@ struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
{ .addr = cpu_to_be32(0x63fd901C), .val = cpu_to_be32(0x00000000), },
};
#define APP_DEST CONFIG_TEXT_BASE
#define APP_DEST 0x70000000
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,

7
arch/arm/cpu/cache-armv4.S
View File

@ -3,6 +3,7 @@
#define CACHE_DLINESIZE 32
.section .text.__mmu_cache_on
ENTRY(__mmu_cache_on)
mov r12, lr
#ifdef CONFIG_MMU
@ -30,6 +31,7 @@ __common_mmu_cache_on:
mrc p15, 0, r0, c1, c0, 0 @ and read it back to
sub pc, lr, r0, lsr #32 @ properly flush pipeline
.section .text.__mmu_cache_off
ENTRY(__mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
@ -42,6 +44,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
.section .text.__mmu_cache_flush
ENTRY(__mmu_cache_flush)
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
@ -74,7 +77,6 @@ no_cache_id:
mov pc, lr
ENDPROC(__mmu_cache_flush)
.section ".text.text"
/*
* dma_inv_range(start, end)
*
@ -88,6 +90,7 @@ ENDPROC(__mmu_cache_flush)
*
* (same as v4wb)
*/
.section .text.__dma_inv_range
ENTRY(__dma_inv_range)
tst r0, #CACHE_DLINESIZE - 1
bic r0, r0, #CACHE_DLINESIZE - 1
@ -111,6 +114,7 @@ ENTRY(__dma_inv_range)
*
* (same as v4wb)
*/
.section .text.__dma_clean_range
ENTRY(__dma_clean_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@ -128,6 +132,7 @@ ENTRY(__dma_clean_range)
* - start - virtual start address
* - end - virtual end address
*/
.section .text.__dma_flush_range
ENTRY(__dma_flush_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry

7
arch/arm/cpu/cache-armv5.S
View File

@ -3,6 +3,7 @@
#define CACHE_DLINESIZE 32
.section .text.__mmu_cache_on
ENTRY(__mmu_cache_on)
mov r12, lr
#ifdef CONFIG_MMU
@ -30,6 +31,7 @@ __common_mmu_cache_on:
mrc p15, 0, r0, c1, c0, 0 @ and read it back to
sub pc, lr, r0, lsr #32 @ properly flush pipeline
.section .text.__mmu_cache_off
ENTRY(__mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
@ -42,6 +44,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
.section .text.__mmu_cache_flush
ENTRY(__mmu_cache_flush)
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
@ -49,7 +52,6 @@ ENTRY(__mmu_cache_flush)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
ENDPROC(__mmu_cache_flush)
.section ".text.text"
/*
* dma_inv_range(start, end)
@ -64,6 +66,7 @@ ENDPROC(__mmu_cache_flush)
*
* (same as v4wb)
*/
.section .text.__dma_inv_range
ENTRY(__dma_inv_range)
tst r0, #CACHE_DLINESIZE - 1
bic r0, r0, #CACHE_DLINESIZE - 1
@ -87,6 +90,7 @@ ENTRY(__dma_inv_range)
*
* (same as v4wb)
*/
.section .text.__dma_clean_range
ENTRY(__dma_clean_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@ -104,6 +108,7 @@ ENTRY(__dma_clean_range)
* - start - virtual start address
* - end - virtual end address
*/
.section .text.__dma_flush_range
ENTRY(__dma_flush_range)
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry

11
arch/arm/cpu/cache-armv6.S
View File

@ -5,6 +5,7 @@
#define CACHE_LINE_SIZE 32
#define D_CACHE_LINE_SIZE 32
.section .text.__mmu_cache_on
ENTRY(__mmu_cache_on)
mov r12, lr
#ifdef CONFIG_MMU
@ -33,6 +34,7 @@ __common_mmu_cache_on:
sub pc, lr, r0, lsr #32 @ properly flush pipeline
.section .text.__mmu_cache_off
ENTRY(__mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
@ -44,6 +46,7 @@ ENTRY(__mmu_cache_off)
#endif
mov pc, lr
.section .text.__mmu_cache_flush
ENTRY(__mmu_cache_flush)
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
@ -52,7 +55,6 @@ ENTRY(__mmu_cache_flush)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
ENDPROC(__mmu_cache_flush)
.section ".text.text"
/*
* v6_dma_inv_range(start,end)
@ -64,6 +66,7 @@ ENDPROC(__mmu_cache_flush)
* - start - virtual start address of region
* - end - virtual end address of region
*/
.section .text.__dma_inv_range
ENTRY(__dma_inv_range)
tst r0, #D_CACHE_LINE_SIZE - 1
bic r0, r0, #D_CACHE_LINE_SIZE - 1
@ -91,12 +94,14 @@ ENTRY(__dma_inv_range)
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
ENDPROC(__dma_inv_range)
/*
* v6_dma_clean_range(start,end)
* - start - virtual start address of region
* - end - virtual end address of region
*/
.section .text.__dma_clean_range
ENTRY(__dma_clean_range)
bic r0, r0, #D_CACHE_LINE_SIZE - 1
1:
@ -111,12 +116,14 @@ ENTRY(__dma_clean_range)
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
ENDPROC(__dma_clean_range)
/*
* v6_dma_flush_range(start,end)
* - start - virtual start address of region
* - end - virtual end address of region
*/
.section .text.__dma_flush_range
ENTRY(__dma_flush_range)
bic r0, r0, #D_CACHE_LINE_SIZE - 1
1:
@ -131,4 +138,4 @@ ENTRY(__dma_flush_range)
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
mov pc, lr
ENDPROC(__dma_flush_range)

8
arch/arm/cpu/cache-armv7.S
View File

@ -1,6 +1,7 @@
#include <linux/linkage.h>
#include <init.h>
.section .text.__mmu_cache_on
ENTRY(__mmu_cache_on)
mov r12, lr
#ifdef CONFIG_MMU
@ -30,6 +31,7 @@ ENTRY(__mmu_cache_on)
mov pc, r12
ENDPROC(__mmu_cache_on)
.section .text.__mmu_cache_off
ENTRY(__mmu_cache_off)
mrc p15, 0, r0, c1, c0
#ifdef CONFIG_MMU
@ -50,6 +52,7 @@ ENTRY(__mmu_cache_off)
mov pc, r12
ENDPROC(__mmu_cache_off)
.section .text.__mmu_cache_flush
ENTRY(__mmu_cache_flush)
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
@ -110,7 +113,6 @@ iflush:
mcr p15, 0, r10, c7, c5, 4 @ ISB
mov pc, lr
ENDPROC(__mmu_cache_flush)
.section ".text.text"
/*
* cache_line_size - get the cache line size from the CSIDR register
@ -134,6 +136,7 @@ ENDPROC(__mmu_cache_flush)
* - start - virtual start address of region
* - end - virtual end address of region
*/
.section .text.__dma_inv_range
ENTRY(__dma_inv_range)
dcache_line_size r2, r3
sub r3, r2, #1
@ -158,6 +161,7 @@ ENDPROC(__dma_inv_range)
* - start - virtual start address of region
* - end - virtual end address of region
*/
.section .text.__dma_clean_range
ENTRY(__dma_clean_range)
dcache_line_size r2, r3
sub r3, r2, #1
@ -176,6 +180,7 @@ ENDPROC(__dma_clean_range)
* - start - virtual start address of region
* - end - virtual end address of region
*/
.section .text.__dma_flush_range
ENTRY(__dma_flush_range)
dcache_line_size r2, r3
sub r3, r2, #1
@ -188,4 +193,3 @@ ENTRY(__dma_flush_range)
dsb
mov pc, lr
ENDPROC(__dma_flush_range)

28
arch/arm/cpu/exceptions.S
View File

@ -109,38 +109,29 @@ _STACK_START:
.arm
.align 5
.globl undefined_instruction
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
.globl software_interrupt
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
.globl prefetch_abort
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
.globl data_abort
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
.globl irq
.globl fiq
.align 5
irq:
get_bad_stack
@ -153,3 +144,22 @@ fiq:
bad_save_user_regs
bl do_fiq
.section .text_exceptions
1: b 1b /* reset */
#ifdef CONFIG_ARM_EXCEPTIONS
ldr pc, =undefined_instruction /* undefined instruction */
ldr pc, =software_interrupt /* software interrupt (SWI) */
ldr pc, =prefetch_abort /* prefetch abort */
ldr pc, =data_abort /* data abort */
1: b 1b /* (reserved) */
ldr pc, =irq /* irq (interrupt) */
ldr pc, =fiq /* fiq (fast interrupt) */
#else
1: b 1b /* undefined instruction */
1: b 1b /* software interrupt (SWI) */
1: b 1b /* prefetch abort */
1: b 1b /* data abort */
1: b 1b /* (reserved) */
1: b 1b /* irq (interrupt) */
1: b 1b /* fiq (fast interrupt) */
#endif

37
arch/arm/cpu/start.c
View File

@ -33,31 +33,6 @@ void __naked __section(.text_entry) start(void)
barebox_arm_head();
}
void __naked __section(.text_exceptions) exception_vectors(void)
{
__asm__ __volatile__ (
".arm\n"
"b reset\n" /* reset */
#ifdef CONFIG_ARM_EXCEPTIONS
"ldr pc, =undefined_instruction\n" /* undefined instruction */
"ldr pc, =software_interrupt\n" /* software interrupt (SWI) */
"ldr pc, =prefetch_abort\n" /* prefetch abort */
"ldr pc, =data_abort\n" /* data abort */
"1: b 1b\n" /* (reserved) */
"ldr pc, =irq\n" /* irq (interrupt) */
"ldr pc, =fiq\n" /* fiq (fast interrupt) */
#else
"1: b 1b\n" /* undefined instruction */
"1: b 1b\n" /* software interrupt (SWI) */
"1: b 1b\n" /* prefetch abort */
"1: b 1b\n" /* data abort */
"1: b 1b\n" /* (reserved) */
"1: b 1b\n" /* irq (interrupt) */
"1: b 1b\n" /* fiq (fast interrupt) */
#endif
);
}
/*
* The actual reset vector. This code is position independent and usually
* does not run at the address it's linked at.
@ -104,7 +79,7 @@ void __naked __bare_init reset(void)
*/
void __naked __section(.text_ll_return) board_init_lowlevel_return(void)
{
uint32_t r, addr;
uint32_t r, addr, offset;
/*
* Get runtime address of this function. Do not
@ -116,13 +91,13 @@ void __naked __section(.text_ll_return) board_init_lowlevel_return(void)
r = STACK_BASE + STACK_SIZE - 16;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
/* Get start of binary image */
addr -= (uint32_t)&__ll_return - TEXT_BASE;
/* Get offset between linked address and runtime address */
offset = (uint32_t)__ll_return - addr;
/* relocate to link address if necessary */
if (addr != TEXT_BASE)
memcpy((void *)TEXT_BASE, (void *)addr,
(unsigned int)&__bss_start - TEXT_BASE);
if (offset)
memcpy((void *)_text, (void *)(_text - offset),
__bss_start - _text);
/* clear bss */
memset(__bss_start, 0, __bss_stop - __bss_start);

3
arch/arm/lib/Makefile
View File

@ -20,5 +20,4 @@ obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memcpy.o
obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o
obj-$(CONFIG_ARM_UNWIND) += unwind.o
obj-$(CONFIG_MODULES) += module.o
extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds
extra-y += barebox.lds

1
arch/arm/lib/ashldi3.S
View File

@ -36,6 +36,7 @@ Boston, MA 02110-1301, USA. */
#define ah r1
#endif
.section .text.__ashldi3
ENTRY(__ashldi3)
ENTRY(__aeabi_llsl)

1
arch/arm/lib/ashrdi3.S
View File

@ -36,6 +36,7 @@ Boston, MA 02110-1301, USA. */
#define ah r1
#endif
.section .text.__ashrdi3
ENTRY(__ashrdi3)
ENTRY(__aeabi_lasr)

8
arch/arm/lib/barebox.lds.S
View File

@ -41,11 +41,6 @@ SECTIONS
*(.text_entry*)
__ll_return = .;
*(.text_ll_return*)
#ifdef CONFIG_ARCH_EP93XX
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243) /* 'CRUS' */
#endif
__bare_init_start = .;
*(.text_bare_init*)
__bare_init_end = .;
@ -80,9 +75,6 @@ SECTIONS
. = ALIGN(4);
.data : { *(.data*) }
. = ALIGN(4);
.got : { *(.got*) }
. = .;
__barebox_cmd_start = .;
.barebox_cmd : { BAREBOX_CMDS }

2
arch/arm/lib/io-writesw-armv4.S
View File

@ -22,6 +22,8 @@
#endif
.endm
.section .text.__raw_writesw
.Loutsw_align: movs ip, r1, lsl #31
bne .Loutsw_noalign

7
arch/arm/lib/lib1funcs.S
View File

@ -205,6 +205,7 @@ Boston, MA 02111-1307, USA. */
.endm
.section .text.__udivsi3
ENTRY(__udivsi3)
ENTRY(__aeabi_uidiv)
@ -233,6 +234,7 @@ ENTRY(__aeabi_uidiv)
ENDPROC(__udivsi3)
ENDPROC(__aeabi_uidiv)
.section .text.__umodsi3
ENTRY(__umodsi3)
subs r2, r1, #1 @ compare divisor with 1
@ -249,6 +251,7 @@ ENTRY(__umodsi3)
ENDPROC(__umodsi3)
.section .text.__divsi3
ENTRY(__divsi3)
ENTRY(__aeabi_idiv)
@ -290,6 +293,7 @@ ENTRY(__aeabi_idiv)
ENDPROC(__divsi3)
ENDPROC(__aeabi_idiv)
.section .text.__modsi3
ENTRY(__modsi3)
cmp r1, #0
@ -314,6 +318,7 @@ ENDPROC(__modsi3)
#ifdef CONFIG_AEABI
.section .text.__aeabi_uidivmod
ENTRY(__aeabi_uidivmod)
stmfd sp!, {r0, r1, ip, lr}
@ -325,6 +330,7 @@ ENTRY(__aeabi_uidivmod)
ENDPROC(__aeabi_uidivmod)
.section .text.__aeabi_idivmod
ENTRY(__aeabi_idivmod)
stmfd sp!, {r0, r1, ip, lr}
@ -338,6 +344,7 @@ ENDPROC(__aeabi_idivmod)
#endif
.section .text.Ldiv0
Ldiv0:
str lr, [sp, #-8]!

1
arch/arm/lib/lshrdi3.S
View File

@ -36,6 +36,7 @@ Boston, MA 02110-1301, USA. */
#define ah r1
#endif
.section .text.__lshrdi3
ENTRY(__lshrdi3)
ENTRY(__aeabi_llsr)

1
arch/arm/mach-at91/Kconfig
View File

@ -45,7 +45,6 @@ config ARCH_AT91RM9200
bool "AT91RM9200"
select CPU_ARM920T
select HAS_AT91_ETHER
select ARCH_HAS_LOWLEVEL_INIT
select MACH_HAS_LOWLEVEL_INIT
select MACH_DO_LOWLEVEL_INIT

18
arch/arm/mach-at91/at91rm9200_lowlevel_init.c
View File

@ -20,24 +20,6 @@ void static inline access_sdram(void)
writel(0x00000000, AT91_SDRAM_BASE);
}
void __naked __bare_init arch_init_lowlevel(void)
{
/*
* relocate exception table
*/
__asm__ __volatile__ (
" ldr r0, =exception_vectors\n"
" ldr r1, =0x0\n"
" mov r2, #16\n"
"loopev:\n"
" subs r2, r2, #1\n"
" ldr r3, [r0], #4\n"
" str r3, [r1], #4\n"
" bne loopev\n"
" mov pc, lr\n"
);
}
void __naked __bare_init board_init_lowlevel(void)
{
u32 r;

2
arch/arm/mach-ep93xx/Makefile
View File

@ -1,3 +1,3 @@
obj-y += clocksource.o gpio.o led.o
obj-y += clocksource.o gpio.o led.o header.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o

8
arch/arm/mach-ep93xx/header.c Normal file
View File

@ -0,0 +1,8 @@
#include <common.h>
#include <linux/compiler.h>
#include <asm/barebox-arm-head.h>
void __naked __section(.flash_header_start) go(void)
{
barebox_arm_head();
}

9
arch/arm/mach-ep93xx/include/mach/barebox.lds.h Normal file
View File

@ -0,0 +1,9 @@
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
#define PRE_IMAGE \
.pre_image : { \
KEEP(*(.flash_header_start*)) \
. = 0x1000; \
LONG(0x53555243) /* 'CRUS' */ \
}

3
include/asm-generic/barebox.lds.h
View File

@ -4,7 +4,8 @@
defined CONFIG_ARCH_IMX51 || \
defined CONFIG_ARCH_IMX53 || \
defined CONFIG_ARCH_IMX6 || \
defined CONFIG_X86
defined CONFIG_X86 || \
defined CONFIG_ARCH_EP93XX
#include <mach/barebox.lds.h>
#endif

8
include/lzo.h
View File

@ -19,12 +19,16 @@
#define lzo1x_worst_compress(x) ((x) + ((x) / 16) + 64 + 3)
#ifndef STATIC
#define STATIC
#endif
/* This requires 'workmem' of size LZO1X_1_MEM_COMPRESS */
int lzo1x_1_compress(const unsigned char *src, size_t src_len,
unsigned char *dst, size_t *dst_len, void *wrkmem);
/* safe decompression with overrun testing */
int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
STATIC int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
unsigned char *dst, size_t *dst_len);
/*
@ -41,7 +45,7 @@ int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
#define LZO_E_INPUT_NOT_CONSUMED (-8)
#define LZO_E_NOT_YET_IMPLEMENTED (-9)
int decompress_unlzo(u8 *input, int in_len,
STATIC int decompress_unlzo(u8 *input, int in_len,
int (*fill) (void *, unsigned int),
int (*flush) (void *, unsigned int),
u8 *output, int *posp,

10
lib/decompress_unlzo.c
View File

@ -33,11 +33,16 @@
#include <common.h>
#include <malloc.h>
#include <linux/types.h>
#include <lzo.h>
#include <errno.h>
#include <fs.h>
#include <xfuncs.h>
#ifdef STATIC
#include "lzo/lzo1x_decompress.c"
#endif
#include <lzo.h>
#include <linux/compiler.h>
#include <asm/unaligned.h>
@ -106,7 +111,7 @@ static inline int parse_header(u8 *input, int *skip, int in_len)
return 1;
}
int decompress_unlzo(u8 *input, int in_len,
STATIC int decompress_unlzo(u8 *input, int in_len,
int (*fill) (void *, unsigned int),
int (*flush) (void *, unsigned int),
u8 *output, int *posp,
@ -284,3 +289,4 @@ exit_1:
exit:
return ret;
}
#define decompress decompress_unlzo

2
lib/lzo/lzo1x_decompress.c
View File

@ -23,7 +23,7 @@
#define COPY4(dst, src) \
put_unaligned(get_unaligned((const u32 *)(src)), (u32 *)(dst))
int lzo1x_decompress_safe(const unsigned char *in, size_t in_len,
STATIC int lzo1x_decompress_safe(const unsigned char *in, size_t in_len,
unsigned char *out, size_t *out_len)
{
const unsigned char * const ip_end = in + in_len;

25
scripts/Makefile.build
View File

@ -7,7 +7,30 @@ src := $(obj)
PHONY := __build
__build:
# Read .config if it exist, otherwise ignore
# Init all relevant variables used in kbuild files so
# 1) they have correct type
# 2) they do not inherit any value from the environment
obj-y :=
obj-m :=
lib-y :=
lib-m :=
always :=
targets :=
subdir-y :=
subdir-m :=
EXTRA_AFLAGS :=
EXTRA_CFLAGS :=
EXTRA_CPPFLAGS :=
EXTRA_LDFLAGS :=
asflags-y :=
ccflags-y :=
cppflags-y :=
ldflags-y :=
subdir-asflags-y :=
subdir-ccflags-y :=
# Read auto.conf if it exists, otherwise ignore
-include include/config/auto.conf
include scripts/Kbuild.include