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Merge branch 'for-next/am335x'

This commit is contained in:
Sascha Hauer 2015-03-06 08:33:20 +01:00
parent ae16aba24b 7ba2d51d6f
commit ea2153ce86
42 changed files with 736 additions and 556 deletions
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22
Documentation/boards/am335x.rst
View File

@ -13,14 +13,20 @@ for the MLO and ``am335x_defconfig`` for the regular barebox image. The
resulting images will be placed under ``images/``:
::
barebox-am33xx-afi-gf.img
barebox-am33xx-afi-gf-mlo.img
barebox-am33xx-beaglebone.img
barebox-am33xx-beaglebone-mlo.img
barebox-am33xx-phytec-phycore-mlo-256mb.img
barebox-am33xx-phytec-phycore-mlo-128mb.img
barebox-am33xx-phytec-phycore-mlo-512mb.img
barebox-am33xx-phytec-phycore-mlo-2x512mb.img
barebox-am33xx-phytec-phyflex-mlo-256mb.img
barebox-am33xx-phytec-phyflex-mlo-512mb.img
barebox-am33xx-phytec-phycore.img
barebox-am33xx-phytec-phycore-mlo-1x128m16.img
barebox-am33xx-phytec-phycore-mlo-1x256m16.img
barebox-am33xx-phytec-phycore-mlo-1x512m16.img
barebox-am33xx-phytec-phycore-no-spi.img
barebox-am33xx-phytec-phyflex.img
Some boards come in different variants, make sure to pick the correct one.
@ -40,3 +46,13 @@ SD/MMC
To start barebox from SD/MMC prepare a card with a FAT filesystem. Copy the MLO
file for your board to the card and name it ``MLO``. Copy the regular image
for your board to the card and name it ``barebox.bin``.
AM335x Boards
------
.. toctree::
:glob:
:numbered:
:maxdepth: 1
am335x/*

35
Documentation/boards/am335x/phytec-som.rst Normal file
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@ -0,0 +1,35 @@
Phytec AM335x based SOMs
========================
The phycore-som-am335x is actually not a real board. It represents a set of
am335x based Phytec module families and its boards in the barebox.
You can find out more about the Phytec SOM concept on the website:
http://phytec.com/products/system-on-modules/
Supported modules and boards
----------------------------
Currently, barebox supports the following SOMs and boards:
- phyCORE
- PCM-953
- phyBOARD-MAIA
- phyBOARD-WEGA
- phyFLEX
- PBA-B-01
- phyCARD
- PCA-A-XS1
Building phycore-som-am335x
---------------------------
The phycore-som-am335x boards are covered by the ``am335x_mlo_defconfig``
for the MLO and ``am335x_defconfig`` for the regular barebox image.

3
arch/arm/boards/Makefile
View File

@ -81,8 +81,7 @@ obj-$(CONFIG_MACH_PCM037) += phytec-phycore-imx31/
obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/
obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/
obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/
obj-$(CONFIG_MACH_PCM051) += phytec-phycore-am335x/
obj-$(CONFIG_MACH_PFLA03) += phytec-phyflex-am335x/
obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/
obj-$(CONFIG_MACH_PHYTEC_PFLA02) += phytec-phyflex-imx6/
obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/
obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/

8
arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/mmc
View File

@ -1,8 +0,0 @@
#!/bin/sh
global.bootm.image=/boot/linuximage
#global.bootm.oftree=/boot/oftree
bootargs-ip
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rw rootwait"

8
arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/nand
View File

@ -1,8 +0,0 @@
#!/bin/sh
global.bootm.image="/dev/nand0.kernel.bb"
#global.bootm.oftree="/env/oftree"
bootargs-ip
global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rw rootfstype=ubifs"

4
arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/init/init-usbserial
View File

@ -1,4 +0,0 @@
#!/bin/sh
#otg1.mode=peripheral
usbgadget -a -A /dev/nand0.kernel.bb(kernel)

1
arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/nv/bootargs.base
View File

@ -1 +0,0 @@
console=ttyO0,115200

1
arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/nv/hostname
View File

@ -1 +0,0 @@
pcm051

215
arch/arm/boards/phytec-phycore-am335x/lowlevel.c
View File

@ -1,215 +0,0 @@
#include <common.h>
#include <linux/sizes.h>
#include <io.h>
#include <init.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <mach/am33xx-silicon.h>
#include <mach/am33xx-clock.h>
#include <mach/generic.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
#include <mach/am33xx-mux.h>
#include <mach/am33xx-generic.h>
#include <mach/wdt.h>
#include <debug_ll.h>
static const struct am33xx_cmd_control pcm051_cmd = {
.slave_ratio0 = 0x80,
.dll_lock_diff0 = 0x0,
.invert_clkout0 = 0x0,
.slave_ratio1 = 0x80,
.dll_lock_diff1 = 0x0,
.invert_clkout1 = 0x0,
.slave_ratio2 = 0x80,
.dll_lock_diff2 = 0x0,
.invert_clkout2 = 0x0,
};
struct pcm051_sdram_timings {
struct am33xx_emif_regs regs;
struct am33xx_ddr_data data;
};
enum {
MT41J128M16125IT_256MB,
MT41J64M1615IT_128MB,
MT41J256M16HA15EIT_512MB,
MT41J512M8125IT_2x512MB,
};
struct pcm051_sdram_timings timings[] = {
/* 256MB */
[MT41J128M16125IT_256MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x3B,
.wr_dqs_slave_ratio0 = 0x33,
.fifo_we_slave_ratio0 = 0x9c,
.wr_slave_ratio0 = 0x6f,
},
},
/* 128MB */
[MT41J64M1615IT_128MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x262F7FDA,
.emif_tim3 = 0x501F82BF,
.sdram_config = 0x61C05232,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x38,
.wr_dqs_slave_ratio0 = 0x34,
.fifo_we_slave_ratio0 = 0xA2,
.wr_slave_ratio0 = 0x72,
},
},
/* 512MB */
[MT41J256M16HA15EIT_512MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
.sdram_config = 0x61C05332,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30
},
.data = {
.rd_slave_ratio0 = 0x35,
.wr_dqs_slave_ratio0 = 0x43,
.fifo_we_slave_ratio0 = 0x97,
.wr_slave_ratio0 = 0x7b,
},
},
/* 1024MB */
[MT41J512M8125IT_2x512MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
.sdram_config = 0x61C053B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30
},
.data = {
.rd_slave_ratio0 = 0x32,
.wr_dqs_slave_ratio0 = 0x48,
.fifo_we_slave_ratio0 = 0x99,
.wr_slave_ratio0 = 0x80,
},
},
};
extern char __dtb_am335x_phytec_phycore_som_start[];
extern char __dtb_am335x_phytec_phycore_som_mlo_start[];
extern char __dtb_am335x_phytec_phycore_som_no_spi_start[];
/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
static noinline void pcm051_board_init(int sdram)
{
void *fdt;
struct pcm051_sdram_timings *timing = &timings[sdram];
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_400);
am335x_sdram_init(0x18B, &pcm051_cmd,
&timing->regs,
&timing->data);
am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
am33xx_enable_uart0_pin_mux();
omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
putc_ll('>');
fdt = __dtb_am335x_phytec_phycore_som_mlo_start - get_runtime_offset();
am335x_barebox_entry(fdt);
}
static noinline void pcm051_board_entry(unsigned long bootinfo, int sdram)
{
am33xx_save_bootinfo((void *)bootinfo);
arm_cpu_lowlevel_init();
/*
* Setup C environment, the board init code uses global variables.
* Stackpointer has already been initialized by the ROM code.
*/
relocate_to_current_adr();
setup_c();
pcm051_board_init(sdram);
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_256mb, bootinfo, r1, r2)
{
pcm051_board_entry(bootinfo, MT41J128M16125IT_256MB);
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_128mb, bootinfo, r1, r2)
{
pcm051_board_entry(bootinfo, MT41J64M1615IT_128MB);
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, bootinfo, r1, r2)
{
pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB);
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_2x512mb, bootinfo, r1, r2)
{
pcm051_board_entry(bootinfo, MT41J512M8125IT_2x512MB);
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2)
{
void *fdt;
fdt = __dtb_am335x_phytec_phycore_som_start - get_runtime_offset();
am335x_barebox_entry(fdt);
}
ENTRY_FUNCTION(start_am33xx_phytec_phycore_no_spi_sdram, r0, r1, r2)
{
void *fdt;
fdt = __dtb_am335x_phytec_phycore_som_no_spi_start - get_runtime_offset();
am335x_barebox_entry(fdt);
}

3
arch/arm/boards/phytec-phyflex-am335x/Makefile
View File

@ -1,3 +0,0 @@
lwl-y += lowlevel.o
obj-y += board.o
bbenv-y += defaultenv-phyflex-am335x

92
arch/arm/boards/phytec-phyflex-am335x/board.c
View File

@ -1,92 +0,0 @@
/*
* pfla03 - phyFLEX-AM335x Board Initalization Code
*
* Copyright (C) 2014 Stefan Müller-Klieser, Phytec Messtechnik GmbH
*
* Based on arch/arm/boards/omap/board-beagle.c
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <bootsource.h>
#include <common.h>
#include <nand.h>
#include <init.h>
#include <io.h>
#include <linux/sizes.h>
#include <envfs.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <mach/am33xx-generic.h>
#include <mach/am33xx-silicon.h>
#include <mach/bbu.h>
static int pfla03_coredevice_init(void)
{
if (!of_machine_is_compatible("phytec,phyflex-am335x-som"))
return 0;
am33xx_register_ethaddr(0, 0);
am33xx_register_ethaddr(1, 1);
return 0;
}
coredevice_initcall(pfla03_coredevice_init);
static struct omap_barebox_part pfla03_barebox_part = {
.nand_offset = SZ_512K,
.nand_size = SZ_512K,
.nor_offset = SZ_128K,
.nor_size = SZ_512K,
};
static char *xloadslots[] = {
"/dev/nand0.xload.bb",
"/dev/nand0.xload_backup1.bb",
"/dev/nand0.xload_backup2.bb",
"/dev/nand0.xload_backup3.bb"
};
static int pfla03_devices_init(void)
{
if (!of_machine_is_compatible("phytec,phyflex-am335x-som"))
return 0;
switch (bootsource_get()) {
case BOOTSOURCE_SPI:
of_device_enable_path("/chosen/environment-spi");
break;
case BOOTSOURCE_MMC:
omap_set_bootmmc_devname("mmc0");
break;
default:
of_device_enable_path("/chosen/environment-nand");
break;
}
omap_set_barebox_part(&pfla03_barebox_part);
armlinux_set_architecture(MACH_TYPE_PFLA03);
defaultenv_append_directory(defaultenv_phyflex_am335x);
am33xx_select_rmii2_crs_dv();
am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox");
am33xx_bbu_nand_xloadslots_register_handler("MLO.nand",
xloadslots, ARRAY_SIZE(xloadslots));
am33xx_bbu_nand_register_handler("nand", "/dev/nand0.barebox.bb");
return 0;
}
device_initcall(pfla03_devices_init);

8
arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/mmc
View File

@ -1,8 +0,0 @@
#!/bin/sh
global.bootm.image=/boot/linuximage
#global.bootm.oftree=/boot/oftree
bootargs-ip
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rw rootwait"

8
arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/spi
View File

@ -1,8 +0,0 @@
#!/bin/sh
global.bootm.image="/dev/m25p0.kernel"
bootargs-ip
# Use rootfs from NAND
global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs"

15
arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/init/bootsource
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@ -1,15 +0,0 @@
#!/bin/sh
if [ -n "$nv.boot.default" ]; then
exit
fi
if [ $bootsource = mmc ]; then
global.boot.default="mmc nand spi net"
elif [ $bootsource = nand ]; then
global.boot.default="nand spi mmc net"
elif [ $bootsource = spi ]; then
global.boot.default="spi nand mmc net"
elif [ $bootsource = net ]; then
global.boot.default="net nand spi mmc"
fi

1
arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/nv/hostname
View File

@ -1 +0,0 @@
pfla03

1
arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/nv/linux.bootargs.base
View File

@ -1 +0,0 @@
console=ttyO0,115200

2
arch/arm/boards/phytec-phycore-am335x/Makefile → arch/arm/boards/phytec-som-am335x/Makefile
View File

@ -1,3 +1,3 @@
lwl-y += lowlevel.o
obj-y += board.o
bbenv-y += defaultenv-phycore-am335x
bbenv-y += defaultenv-physom-am335x

49
arch/arm/boards/phytec-phycore-am335x/board.c → arch/arm/boards/phytec-som-am335x/board.c
View File

@ -1,9 +1,10 @@
/*
* pcm051 - phyCORE-AM335x Board Initalization Code
* Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
*
* Copyright (C) 2012 Teresa Gámez, Phytec Messtechnik GmbH
*
* Based on arch/arm/boards/omap/board-beagle.c
* Device initialization for the following modules and board variants:
* - phyCORE: PCM-953, phyBOARD-MAIA, phyBOARD-WEGA
* - phyFLEX: PBA-B-01
* - phyCARD: PCA-A-XS1
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -27,22 +28,23 @@
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <mach/am33xx-generic.h>
#include <mach/am33xx-silicon.h>
#include <mach/bbu.h>
static int pcm051_coredevice_init(void)
static int physom_coredevice_init(void)
{
if (!of_machine_is_compatible("phytec,phycore-am335x-som"))
if (!of_machine_is_compatible("phytec,am335x-som"))
return 0;
am33xx_register_ethaddr(0, 0);
return 0;
}
coredevice_initcall(pcm051_coredevice_init);
coredevice_initcall(physom_coredevice_init);
static struct omap_barebox_part pcm051_barebox_part = {
static struct omap_barebox_part physom_barebox_part = {
.nand_offset = SZ_512K,
.nand_size = SZ_512K,
.nor_offset = SZ_128K,
@ -56,9 +58,9 @@ static char *xloadslots[] = {
"/dev/nand0.xload_backup3.bb"
};
static int pcm051_devices_init(void)
static int physom_devices_init(void)
{
if (!of_machine_is_compatible("phytec,phycore-am335x-som"))
if (!of_machine_is_compatible("phytec,am335x-som"))
return 0;
switch (bootsource_get()) {
@ -73,10 +75,27 @@ static int pcm051_devices_init(void)
break;
}
omap_set_barebox_part(&pcm051_barebox_part);
armlinux_set_architecture(MACH_TYPE_PCM051);
defaultenv_append_directory(defaultenv_phycore_am335x);
omap_set_barebox_part(&physom_barebox_part);
defaultenv_append_directory(defaultenv_physom_am335x);
/* Special module set up */
if (of_machine_is_compatible("phytec,phycore-am335x-som")) {
armlinux_set_architecture(MACH_TYPE_PCM051);
barebox_set_hostname("pcm051");
}
if (of_machine_is_compatible("phytec,phyflex-am335x-som")) {
armlinux_set_architecture(MACH_TYPE_PFLA03);
am33xx_select_rmii2_crs_dv();
barebox_set_hostname("pfla03");
}
if (of_machine_is_compatible("phytec,phycard-am335x-som")) {
armlinux_set_architecture(MACH_TYPE_PCAAXS1);
barebox_set_hostname("pcaaxs1");
}
/* Register update handler */
am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox");
am33xx_bbu_nand_xloadslots_register_handler("MLO.nand",
@ -88,4 +107,4 @@ static int pcm051_devices_init(void)
return 0;
}
device_initcall(pcm051_devices_init);
device_initcall(physom_devices_init);

8
arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/mmc Normal file
View File

@ -0,0 +1,8 @@
#!/bin/sh
global.bootm.image=/boot/linuximage
global.bootm.oftree=/boot/oftree
bootargs-ip
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rw rootwait"

2
arch/arm/boards/phytec-phyflex-am335x/defaultenv-phyflex-am335x/boot/nand → arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/nand
View File

@ -1,7 +1,7 @@
#!/bin/sh
global.bootm.image="/dev/nand0.kernel.bb"
#global.bootm.oftree="/env/oftree"
global.bootm.oftree="/dev/nand0.oftree.bb"
bootargs-ip

3
arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/boot/spi → arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/boot/spi
View File

@ -1,8 +1,9 @@
#!/bin/sh
global.bootm.image="/dev/m25p0.kernel"
global.bootm.oftree="/dev/m25p0.oftree"
bootargs-ip
# Use rootfs from NAND
global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rw rootfstype=ubifs"
global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rw rootfstype=ubifs"

0
arch/arm/boards/phytec-phycore-am335x/defaultenv-phycore-am335x/init/bootsource → arch/arm/boards/phytec-som-am335x/defaultenv-physom-am335x/init/bootsource
View File

123
arch/arm/boards/phytec-phyflex-am335x/lowlevel.c → arch/arm/boards/phytec-som-am335x/lowlevel.c
View File

@ -1,9 +1,5 @@
/*
* pfla03 - phyFLEX-AM335x lowlevel code
*
* Copyright (C) 2014 Stefan Müller-Klieser, Phytec Messtechnik GmbH
*
* Based on arch/arm/boards/omap/board-beagle.c
* Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -34,10 +30,12 @@
#include <mach/wdt.h>
#include <debug_ll.h>
#include "ram-timings.h"
#define CLK_M_OSC_MHZ 25
#define DDR_IOCTRL 0x18B
static const struct am33xx_cmd_control pfla03_cmd = {
static const struct am33xx_cmd_control physom_cmd = {
.slave_ratio0 = 0x80,
.dll_lock_diff0 = 0x0,
.invert_clkout0 = 0x0,
@ -49,61 +47,6 @@ static const struct am33xx_cmd_control pfla03_cmd = {
.invert_clkout2 = 0x0,
};
struct pfla03_sdram_timings {
struct am33xx_emif_regs regs;
struct am33xx_ddr_data data;
};
enum {
MT41K128M16JT_256MB,
MT41K256M16HA_512MB,
};
struct pfla03_sdram_timings pfla03_timings[] = {
/* 256 MB */
[MT41K128M16JT_256MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x34,
.wr_dqs_slave_ratio0 = 0x47,
.fifo_we_slave_ratio0 = 0x9a,
.wr_slave_ratio0 = 0x7e,
.use_rank0_delay = 0x0,
.dll_lock_diff0 = 0x0,
},
},
/* 512 MB */
[MT41K256M16HA_512MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
.sdram_config = 0x61C05332,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x36,
.wr_dqs_slave_ratio0 = 0x47,
.fifo_we_slave_ratio0 = 0x95,
.wr_slave_ratio0 = 0x7f,
.use_rank0_delay = 0x0,
.dll_lock_diff0 = 0x0,
},
},
};
extern char __dtb_am335x_phytec_phyflex_start[];
/**
* @brief The basic entry point for board initialization.
*
@ -113,10 +56,9 @@ extern char __dtb_am335x_phytec_phyflex_start[];
*
* @return void
*/
static noinline void pfla03_board_init(int sdram)
static noinline void physom_board_init(int sdram, void *fdt)
{
void *fdt;
struct pfla03_sdram_timings *timing = &pfla03_timings[sdram];
struct am335x_sdram_timings *timing = &physom_timings[sdram];
/*
* WDT1 is already running when the bootloader gets control
@ -125,12 +67,13 @@ static noinline void pfla03_board_init(int sdram)
writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
am33xx_pll_init(MPUPLL_M_600, CLK_M_OSC_MHZ, DDRPLL_M_400);
am335x_sdram_init(DDR_IOCTRL, &pfla03_cmd,
am335x_sdram_init(DDR_IOCTRL, &physom_cmd,
&timing->regs,
&timing->data);
@ -139,12 +82,10 @@ static noinline void pfla03_board_init(int sdram)
omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
putc_ll('>');
fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset();
am335x_barebox_entry(fdt);
}
static noinline void pfla03_board_entry(unsigned long bootinfo, int sdram)
static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void *fdt)
{
am33xx_save_bootinfo((void *)bootinfo);
@ -157,24 +98,40 @@ static noinline void pfla03_board_entry(unsigned long bootinfo, int sdram)
relocate_to_current_adr();
setup_c();
pfla03_board_init(sdram);
physom_board_init(sdram, fdt);
}
ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sram_256mb, bootinfo, r1, r2)
{
pfla03_board_entry(bootinfo, MT41K128M16JT_256MB);
}
#define PHYTEC_ENTRY_MLO(name, fdt_name, sdram) \
ENTRY_FUNCTION(name, bootinfo, r1, r2) \
{ \
extern char __dtb_##fdt_name##_start[]; \
void *fdt =__dtb_##fdt_name##_start - \
get_runtime_offset(); \
physom_board_entry(bootinfo, sdram, fdt); \
}
ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sram_512mb, bootinfo, r1, r2)
{
pfla03_board_entry(bootinfo, MT41K256M16HA_512MB);
}
#define PHYTEC_ENTRY(name, fdt_name) \
ENTRY_FUNCTION(name, r0, r1, r2) \
{ \
extern char __dtb_##fdt_name##_start[]; \
void *fdt =__dtb_##fdt_name##_start - \
get_runtime_offset(); \
am335x_barebox_entry(fdt); \
}
ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sdram, r0, r1, r2)
{
void *fdt;
/* phycore-som */
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_128mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J64M1615IT_128MB);
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J128M16125IT_256MB);
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J256M16HA15EIT_512MB);
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J512M8125IT_2x512MB);
PHYTEC_ENTRY(start_am33xx_phytec_phycore_sdram, am335x_phytec_phycore_som);
PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_sdram, am335x_phytec_phycore_som_no_spi);
fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset();
/* phyflex-som */
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_256mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K128M16JT_256MB);
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_512mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K256M16HA_512MB);
PHYTEC_ENTRY(start_am33xx_phytec_phyflex_sdram, am335x_phytec_phyflex_som);
am335x_barebox_entry(fdt);
}
/* phycard-som */
PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycard_sram_256mb, am335x_phytec_phycard_som_mlo, PHYCARD_NT5CB128M16BP_256MB);
PHYTEC_ENTRY(start_am33xx_phytec_phycard_sdram, am335x_phytec_phycard_som);

177
arch/arm/boards/phytec-som-am335x/ram-timings.h Normal file
View File

@ -0,0 +1,177 @@
/*
* Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __RAM_TIMINGS_H
#define __RAM_TIMINGS_H
struct am335x_sdram_timings {
struct am33xx_emif_regs regs;
struct am33xx_ddr_data data;
};
enum {
PHYFLEX_MT41K128M16JT_256MB,
PHYFLEX_MT41K256M16HA_512MB,
PHYCORE_MT41J128M16125IT_256MB,
PHYCORE_MT41J64M1615IT_128MB,
PHYCORE_MT41J256M16HA15EIT_512MB,
PHYCORE_MT41J512M8125IT_2x512MB,
PHYCARD_NT5CB128M16BP_256MB,
};
struct am335x_sdram_timings physom_timings[] = {
/* 256 MB */
[PHYFLEX_MT41K128M16JT_256MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x34,
.wr_dqs_slave_ratio0 = 0x47,
.fifo_we_slave_ratio0 = 0x9a,
.wr_slave_ratio0 = 0x7e,
.use_rank0_delay = 0x0,
.dll_lock_diff0 = 0x0,
},
},
/* 512 MB */
[PHYFLEX_MT41K256M16HA_512MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
.sdram_config = 0x61C05332,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x36,
.wr_dqs_slave_ratio0 = 0x47,
.fifo_we_slave_ratio0 = 0x95,
.wr_slave_ratio0 = 0x7f,
.use_rank0_delay = 0x0,
.dll_lock_diff0 = 0x0,
},
},
/* 256MB */
[PHYCORE_MT41J128M16125IT_256MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x3B,
.wr_dqs_slave_ratio0 = 0x33,
.fifo_we_slave_ratio0 = 0x9c,
.wr_slave_ratio0 = 0x6f,
},
},
/* 128MB */
[PHYCORE_MT41J64M1615IT_128MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x262F7FDA,
.emif_tim3 = 0x501F82BF,
.sdram_config = 0x61C05232,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x38,
.wr_dqs_slave_ratio0 = 0x34,
.fifo_we_slave_ratio0 = 0xA2,
.wr_slave_ratio0 = 0x72,
},
},
/* 512MB */
[PHYCORE_MT41J256M16HA15EIT_512MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
.sdram_config = 0x61C05332,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30
},
.data = {
.rd_slave_ratio0 = 0x35,
.wr_dqs_slave_ratio0 = 0x43,
.fifo_we_slave_ratio0 = 0x97,
.wr_slave_ratio0 = 0x7b,
},
},
/* 1024MB */
[PHYCORE_MT41J512M8125IT_2x512MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
.sdram_config = 0x61C053B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30
},
.data = {
.rd_slave_ratio0 = 0x32,
.wr_dqs_slave_ratio0 = 0x48,
.fifo_we_slave_ratio0 = 0x99,
.wr_slave_ratio0 = 0x80,
},
},
/* 256MB */
[PHYCARD_NT5CB128M16BP_256MB] = {
.regs = {
.emif_read_latency = 0x7,
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
},
.data = {
.rd_slave_ratio0 = 0x35,
.wr_dqs_slave_ratio0 = 0x3A,
.fifo_we_slave_ratio0 = 0x9b,
.wr_slave_ratio0 = 0x73,
.use_rank0_delay = 0x01,
.dll_lock_diff0 = 0x0,
},
},
};
#endif

5
arch/arm/configs/am335x_defconfig
View File

@ -4,8 +4,7 @@ CONFIG_BAREBOX_UPDATE_AM33XX_NAND=y
CONFIG_OMAP_MULTI_BOARDS=y
CONFIG_MACH_AFI_GF=y
CONFIG_MACH_BEAGLEBONE=y
CONFIG_MACH_PCM051=y
CONFIG_MACH_PFLA03=y
CONFIG_MACH_PHYTEC_SOM_AM335X=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_BOARD_APPEND_ATAG=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@ -25,6 +24,7 @@ CONFIG_MENU=y
CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_RESET_SOURCE=y
CONFIG_DEBUG_INFO=y
CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
@ -125,6 +125,7 @@ CONFIG_EEPROM_AT24=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_BUS_OMAP_GPMC=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y

3
arch/arm/configs/am335x_mlo_defconfig
View File

@ -4,8 +4,7 @@ CONFIG_OMAP_SERIALBOOT=y
CONFIG_OMAP_MULTI_BOARDS=y
CONFIG_MACH_AFI_GF=y
CONFIG_MACH_BEAGLEBONE=y
CONFIG_MACH_PCM051=y
CONFIG_MACH_PFLA03=y
CONFIG_MACH_PHYTEC_SOM_AM335X=y
CONFIG_THUMB2_BAREBOX=y
# CONFIG_MEMINFO is not set
CONFIG_MMU=y

5
arch/arm/dts/Makefile
View File

@ -29,8 +29,9 @@ pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o
pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o
pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore-som.dtb.o am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o
pbl-dtb-$(CONFIG_MACH_PFLA03) += am335x-phytec-phyflex.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o \
am335x-phytec-phycore-som.dtb.o am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o \
am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o imx6q-phytec-phyboard-alcor.dtb.o imx6dl-phytec-phyboard-subra.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o

28
arch/arm/dts/am335x-phytec-phycard-som-mlo.dts Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright (C) 2015 Wadim Egorov <w.egorovphytec.de> PHYTEC Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-phytec-phycard-som.dtsi"
/ {
model = "Phytec phyCARD AM335x";
compatible = "phytec,phycard-am335x-som", "phytec,am335x-som", "ti,am33xx";
};
/* Keep all bootsources disabled, we enable and register them
* later while booting.
*/
&mmc1 {
status = "disabled";
};
&gpmc {
status = "disabled";
};

20
arch/arm/dts/am335x-phytec-phycard-som.dts Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright (C) 2015 Wadim Egorov <w.egorovphytec.de> PHYTEC Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-phytec-phycard-som.dtsi"
/ {
model = "Phytec phyCARD AM335x";
compatible = "phytec,phycard-am335x-som", "phytec,am335x-som", "ti,am33xx";
};
&eeprom {
status = "okay";
};

228
arch/arm/dts/am335x-phytec-phycard-som.dtsi Normal file
View File

@ -0,0 +1,228 @@
/ {
chosen {
linux,stdout-path = &uart0;
environment-nand {
compatible = "barebox,environment";
device-path = &nand, "partname:bareboxenv";
status = "disabled";
};
};
};
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart3_pins: pinmux_uart3 {
pinctrl-single,pins = <
0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd3.uart3_rxd */
0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */
0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */
0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */
0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */
0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */
0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */
>;
};
emac_rmii1_pins: pinmux_emac_rmii1_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
>;
};
nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
eeprom: 24c32@52 {
status = "disabled";
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x54>;
};
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
status = "okay";
};
&phy_sel {
rmii-clock-ext;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
};
&mac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rmii1_pins>;
slaves = <1>;
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand: nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-nand = "true";
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <30>;
gpmc,cs-wr-off-ns = <30>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <30>;
gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <10>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <30>;
gpmc,wr-cycle-ns = <30>;
gpmc,wait-pin = <1>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <50>;
gpmc,cycle2cycle-diffcsen;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
elm_id = <&elm>;
partition@0 {
label = "xload";
reg = <0x0 0x20000>;
};
partition@1 {
label = "xload_backup1";
reg = <0x20000 0x20000>;
};
partition@2 {
label = "xload_backup2";
reg = <0x40000 0x20000>;
};
partition@3 {
label = "xload_backup3";
reg = <0x60000 0x20000>;
};
partition@4 {
label = "barebox";
reg = <0x80000 0x80000>;
};
partition@5 {
label = "bareboxenv";
reg = <0x100000 0x40000>;
};
partition@6 {
label = "oftree";
reg = <0x140000 0x40000>;
};
partition@7 {
label = "kernel";
reg = <0x180000 0x800000>;
};
partition@8 {
label = "root";
reg = <0x980000 0x0>;
};
};
};

2
arch/arm/dts/am335x-phytec-phycore-som-mlo.dts
View File

@ -12,7 +12,7 @@
/ {
model = "Phytec phyCORE AM335x";
compatible = "phytec,phycore-am335x-som", "ti,am33xx";
compatible = "phytec,phycore-am335x-som", "phytec,am335x-som", "ti,am33xx";
};
/* Keep all bootsources disabled, we enable and register them

2
arch/arm/dts/am335x-phytec-phycore-som.dts
View File

@ -12,7 +12,7 @@
/ {
model = "Phytec phyCORE AM335x";
compatible = "phytec,phycore-am335x-som", "ti,am33xx";
compatible = "phytec,phycore-am335x-som", "phytec,am335x-som", "ti,am33xx";
};
&spi0 {

8
arch/arm/dts/am335x-phytec-phycore-som.dtsi
View File

@ -291,17 +291,17 @@
partition@5 {
label = "bareboxenv";
reg = <0x100000 0x20000>;
reg = <0x100000 0x40000>;
};
partition@6 {
label = "oftree";
reg = <0x120000 0x20000>;
reg = <0x140000 0x40000>;
};
partition@7 {
label = "kernel";
reg = <0x140000 0x800000>;
reg = <0x180000 0x800000>;
};
partition@8 {
@ -310,7 +310,7 @@
* Size 0x0 extends partition to
* end of nand flash.
*/
reg = <0x940000 0x0>;
reg = <0x980000 0x0>;
};
};
};

28
arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright (C) 2015 Wadim Egorov <w.egorov@phytec.de> PHYTEC Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-phytec-phyflex-som.dtsi"
/ {
model = "Phytec phyFLEX AM335x";
compatible = "phytec,phyflex-am335x-som", "phytec,am335x-som", "ti,am33xx";
};
/* Keep all bootsources disabled, we enable and register them
* later while booting.
*/
&mmc1 {
status = "disabled";
};
&gpmc {
status = "disabled";
};

24
arch/arm/dts/am335x-phytec-phyflex-som.dts Normal file
View File

@ -0,0 +1,24 @@
/*
* Copyright (C) 2015 Wadim Egorov <w.egorov@phytec.de> PHYTEC Messtechnik GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-phytec-phyflex-som.dtsi"
/ {
model = "Phytec phyFLEX AM335x";
compatible = "phytec,phyflex-am335x-som", "phytec,am335x-som", "ti,am33xx";
};
&spi0 {
status = "okay";
};
&at24c32 {
status = "okay";
};

51
arch/arm/dts/am335x-phytec-phyflex.dts → arch/arm/dts/am335x-phytec-phyflex-som.dtsi
View File

@ -1,11 +1,4 @@
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "Phytec phyFLEX AM335x";
compatible = "phytec,phyflex-am335x-som", "ti,am33xx";
chosen {
linux,stdout-path = &uart0;
@ -36,16 +29,10 @@
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
&am33xx_pinmux {
usb_pins: pinmux_usb {
pinctrl-single,pins = <
0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */
@ -77,7 +64,7 @@
0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
>;
>;
};
emac_rgmii1_pins: pinmux_emac_rgmii1_pins {
@ -136,30 +123,6 @@
};
};
&cppi41dma {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb {
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};
&usb1_phy {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@ -187,7 +150,7 @@
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
status = "disabled";
flash: m25p80 {
compatible = "m25p80";
spi-max-frequency = <48000000>;
@ -340,22 +303,22 @@
partition@5 {
label = "bareboxenv";
reg = <0x100000 0x20000>;
reg = <0x100000 0x40000>;
};
partition@6 {
label = "oftree";
reg = <0x120000 0x20000>;
reg = <0x140000 0x40000>;
};
partition@7 {
label = "kernel";
reg = <0x140000 0x800000>;
reg = <0x180000 0x800000>;
};
partition@8 {
label = "root";
reg = <0x940000 0x0>;
reg = <0x980000 0x0>;
};
};
};

12
arch/arm/mach-omap/Kconfig
View File

@ -147,17 +147,11 @@ config MACH_BEAGLEBONE
help
Say Y here if you are using Beagle Bone
config MACH_PCM051
bool "Phytec phyCORE pcm051"
config MACH_PHYTEC_SOM_AM335X
bool "Phytec AM335X SOMs"
select ARCH_AM33XX
help
Say Y here if you are using Phytecs phyCORE pcm051 board
config MACH_PFLA03
bool "Phytec phyFLEX am335x pfla03"
select ARCH_AM33XX
help
Say Y here if you are using Phytecs phyFLEX pfla03 board
Say Y here if you are using a am335x based Phytecs SOM
endif
choice

36
arch/arm/mach-omap/am33xx_generic.c
View File

@ -26,6 +26,7 @@
#include <mach/sys_info.h>
#include <mach/am33xx-generic.h>
#include <mach/gpmc.h>
#include <reset_source.h>
void __noreturn am33xx_reset_cpu(unsigned long addr)
{
@ -152,6 +153,38 @@ static int am33xx_bootsource(void)
return 0;
}
static void am33xx_detect_reset_reason(void)
{
uint32_t val = 0;
val = readl(AM33XX_PRM_RSTST);
/* clear AM33XX_PRM_RSTST - must be cleared by software
* (warm reset insensitive) */
writel(val, AM33XX_PRM_RSTST);
switch (val) {
case (1 << 9):
reset_source_set(RESET_JTAG);
break;
case (1 << 5):
reset_source_set(RESET_EXT);
break;
case (1 << 4):
case (1 << 3):
reset_source_set(RESET_WDG);
break;
case (1 << 1):
reset_source_set(RESET_RST);
break;
case (1 << 0):
reset_source_set(RESET_POR);
break;
default:
reset_source_set(RESET_UKWN);
break;
}
}
int am33xx_register_ethaddr(int eth_id, int mac_id)
{
void __iomem *mac_id_low = (void *)AM33XX_MAC_ID0_LO + mac_id * 8;
@ -209,6 +242,9 @@ int am33xx_init(void)
am33xx_enable_per_clocks();
if (IS_ENABLED(CONFIG_RESET_SOURCE))
am33xx_detect_reset_reason();
return am33xx_bootsource();
}

1
arch/arm/mach-omap/include/mach/am33xx-silicon.h
View File

@ -68,6 +68,7 @@
#define AM33XX_PRM_RSTCTRL (AM33XX_PRM_BASE + 0x0f00)
#define AM33XX_PRM_RSTCTRL_RESET 0x1
#define AM33XX_PRM_RSTST (AM33XX_PRM_BASE + 0x0f08)
/* CTRL */
#define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000)

5
common/reset_source.c
View File

@ -26,6 +26,7 @@ static const char * const reset_src_names[] = {
[RESET_WKE] = "WKE",
[RESET_JTAG] = "JTAG",
[RESET_THERM] = "THERM",
[RESET_EXT] = "EXT",
};
static enum reset_src_type reset_source;
@ -40,14 +41,14 @@ void reset_source_set(enum reset_src_type st)
{
reset_source = st;
setenv("global.system.reset", reset_src_names[st]);
globalvar_add_simple("system.reset", reset_src_names[reset_source]);
}
EXPORT_SYMBOL(reset_source_set);
/* ensure this runs after the 'global' device is already registerd */
static int reset_source_init(void)
{
globalvar_add_simple("system.reset", reset_src_names[RESET_UKWN]);
reset_source_set(reset_source);
return 0;
}

44
images/Makefile.am33xx
View File

@ -15,41 +15,49 @@ pblx-$(CONFIG_MACH_AFI_GF) += start_am33xx_afi_gf_sram
FILE_barebox-am33xx-afi-gf-mlo.img = start_am33xx_afi_gf_sram.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_AFI_GF) += barebox-am33xx-afi-gf-mlo.img
pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sdram
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_sdram
FILE_barebox-am33xx-phytec-phycore.img = start_am33xx_phytec_phycore_sdram.pblx
am33xx-barebox-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore.img
am33xx-barebox-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore.img
pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_no_spi_sdram
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_no_spi_sdram
FILE_barebox-am33xx-phytec-phycore-no-spi.img = start_am33xx_phytec_phycore_no_spi_sdram.pblx
am33xx-barebox-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-no-spi.img
am33xx-barebox-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-no-spi.img
pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_256mb
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_sram_256mb
FILE_barebox-am33xx-phytec-phycore-mlo-256mb.img = start_am33xx_phytec_phycore_sram_256mb.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-256mb.img
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-256mb.img
pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_128mb
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_sram_128mb
FILE_barebox-am33xx-phytec-phycore-mlo-128mb.img = start_am33xx_phytec_phycore_sram_128mb.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-128mb.img
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-128mb.img
pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_512mb
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_sram_512mb
FILE_barebox-am33xx-phytec-phycore-mlo-512mb.img = start_am33xx_phytec_phycore_sram_512mb.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-512mb.img
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-512mb.img
pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_2x512mb
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycore_sram_2x512mb
FILE_barebox-am33xx-phytec-phycore-mlo-2x512mb.img = start_am33xx_phytec_phycore_sram_2x512mb.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-2x512mb.img
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycore-mlo-2x512mb.img
pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sdram
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phyflex_sdram
FILE_barebox-am33xx-phytec-phyflex.img = start_am33xx_phytec_phyflex_sdram.pblx
am33xx-barebox-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex.img
am33xx-barebox-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phyflex.img
pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sram_256mb
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phyflex_sram_256mb
FILE_barebox-am33xx-phytec-phyflex-mlo-256mb.img = start_am33xx_phytec_phyflex_sram_256mb.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex-mlo-256mb.img
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phyflex-mlo-256mb.img
pblx-$(CONFIG_MACH_PFLA03) += start_am33xx_phytec_phyflex_sram_512mb
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phyflex_sram_512mb
FILE_barebox-am33xx-phytec-phyflex-mlo-512mb.img = start_am33xx_phytec_phyflex_sram_512mb.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_PFLA03) += barebox-am33xx-phytec-phyflex-mlo-512mb.img
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phyflex-mlo-512mb.img
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycard_sdram
FILE_barebox-am33xx-phytec-phycard.img = start_am33xx_phytec_phycard_sdram.pblx
am33xx-barebox-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycard.img
pblx-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += start_am33xx_phytec_phycard_sram_256mb
FILE_barebox-am33xx-phytec-phycard-mlo-256mb.img = start_am33xx_phytec_phycard_sram_256mb.pblx.mlo
am33xx-mlo-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += barebox-am33xx-phytec-phycard-mlo-256mb.img
pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx

1
include/reset_source.h
View File

@ -21,6 +21,7 @@ enum reset_src_type {
RESET_WKE, /* wake-up (some SoCs can handle this) */
RESET_JTAG, /* JTAG reset */
RESET_THERM, /* SoC shut down because of overtemperature */
RESET_EXT, /* External reset through device pin */
};
#ifdef CONFIG_RESET_SOURCE