sysmo-bts
/
barebox
9
0
Fork 0
Code Releases Activity

Merge branch 'mpc86xx'

This commit is contained in:
Jon Loeliger 2006-05-30 09:39:33 -05:00
parent bdee35d0e0 38cee12dcf
commit eaa1fa16c4
2 changed files with 39 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
cpu/mpc86xx/cpu.c
View File

@ -169,7 +169,7 @@ soft_restart(unsigned long addr)
int set_px_sysclk(ulong sysclk) int set_px_sysclk(ulong sysclk)
{ {
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux,tmp; u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
/* Per table 27, page 58 of MPC8641HPCN spec*/ /* Per table 27, page 58 of MPC8641HPCN spec*/
switch(sysclk) switch(sysclk)
@ -354,6 +354,24 @@ void set_px_go_with_watchdog(void)
out8(PIXIS_BASE+PIXIS_VCTL,tmp); out8(PIXIS_BASE+PIXIS_VCTL,tmp);
} }
int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u8 tmp;
tmp = in8(PIXIS_BASE+PIXIS_VCTL);
tmp = tmp & 0x1E;
out8(PIXIS_BASE+PIXIS_VCTL,tmp);
tmp = in8(PIXIS_BASE + PIXIS_VCTL);
tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */
out8(PIXIS_BASE + PIXIS_VCTL, tmp);
return 0;
}
U_BOOT_CMD(
diswd, 1, 0, disable_watchdog,
"diswd - Disable watchdog timer \n",
NULL
);
/* This function takes the non-integral cpu:mpx pll ratio /* This function takes the non-integral cpu:mpx pll ratio
* and converts it to an integer that can be used to assign * and converts it to an integer that can be used to assign
* FPGA register values. * FPGA register values.
@ -509,18 +527,27 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
goto my_usage; goto my_usage;
while(1); /* Not reached */ while(1); /* Not reached */
} else { } else if(argv[2][1] == 'd'){
/* Reset from next bank without changing frequencies */ /* Reset from next bank without changing frequencies but with watchdog timer enabled */
read_from_px_regs(0); read_from_px_regs(0);
read_from_px_regs_altbank(0); read_from_px_regs_altbank(0);
if(argc > 2)
goto my_usage;
printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); printf("Setting registers VCFGEN1, VBOOT, and VCTL\n");
set_altbank(); set_altbank();
read_from_px_regs_altbank(1); read_from_px_regs_altbank(1);
printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
set_px_go_with_watchdog(); set_px_go_with_watchdog();
while(1); /* Not reached */ while(1); /* Not reached */
} else {
/* Reset from next bank without changing frequency and without watchdog timer enabled */
read_from_px_regs(0);
read_from_px_regs_altbank(0);
if(argc > 2)
goto my_usage;
printf("Setting registers VCFGNE1, VBOOT, and VCTL\n");
set_altbank();
read_from_px_regs_altbank(1);
printf("Resetting board to boot from the other bank....\n");
set_px_go();
} }
default: default:

14
cpu/mpc86xx/spd_sdram.c
View File

@ -1088,24 +1088,24 @@ unsigned int enable_ddr(unsigned int ddr_num)
* If the user wanted ECC (enabled via sdram_cfg[2]) * If the user wanted ECC (enabled via sdram_cfg[2])
*/ */
if (config == 0x02) { if (config == 0x02) {
ddr->err_disable = 0x00000000;
asm("sync;isync;");
ddr->err_sbe = 0x00ff0000;
ddr->err_int_en = 0x0000000d;
sdram_cfg_1 |= 0x20000000; /* ECC_EN */ sdram_cfg_1 |= 0x20000000; /* ECC_EN */
} }
#endif #endif
/* /*
* REV1 uses 1T timing. * Set 1T or 2T timing based on 1 or 2 modules
* REV2 may use 1T or 2T as configured by the user.
*/ */
{ {
uint pvr = get_pvr(); if (!(no_dimm1 || no_dimm2)) {
if (pvr != PVR_85xx_REV1) {
#if defined(CONFIG_DDR_2T_TIMING)
/* /*
* 2T timing,because both DIMMS are present.
* Enable 2T timing by setting sdram_cfg[16]. * Enable 2T timing by setting sdram_cfg[16].
*/ */
sdram_cfg_1 |= 0x8000; /* 2T_EN */ sdram_cfg_1 |= 0x8000; /* 2T_EN */
#endif
} }
} }