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mtd nand: add mxs-nand driver 

Based on the U-Boot version. Changed to kernel style register layout, added
MX23 support (WIP!), made MMU aware and adapted to barebox.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Wolfram Sang 2011-12-18 23:26:39 +01:00 committed by Sascha Hauer
parent 4a39f83320
commit eb76c8e827
9 changed files with 1311 additions and 1 deletions
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1
arch/arm/mach-mxs/include/mach/clock-imx23.h
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@ -24,5 +24,6 @@ unsigned imx_set_sspclk(unsigned, unsigned, int);
unsigned imx_set_ioclk(unsigned);
unsigned imx_set_lcdifclk(unsigned);
unsigned imx_get_lcdifclk(void);
void imx_enable_nandclk(void);
#endif /* MACH_CLOCK_IMX23_H */

1
arch/arm/mach-mxs/include/mach/clock-imx28.h
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@ -26,6 +26,7 @@ unsigned imx_set_lcdifclk(unsigned);
unsigned imx_get_lcdifclk(void);
unsigned imx_get_fecclk(void);
void imx_enable_enetclk(void);
void imx_enable_nandclk(void);
#endif /* MACH_CLOCK_IMX28_H */

3
arch/arm/mach-mxs/include/mach/imx23-regs.h
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@ -27,6 +27,9 @@
#endif
#define IMX_MEMORY_BASE 0x40000000
#define MXS_APBH_BASE 0x80004000
#define MXS_BCH_BASE 0x8000a000
#define MXS_GPMI_BASE 0x8000c000
#define IMX_UART1_BASE 0x8006c000
#define IMX_UART2_BASE 0x8006e000
#define IMX_DBGUART_BASE 0x80070000

4
arch/arm/mach-mxs/include/mach/imx28-regs.h
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@ -23,7 +23,9 @@
#define IMX_SRAM_BASE 0x00000000
#define IMX_MEMORY_BASE 0x40000000
#define IMX_NFC_BASE 0x8000C000
#define MXS_APBH_BASE 0x80004000
#define MXS_BCH_BASE 0x8000a000
#define MXS_GPMI_BASE 0x8000c000
#define IMX_SSP0_BASE 0x80010000
#define IMX_SSP1_BASE 0x80012000
#define IMX_SSP2_BASE 0x80014000

19
arch/arm/mach-mxs/speed-imx23.c
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@ -47,6 +47,8 @@
# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
#define HW_CLKCTRL_GPMI 0x080
# define CLKCTRL_GPMI_CLKGATE (1 << 31)
# define CLKCTRL_GPMI_DIV_MASK 0x3ff
/* note: no set/clear register! */
#define HW_CLKCTRL_SPDIF 0x090
/* note: no set/clear register! */
@ -266,6 +268,23 @@ unsigned imx_set_sspclk(unsigned index, unsigned nc, int high)
return imx_get_sspclk(index);
}
void imx_enable_nandclk(void)
{
uint32_t reg;
/* Clear bypass bit; refman says clear, but fsl-code does set. Hooray! */
writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_SET);
reg = readl(IMX_CCM_BASE + HW_CLKCTRL_GPMI) & ~CLKCTRL_GPMI_CLKGATE;
writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI);
udelay(1000);
/* Initialize DIV to 1 */
reg &= ~CLKCTRL_GPMI_DIV_MASK;
reg |= 1;
writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI);
}
void imx_dump_clocks(void)
{
printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000);

19
arch/arm/mach-mxs/speed-imx28.c
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@ -48,6 +48,8 @@
# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
#define HW_CLKCTRL_GPMI 0x0d0
# define CLKCTRL_GPMI_CLKGATE (1 << 31)
# define CLKCTRL_GPMI_DIV_MASK 0x3ff
/* note: no set/clear register! */
#define HW_CLKCTRL_SPDIF 0x0e0
/* note: no set/clear register! */
@ -376,6 +378,23 @@ void imx_enable_enetclk(void)
IMX_CCM_BASE + HW_CLKCTRL_ENET);
}
void imx_enable_nandclk(void)
{
uint32_t reg;
/* Clear bypass bit; refman says clear, but fsl-code does set. Hooray! */
writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_SET);
reg = readl(IMX_CCM_BASE + HW_CLKCTRL_GPMI) & ~CLKCTRL_GPMI_CLKGATE;
writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI);
udelay(1000);
/* Initialize DIV to 1 */
reg &= ~CLKCTRL_GPMI_DIV_MASK;
reg |= 1;
writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI);
}
void imx_dump_clocks(void)
{
printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000);

5
drivers/mtd/nand/Kconfig
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@ -53,6 +53,11 @@ config NAND_IMX
prompt "i.MX NAND driver"
depends on ARCH_IMX
config NAND_MXS
bool
prompt "i.MX23/28 NAND driver"
depends on MXS_APBH_DMA
config NAND_OMAP_GPMC
tristate "NAND Flash Support for GPMC based OMAP platforms"
depends on OMAP_GPMC

2
drivers/mtd/nand/Makefile
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@ -15,3 +15,5 @@ obj-$(CONFIG_NAND_IMX) += nand_imx.o
obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_NAND_S3C24XX) += nand_s3c24xx.o
obj-$(CONFIG_NAND_S3C24X0) += nand_s3c2410.o
obj-$(CONFIG_NAND_MXS) += nand_mxs.o

1258
drivers/mtd/nand/nand_mxs.c Normal file
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