ARM OMAP4: use writel and readl
replace *(volatile int*) by writel and readl Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -263,7 +263,9 @@ int omap4_emif_config(unsigned int base, const struct ddr_regs *ddr_regs)
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static void reset_phy(unsigned int base)
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static void reset_phy(unsigned int base)
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{
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{
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*(volatile int*)(base + IODFT_TLGC) |= (1 << 10);
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unsigned int val = readl(base + IODFT_TLGC);
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val |= (1 << 10);
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writel(val, base + IODFT_TLGC);
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}
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}
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void omap4_ddr_init(const struct ddr_regs *ddr_regs,
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void omap4_ddr_init(const struct ddr_regs *ddr_regs,
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@ -290,8 +292,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
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/* Both EMIFs 128 byte interleaved */
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/* Both EMIFs 128 byte interleaved */
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writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0);
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writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0);
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*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
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writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2);
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*(volatile int*)(OMAP44XX_DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
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writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);
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/* DDR needs to be initialised @ 19.2 MHz
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/* DDR needs to be initialised @ 19.2 MHz
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* So put core DPLL in bypass mode
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* So put core DPLL in bypass mode
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@ -301,10 +303,10 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
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/* No IDLE: BUG in SDC */
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/* No IDLE: BUG in SDC */
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sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
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sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
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while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
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while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
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*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
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writel(0x0, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
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*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
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writel(0x0, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
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omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs);
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omap4_emif_config(OMAP44XX_EMIF1_BASE, ddr_regs);
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omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs);
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omap4_emif_config(OMAP44XX_EMIF2_BASE, ddr_regs);
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@ -313,13 +315,13 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
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omap4_lock_core_dpll_shadow(core);
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omap4_lock_core_dpll_shadow(core);
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/* Set DLL_OVERRIDE = 0 */
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/* Set DLL_OVERRIDE = 0 */
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*(volatile int*)CM_DLL_CTRL = 0x0;
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writel(0x0, CM_DLL_CTRL);
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delay(200);
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delay(200);
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/* Check for DDR PHY ready for EMIF1 & EMIF2 */
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/* Check for DDR PHY ready for EMIF1 & EMIF2 */
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while((((*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \
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while (((readl(OMAP44XX_EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) \
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|| (((*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04));
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|| ((readl(OMAP44XX_EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04));
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/* Reprogram the DDR PYHY Control register */
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/* Reprogram the DDR PYHY Control register */
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/* PHY control values */
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/* PHY control values */
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@ -331,9 +333,9 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
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/* No IDLE: BUG in SDC */
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/* No IDLE: BUG in SDC */
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//sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
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//sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
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//while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
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//while ((readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
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*(volatile int*)(OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
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writel(0x80000000, OMAP44XX_EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
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*(volatile int*)(OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
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writel(0x80000000, OMAP44XX_EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
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/*
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/*
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* DMM : DMM_LISA_MAP_0(Section_0)
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* DMM : DMM_LISA_MAP_0(Section_0)
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@ -347,8 +349,8 @@ void omap4_ddr_init(const struct ddr_regs *ddr_regs,
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reset_phy(OMAP44XX_EMIF1_BASE);
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reset_phy(OMAP44XX_EMIF1_BASE);
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reset_phy(OMAP44XX_EMIF2_BASE);
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reset_phy(OMAP44XX_EMIF2_BASE);
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*((volatile int *)0x80000000) = 0;
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writel(0, 0x80000000);
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*((volatile int *)0x80000080) = 0;
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writel(0, 0x80000080);
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}
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}
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void omap4_power_i2c_send(u32 r)
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void omap4_power_i2c_send(u32 r)
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