MIPS: mach-ar231x: add lowlevel init pbl macros
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Oleksij Rempel
Sascha Hauer
parent
24b0d2effd
commit
ed61198836
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#ifndef __ASM_MACH_AR2312_PBL_MACROS_H
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#define __ASM_MACH_AR2312_PBL_MACROS_H
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#include <asm/regdef.h>
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#include <mach/ar2312_regs.h>
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.macro pbl_ar2312_pll
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.set push
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.set noreorder
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mfc0 k0, CP0_STATUS
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li k1, ST0_NMI
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and k1, k1, k0
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bnez k1, pllskip
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nop
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/* Clear any prior AHB errors by reading both addr registers */
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li t0, KSEG1 | AR2312_PROCADDR
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lw zero, 0(t0)
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li t0, KSEG1 | AR2312_DMAADDR
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lw zero, 0(t0)
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pbl_sleep t2, 4000
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li t0, KSEG1 | AR2312_CLOCKCTL2
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lw t1, (t0)
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bgez t1, pllskip /* upper bit guaranteed non-0 at reset */
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nop
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/* For Viper 0xbc003064 register has to be programmed with 0x91000 to
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* get 180Mhz Processor clock
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* Set /2 clocking and turn OFF AR2312_CLOCKCTL2_STATUS_PLL_BYPASS.
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* Processor RESETs at this point; the CLOCKCTL registers retain
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* their new values across the reset.
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*/
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li t0, KSEG1 | AR2312_CLOCKCTL1
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li t1, AR2313_CLOCKCTL1_SELECTION
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sw t1, (t0)
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li t0, KSEG1 | AR2312_CLOCKCTL2
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li t1, AR2312_CLOCKCTL2_WANT_RESET
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sw t1, (t0) /* reset CPU */
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1: b 1b /* NOTREACHED */
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nop
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pllskip:
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.set pop
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.endm
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.macro pbl_ar2312_rst_uart0
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.set push
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.set noreorder
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li a0, KSEG1 | AR2312_RESET
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lw t0, 0(a0)
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and t0, ~AR2312_RESET_APB
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or t0, AR2312_RESET_UART0
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sw t0, 0(a0)
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lw zero, 0(a0) /* flush */
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and t0, ~AR2312_RESET_UART0
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sw t0, 0(a0)
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lw zero, 0(a0) /* flush */
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1: /* Use internal clocking */
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li a0, KSEG1 | AR2312_CLOCKCTL0
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lw t0, 0(a0)
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and t0, ~AR2312_CLOCKCTL_UART0
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sw t0, 0(a0)
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.set pop
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.endm
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.macro pbl_ar2312_x16_sdram
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.set push
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.set noreorder
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li a0, KSEG1 | AR2312_MEM_CFG0
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li a1, KSEG1 | AR2312_MEM_CFG1
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li a2, KSEG1 | AR2312_MEM_REF
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li a3, MEM_CFG1_E0 | (MEM_CFG1_AC_128 << MEM_CFG1_AC0_S)
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/* Set the I and M bits to issue an SDRAM nop */
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ori t0, a3, MEM_CFG1_M | MEM_CFG1_I
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sw t0, 0(a1) /* AR2312_MEM_CFG1 */
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pbl_sleep t2, 50
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/* Reset the M bit to issue an SDRAM PRE-ALL */
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ori t0, a3, MEM_CFG1_I
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sw t0, 0(a1) /* AR2312_MEM_CFG1 */
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sync
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/* Generate a refresh every 16 clocks (spec says 10) */
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li t0, 16 /* very fast refresh for now */
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sw t0, 0(a2) /* AR2312_MEM_REF */
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pbl_sleep t2, 5
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/* Set command write mode, and read SDRAM */
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ori t0, a3, MEM_CFG1_M
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sw t0, 0(a1) /* AR2312_MEM_CFG1 */
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sync
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li t0, KSEG1 | AR2312_SDRAM0
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or t0, 0x23000 /* 16bit burst */
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lw zero, 0(t0)
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/* Program configuration register */
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li t0, MEM_CFG0_C | MEM_CFG0_C2 | MEM_CFG0_R1 | \
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MEM_CFG0_B0 | MEM_CFG0_X
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sw t0, 0(a0) /* AR2312_MEM_CFG0 */
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sync
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li t0, AR2312_SDRAM_MEMORY_REFRESH_VALUE
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sw t0, 0(a2) /* AR2312_MEM_REF */
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sync
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/* Clear I and M and set cfg1 to the normal operational value */
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sw a3, 0(a1) /* AR2312_MEM_CFG1 */
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sync
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pbl_sleep t2, 10
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/* Now we need to set size of RAM to prevent some wired errors.
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* Since I do not have access to any board with two SDRAM chips, or
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* any was registered in the wild - we will support only one. */
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/* So, lets find the beef */
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li a0, KSEG1 | AR2312_MEM_CFG1
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li a1, KSEG1 | AR2312_SDRAM0
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li a2, 0xdeadbeef
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li t0, 0x200000
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li t1, MEM_CFG1_AC_2
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/* We will write some magic word to the beginning of RAM,
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* and see if it appears somewhere else. If yes, we made
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* a travel around the world. */
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/* But first of all save original state of the first RAM word. */
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lw a3, 0(a1)
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sw a2, 0(a1)
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find_the_beef:
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or t2, a1, t0
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lw t3, 0(t2)
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beq a2, t3, 1f
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nop
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sll t0, 1
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add t1, 1
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/* we should have some limit here. */
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blt t1, MEM_CFG1_AC_64, find_the_beef
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nop
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b make_beefsteak
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nop
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/* additional paranoid check */
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1:
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sw zero, 0(a1)
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lw t3, 0(t2)
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bne zero, t3, find_the_beef
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nop
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make_beefsteak:
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/* create new config for AR2312_MEM_CFG1 and overwrite it */
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sll t1, MEM_CFG1_AC0_S
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or t2, t1, MEM_CFG1_E0
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sw t2, 0(a0) /* AR2312_MEM_CFG1 */
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/* restore original state of the first RAM word */
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sw a3, 0(a1)
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.set pop
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.endm
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#endif /* __ASM_MACH_AR2312_PBL_MACROS_H */
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