ARM: i.MX25: Fix LCDC clocks
- Make sure the LCDC ipg clock is turned off during startup - register all LCDC clocks (ahb, ipg, per) and pass them to driver This is necessary because the LCDC doesn't have an enable bit. It just starts working once the clocks are turned on. If the registers have invalid values at that time the controller goes into some error state. So we have to make sure the clocks are turned off during startup and only turned on in the driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -55,7 +55,20 @@ enum mx25_clks {
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per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
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per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
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per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
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lcdc_per_gate, clk_max
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csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per,
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gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per,
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pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per,
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uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb,
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esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb,
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reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg,
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cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg,
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reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9,
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gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12,
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iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg,
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pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
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sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
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uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
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wdt_ipg, clk_max
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};
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static struct clk *clks[clk_max];
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@ -83,7 +96,7 @@ static int imx25_ccm_probe(struct device_d *dev)
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writel((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 13) | (1 << 14) |
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(1 << 15) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) |
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(1 << 26) | (1 << 29) | (1 << 31),
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(1 << 26) | (1 << 31),
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base + CCM_CGCR1);
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writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 10) | (1 << 13) | (1 << 14) |
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@ -132,7 +145,9 @@ static int imx25_ccm_probe(struct device_d *dev)
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clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6);
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clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6);
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clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6);
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clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per7", base + CCM_CGCR0, 7);
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clks[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", base + CCM_CGCR0, 24);
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clks[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", base + CCM_CGCR1, 29);
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clks[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", base + CCM_CGCR0, 7);
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clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL);
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@ -152,9 +167,9 @@ static int imx25_ccm_probe(struct device_d *dev)
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clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[lcdc_per_gate], MX25_LCDC_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[dummy], MX25_LCDC_BASE_ADDR, "ipg");
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clkdev_add_physbase(clks[dummy], MX25_LCDC_BASE_ADDR, "ahb");
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clkdev_add_physbase(clks[lcdc_ipg_per], MX25_LCDC_BASE_ADDR, "per");
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clkdev_add_physbase(clks[lcdc_ipg], MX25_LCDC_BASE_ADDR, "ipg");
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clkdev_add_physbase(clks[lcdc_ahb], MX25_LCDC_BASE_ADDR, "ahb");
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return 0;
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}
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