ARM i.MX31 pcm037: rewrite lowlevel init code in C
Tested with NOR and NAND boot. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
dfb2f22670
commit
f05392ac01
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@ -16,6 +16,6 @@
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#
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#
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obj-y += lowlevel_init.o
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pbl-y += lowlevel_init.o
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obj-y += lowlevel.o
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pbl-y += lowlevel.o
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obj-y += pcm037.o
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@ -0,0 +1,162 @@
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <mach/imx-nand.h>
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#include <asm/barebox-arm.h>
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#include <asm/system.h>
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#include <asm-generic/memory_layout.h>
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#include <asm-generic/sections.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/imx31-regs.h>
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#include <mach/imx-pll.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/esdctl.h>
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#ifdef CONFIG_NAND_IMX_BOOT
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static void __bare_init __naked insdram(void)
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{
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/* setup a stack to be able to call imx_nand_load_image() */
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arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
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imx_nand_load_image(_text, barebox_image_size);
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board_init_lowlevel_return();
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}
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#endif
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#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
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void __bare_init __naked reset(void)
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{
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uint32_t r;
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volatile int v;
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#ifdef CONFIG_NAND_IMX_BOOT
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int i;
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unsigned int *trg, *src;
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#endif
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common_reset();
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writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
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writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
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for (v = 0; v < 0x4000; v++);
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writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
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MX31_CCM_CCMR);
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writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
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MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
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writel(MX31_PDR0_CSI_PODF(0xff1) | \
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MX31_PDR0_PER_PODF(7) | \
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MX31_PDR0_HSP_PODF(3) | \
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MX31_PDR0_NFC_PODF(5) | \
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MX31_PDR0_IPG_PODF(1) | \
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MX31_PDR0_MAX_PODF(3) | \
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MX31_PDR0_MCU_PODF(0), \
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MX31_CCM_BASE_ADDR + MX31_CCM_PDR0);
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writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) |
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IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd),
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MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
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writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
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IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
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MX31_CCM_SPCTL);
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/*
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* Configure IOMUXC
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* Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched),
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* 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
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* (behaviour copied by sha, source unknown)
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*/
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writel(0, 0x43fac26c);
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writel(0, 0x43fac270);
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writel(0, 0x43fac274);
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writel(0x1000, 0x43fac27c);
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for (r = 0x43fac284; r <= 0x43fac2dc; r += 4)
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writel(0, r);
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x80000000 && r < 0xa0000000)
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board_init_lowlevel_return();
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#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
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#define ROWS0 ESDCTL0_ROW13
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#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
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#define ROWS0 ESDCTL0_ROW14
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#endif
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writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
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writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00);
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writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0x12344321, MX31_CSD0_BASE_ADDR);
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writel(0x12344321, MX31_CSD0_BASE_ADDR);
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writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33);
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writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000);
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writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR);
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writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
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#define ROWS1 ESDCTL0_ROW13
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#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
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#define ROWS1 ESDCTL0_ROW14
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#endif
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writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1);
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writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
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writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00);
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writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
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writel(0x12344321, MX31_CSD1_BASE_ADDR);
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writel(0x12344321, MX31_CSD1_BASE_ADDR);
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writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
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writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33);
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writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000);
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writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
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writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR);
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writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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#endif
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#ifdef CONFIG_NAND_IMX_BOOT
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/* skip NAND boot if not running from NFC space */
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r = get_pc();
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if (r < MX31_NFC_BASE_ADDR || r > MX31_NFC_BASE_ADDR + 0x800)
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board_init_lowlevel_return();
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src = (unsigned int *)MX31_NFC_BASE_ADDR;
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trg = (unsigned int *)_text;
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/* Move ourselves out of NFC SRAM */
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for (i = 0; i < 0x800 / sizeof(int); i++)
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*trg++ = *src++;
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/* Jump to SDRAM */
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r = (unsigned int)&insdram;
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__asm__ __volatile__("mov pc, %0" : : "r"(r));
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#else
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board_init_lowlevel_return();
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#endif
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}
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@ -1,170 +0,0 @@
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <mach/imx31-regs.h>
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#include <mach/imx-pll.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/esdctl.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define writeb(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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strb r1, [r0];
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.macro DELAY loops
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ldr r2, =\loops
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1:
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subs r2, r2, #1
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nop
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bcs 1b
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.endm
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.section ".text_bare_init","ax"
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.globl reset
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reset:
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common_reset r0
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writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR)
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writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
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DELAY 0x40000
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writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
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MX31_CCM_CCMR)
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writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
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MX31_CCM_BASE_ADDR + MX31_CCM_CCMR)
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writel(MX31_PDR0_CSI_PODF(0xff1) | \
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MX31_PDR0_PER_PODF(7) | \
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MX31_PDR0_HSP_PODF(3) | \
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MX31_PDR0_NFC_PODF(5) | \
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MX31_PDR0_IPG_PODF(1) | \
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MX31_PDR0_MAX_PODF(3) | \
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MX31_PDR0_MCU_PODF(0), \
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MX31_CCM_BASE_ADDR + MX31_CCM_PDR0)
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writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) |
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IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd),
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MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL)
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writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
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IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
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MX31_CCM_SPCTL)
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/* Configure IOMUXC
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* Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
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* (behaviour copied by sha, source unknown)
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*/
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mov r1, #0;
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ldr r0, =0x43FAC26C
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str r1, [r0], #4
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str r1, [r0], #4
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str r1, [r0], #0x10
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ldr r2, =0x43FAC2DC
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clear_iomux:
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str r1, [r0], #4
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cmp r0, r2
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bls clear_iomux
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writel(0x1000, 0x43FAC27C )/* CS2 CSD0) */
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0x80000000
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blo 1f
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cmp pc, #0x90000000
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bhs 1f
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b board_init_lowlevel_return
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1:
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#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
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#define ROWS0 ESDCTL0_ROW13
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#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
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#define ROWS0 ESDCTL0_ROW14
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#endif
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writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
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writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
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writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
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writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00)
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writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
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writel(0x12344321, MX31_CSD0_BASE_ADDR)
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writel(0x12344321, MX31_CSD0_BASE_ADDR)
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writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
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writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33)
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writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000)
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writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
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writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR)
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writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
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#define ROWS1 ESDCTL0_ROW13
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#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
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#define ROWS1 ESDCTL0_ROW14
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#endif
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writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1)
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writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
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writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00)
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writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
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writel(0x12344321, MX31_CSD1_BASE_ADDR)
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writel(0x12344321, MX31_CSD1_BASE_ADDR)
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writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
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writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33)
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writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000)
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writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1)
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writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR)
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writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC)
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#endif
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */
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ldr r0, =MX31_NFC_BASE_ADDR /* start of NFC SRAM */
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ldr r2, =MX31_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
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/* skip NAND boot if not running from NFC space */
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cmp pc, r0
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blo ret
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cmp pc, r2
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bhs ret
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/* Move ourselves out of NFC SRAM */
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ldr r1, =_text
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copy_loop:
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ldmia r0!, {r3-r9} /* copy from source address [r0] */
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stmia r1!, {r3-r9} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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ble copy_loop
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ldr pc, =1f /* Jump to SDRAM */
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1:
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b nand_boot /* Load barebox from NAND Flash */
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ret:
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#endif /* CONFIG_NAND_IMX_BOOT */
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b board_init_lowlevel_return
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