Add the basic support for the DIGI a9m2440 CPU card.
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
This commit is contained in:
Juergen Beisert
parent
27acfbda77
commit
f1ed0ae1c6
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@ -17,6 +17,7 @@ config ARCH_TEXT_BASE
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default 0x31fc0000 if MACH_A9M2410
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default 0x87f00000 if MACH_PCM043
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default 0xa7f00000 if MACH_PCA100
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default 0x33fc0000 if MACH_A9M2440
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default 0x23f00000 if MACH_MMCCPU
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config BOARDINFO
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@ -27,6 +28,7 @@ config BOARDINFO
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default "Freescale i.MX27 ADS" if MACH_IMX27ADS
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default "Phytec phyCORE-i.MX31" if MACH_PCM037
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default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260_EK
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default "Digi A9M2440" if MACH_A9M2440
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default "Ronetix PM9263" if MACH_PM9263
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default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
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default "Phytec phyCORE-i.MX35" if MACH_PCM043
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@ -206,6 +208,16 @@ config MACH_A9M2410
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Say Y here if you are using Digi's Connect Core 9M equipped
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with a Samsung S3C2410 Processor
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config MACH_A9M2440
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bool "Digi A9M2440"
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select CPU_S3C2440
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select MACH_HAS_LOWLEVEL_INIT
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select S3C24XX_PLL_INIT
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select S3C24XX_SDRAM_INIT
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help
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Say Y here if you are using Digi's Connect Core 9M equipped
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with a Samsung S3C2440 Processor
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config MACH_PCA100
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bool "phyCard-i.MX27"
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select ARCH_IMX27
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@ -24,6 +24,7 @@ board-$(CONFIG_MACH_PCM043) := pcm043
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board-$(CONFIG_MACH_A9M2410) := a9m2410
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board-$(CONFIG_MACH_PCA100) := phycard-i.MX27
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board-$(CONFIG_MACH_MMCCPU) := mmccpu
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board-$(CONFIG_MACH_A9M2440) := a9m2440
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# FIXME "cpu-y" never used on ARM!
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cpu-$(CONFIG_ARM920T) := arm920t
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@ -0,0 +1,229 @@
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#
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# Automatically generated make config: don't edit
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# U-Boot version: 2.0.0-rc9
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# Wed Jul 1 14:23:41 2009
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#
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CONFIG_ARCH_TEXT_BASE=0x33fc0000
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CONFIG_BOARDINFO="Digi A9M2440"
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# CONFIG_BOARD_LINKER_SCRIPT is not set
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CONFIG_GENERIC_LINKER_SCRIPT=y
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CONFIG_ARM=y
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CONFIG_ARM920T=y
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# CONFIG_MACH_MX1ADS is not set
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# CONFIG_MACH_SCB9328 is not set
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# CONFIG_MACH_PCM038 is not set
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# CONFIG_MACH_IMX21ADS is not set
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# CONFIG_MACH_IMX27ADS is not set
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# CONFIG_MACH_PCM043 is not set
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# CONFIG_MACH_FREESCALE_MX35_3STACK is not set
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# CONFIG_MACH_ECO920 is not set
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# CONFIG_MACH_NXDB500 is not set
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# CONFIG_MACH_PCM037 is not set
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# CONFIG_MACH_OMAP is not set
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# CONFIG_MACH_AT91SAM9260_EK is not set
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# CONFIG_MACH_PM9263 is not set
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# CONFIG_MACH_A9M2410 is not set
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CONFIG_MACH_A9M2440=y
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# CONFIG_MACH_PCA100 is not set
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# CONFIG_MACH_MMCCPU is not set
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CONFIG_ARCH_S3C24xx=y
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CONFIG_CPU_S3C2440=y
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#
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# Board specific settings
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#
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#
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# S3C24X0 Features
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#
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CONFIG_S3C24XX_LOW_LEVEL_INIT=y
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CONFIG_S3C24XX_PLL_INIT=y
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CONFIG_S3C24XX_SDRAM_INIT=y
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CONFIG_S3C24XX_NAND_BOOT=y
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#
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# Arm specific settings
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#
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CONFIG_CMD_ARM_CPUINFO=y
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CONFIG_CMDLINE_TAG=y
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CONFIG_SETUP_MEMORY_TAGS=y
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# CONFIG_INITRD_TAG is not set
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CONFIG_GREGORIAN_CALENDER=y
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CONFIG_HAS_KALLSYMS=y
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CONFIG_HAS_MODULES=y
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CONFIG_CMD_MEMORY=y
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CONFIG_ENV_HANDLING=y
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#
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# General Settings
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#
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CONFIG_LOCALVERSION_AUTO=y
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#
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# memory layout
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#
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CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
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CONFIG_TEXT_BASE=0x33fc0000
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CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
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CONFIG_MEMORY_LAYOUT_DEFAULT=y
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# CONFIG_MEMORY_LAYOUT_FIXED is not set
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CONFIG_STACK_SIZE=0x8000
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CONFIG_MALLOC_SIZE=0x400000
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CONFIG_BROKEN=y
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CONFIG_EXPERIMENTAL=y
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# CONFIG_MODULES is not set
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# CONFIG_KALLSYMS is not set
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CONFIG_MACH_HAS_LOWLEVEL_INIT=y
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CONFIG_MACH_DO_LOWLEVEL_INIT=y
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CONFIG_PROMPT="uboot:"
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CONFIG_BAUDRATE=38400
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CONFIG_LONGHELP=y
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CONFIG_CBSIZE=1024
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CONFIG_MAXARGS=16
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CONFIG_SHELL_HUSH=y
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# CONFIG_SHELL_SIMPLE is not set
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CONFIG_GLOB=y
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CONFIG_PROMPT_HUSH_PS2="> "
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CONFIG_CMDLINE_EDITING=y
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CONFIG_AUTO_COMPLETE=y
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CONFIG_DYNAMIC_CRC_TABLE=y
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CONFIG_ERRNO_MESSAGES=y
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CONFIG_TIMESTAMP=y
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CONFIG_CONSOLE_FULL=y
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CONFIG_CONSOLE_ACTIVATE_FIRST=y
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# CONFIG_OF_FLAT_TREE is not set
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CONFIG_PARTITION=y
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CONFIG_DEFAULT_ENVIRONMENT=y
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CONFIG_DEFAULT_ENVIRONMENT_PATH="board/a9m2440/env"
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#
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# Debugging
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#
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CONFIG_DEBUG_INFO=y
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# CONFIG_ENABLE_FLASH_NOISE is not set
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# CONFIG_ENABLE_PARTITION_NOISE is not set
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# CONFIG_ENABLE_DEVICE_NOISE is not set
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#
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# Commands
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#
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#
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# scripting
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#
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CONFIG_CMD_EDIT=y
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CONFIG_CMD_SLEEP=y
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CONFIG_CMD_SAVEENV=y
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CONFIG_CMD_LOADENV=y
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CONFIG_CMD_EXPORT=y
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CONFIG_CMD_PRINTENV=y
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CONFIG_CMD_READLINE=y
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CONFIG_CMD_TRUE=y
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CONFIG_CMD_FALSE=y
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#
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# file commands
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#
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CONFIG_CMD_LS=y
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CONFIG_CMD_RM=y
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CONFIG_CMD_CAT=y
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CONFIG_CMD_MKDIR=y
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CONFIG_CMD_RMDIR=y
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CONFIG_CMD_CP=y
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CONFIG_CMD_PWD=y
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CONFIG_CMD_CD=y
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CONFIG_CMD_MOUNT=y
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CONFIG_CMD_UMOUNT=y
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#
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# console
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#
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CONFIG_CMD_CLEAR=y
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CONFIG_CMD_ECHO=y
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# CONFIG_CMD_SPLASH is not set
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#
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# memory
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#
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADY is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_CRC=y
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CONFIG_CMD_MTEST=y
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# CONFIG_CMD_MTEST_ALTERNATIVE is not set
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#
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# flash
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#
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CONFIG_CMD_FLASH=y
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CONFIG_CMD_NAND=y
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#
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# booting
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#
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CONFIG_CMD_BOOTM=y
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# CONFIG_CMD_BOOTM_ZLIB is not set
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# CONFIG_CMD_BOOTM_BZLIB is not set
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# CONFIG_CMD_BOOTM_SHOW_TYPE is not set
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CONFIG_CMD_RESET=y
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CONFIG_CMD_GO=y
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CONFIG_CMD_TIMEOUT=y
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CONFIG_CMD_PARTITION=y
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CONFIG_CMD_TEST=y
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CONFIG_CMD_VERSION=y
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CONFIG_CMD_HELP=y
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CONFIG_CMD_DEVINFO=y
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CONFIG_NET=y
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CONFIG_NET_BOOTP=y
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CONFIG_NET_DHCP=y
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# CONFIG_NET_RARP is not set
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# CONFIG_NET_SNTP is not set
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# CONFIG_NET_NFS is not set
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CONFIG_NET_PING=y
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CONFIG_NET_TFTP=y
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#
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# Drivers
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#
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#
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# serial drivers
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#
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# CONFIG_DRIVER_SERIAL_NS16550 is not set
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CONFIG_DRIVER_SERIAL_S3C24X0=y
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# CONFIG_DRIVER_SERIAL_S3C24X0_AUTOSYNC is not set
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CONFIG_MIIPHY=y
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#
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# Network drivers
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#
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# CONFIG_DRIVER_NET_SMC911X is not set
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CONFIG_DRIVER_NET_SMC91111=y
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#
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# SPI drivers
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#
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# CONFIG_SPI is not set
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#
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# flash drivers
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#
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# CONFIG_DRIVER_CFI is not set
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# CONFIG_DRIVER_CFI_OLD is not set
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CONFIG_NAND=y
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CONFIG_NAND_S3C24X0=y
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# CONFIG_MTD_NAND_VERIFY_WRITE is not set
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# CONFIG_MTD_NAND_ECC_SMC is not set
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CONFIG_MTD_NAND_IDS=y
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# CONFIG_MTD_NAND_DISKONCHIP is not set
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# CONFIG_USB is not set
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#
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# Filesystem support
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#
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# CONFIG_FS_CRAMFS is not set
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CONFIG_FS_RAMFS=y
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CONFIG_FS_DEVFS=y
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CONFIG_CRC32=y
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# CONFIG_GENERIC_FIND_NEXT_BIT is not set
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@ -0,0 +1,3 @@
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obj-y += lowlevel_init.o
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obj-y += a9m2440.o
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@ -0,0 +1,254 @@
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/*
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* Copyright (C) 2009 Juergen Beisert, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/**
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* @file
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* @brief a9m2440 Specific Board Initialization routines
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*
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*/
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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#include <asm/armlinux.h>
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#include <asm/mach-types.h>
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#include <partition.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <asm/arch/s3c24x0-iomap.h>
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#include <asm/arch/s3c24x0-nand.h>
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static struct device_d sdram_dev = {
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.name = "ram",
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.id = "ram0",
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.map_base = CS6_BASE,
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.type = DEVICE_TYPE_DRAM,
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};
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static struct s3c24x0_nand_platform_data nand_info = {
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.nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
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};
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static struct device_d nand_dev = {
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.name = "s3c24x0_nand",
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.map_base = S3C24X0_NAND_BASE,
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.platform_data = &nand_info,
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};
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/*
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* SMSC 91C111 network controller on the baseboard
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* connected to CS line 1 and interrupt line
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* GPIO3, data width is 32 bit
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*/
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static struct device_d network_dev = {
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.name = "smc91c111",
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.id = "eth0",
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.map_base = CS1_BASE + 0x300,
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.size = 16,
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.type = DEVICE_TYPE_ETHER,
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};
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static int a9m2440_devices_init(void)
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{
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uint32_t reg;
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struct device_d *nand, *dev;
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/*
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* detect the current memory size
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* Note: On this card the second SDRAM page is not used
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*/
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reg = readl(BANKSIZE);
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switch (reg &= 0x7) {
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case 0:
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sdram_dev.size = 32 * 1024 * 1024;
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break;
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case 1:
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sdram_dev.size = 64 * 1024 * 1024;
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break;
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case 2:
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sdram_dev.size = 128 * 1024 * 1024;
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break;
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case 4:
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sdram_dev.size = 2 * 1024 * 1024;
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break;
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case 5:
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sdram_dev.size = 4 * 1024 * 1024;
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break;
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case 6:
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sdram_dev.size = 8 * 1024 * 1024;
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break;
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case 7:
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sdram_dev.size = 16 * 1024 * 1024;
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break;
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}
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/* both banks are present */
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sdram_dev.size <<= 1;
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/* ---------- configure the GPIOs ------------- */
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writel(0x007FFFFF, GPACON);
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writel(0x00000000, GPCCON);
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writel(0x00000000, GPCUP);
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writel(0x00000000, GPDCON);
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writel(0x00000000, GPDUP);
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writel(0xAAAAAAAA, GPECON);
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writel(0x0000E03F, GPEUP);
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writel(0x00000000, GPBCON); /* all inputs */
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writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */
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writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
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writel(0x000000FF, GPFUP);
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writel(readl(GPGDAT) | 0x1010, GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */
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writel(0x0100A93A, GPGCON); /* switch on USB device */
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writel(0x0000F000, GPGUP);
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writel(0x0029FAAA, GPHCON);
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writel((1 << 12) | (0 << 11), GPJDAT);
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writel(0x0016aaaa, GPJCON);
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writel(~((0<<12)| (1<<11)), GPJUP);
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writel((0 << 12) | (0 << 11), GPJDAT);
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writel(0x0016aaaa, GPJCON);
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writel(0x00001fff, GPJUP);
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writel(0x00000000, DSC0);
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writel(0x00000000, DSC1);
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/*
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* USB port1 normal, USB port0 normal, USB1 pads for device
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* PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
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*/
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writel(0x00140, MISCCR);
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/* ----------- configure the access to the outer space ---------- */
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reg = readl(BWSCON);
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/* CS#1 to access the network controller */
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reg &= ~0xf0;
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reg |= 0xe0;
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writel(0x1350, BANKCON1);
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/* CS#2 to the dual 16550 UART */
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reg &= ~0xf00;
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reg |= 0x400;
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writel(0x0d50, BANKCON2);
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writel(reg, BWSCON);
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/* release the reset signal to the network and UART device */
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reg = readl(MISCCR);
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reg |= 0x10000;
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writel(reg, MISCCR);
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/* ----------- the devices the boot loader should work with -------- */
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register_device(&nand_dev);
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register_device(&sdram_dev);
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register_device(&network_dev);
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#ifdef CONFIG_NAND
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/* ----------- add some vital partitions -------- */
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nand = get_device_by_path("/dev/nand0");
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if (nand) {
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dev = dev_add_partition(nand, 0x00000, 0x40000,
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PARTITION_FIXED, "self_raw");
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if (dev) {
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dev_add_bb_dev(dev, "self0");
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dev = dev_add_partition(nand, 0x40000, 0x20000,
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PARTITION_FIXED, "env_raw");
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if (dev)
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dev_add_bb_dev(dev, "env0");
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}
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}
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#endif
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armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
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armlinux_set_architecture(698); /* A9M2440 */
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return 0;
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}
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device_initcall(a9m2440_devices_init);
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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void __bare_init nand_boot(void)
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{
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
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}
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#endif
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|
||||
static struct device_d a9m2440_serial_device = {
|
||||
.name = "s3c24x0_serial",
|
||||
.id = "cs0",
|
||||
.map_base = UART1_BASE,
|
||||
.size = UART1_SIZE,
|
||||
.type = DEVICE_TYPE_CONSOLE,
|
||||
};
|
||||
|
||||
static int a9m2440_console_init(void)
|
||||
{
|
||||
register_device(&a9m2440_serial_device);
|
||||
return 0;
|
||||
}
|
||||
|
||||
console_initcall(a9m2440_console_init);
|
||||
|
||||
/** @page a9m2440 DIGI's a9m2440
|
||||
|
||||
This CPU card is based on a Samsung S3C2440 CPU. The card is shipped with:
|
||||
|
||||
- S3C2440\@400 MHz or 533 MHz (ARM920T/ARMv4T)
|
||||
- 16.9344 MHz crystal reference
|
||||
- SDRAM 64 MiB
|
||||
- Samsung K4M563233E-EE1H
|
||||
- 2M x 32Bit x 4 Banks Mobile SDRAM
|
||||
- 90 pin FBGA
|
||||
- CL3\@133MHz, CL2\@100MHz (CAS/RAS delay 19ns)
|
||||
- four banks
|
||||
- 32 bit data bits
|
||||
- row address size is 11
|
||||
- Row cycle time: 69ns
|
||||
- collumn address size is 9 bits
|
||||
- Extended temperature range (-25°C...85°C)
|
||||
- 64ms refresh period (4k)
|
||||
- NAND Flash 64 MiB
|
||||
- Samsung KM29U512T
|
||||
- 64MiB 3,3V 8-bit
|
||||
- ID: 0xEC, 0x76, 0x??, 0xBD
|
||||
- 30ns/40ns/20ns
|
||||
- I2C interface, 100KHz and 400KHz
|
||||
- Real Time Clock
|
||||
- Dallas DS1337
|
||||
- address 0xD0
|
||||
- LCD interface
|
||||
- Touch Screen interface
|
||||
- Camera interface
|
||||
- I2S interface
|
||||
- AC97 Audio-CODEC interface
|
||||
- SD card interface
|
||||
- 3 serial RS232 interfaces
|
||||
- Host and device USB interface, USB1.1 compliant
|
||||
- Ethernet interface
|
||||
- 10Mbps, Cirrus Logic, CS8900A (on the CPU card) or
|
||||
- 10/100Mbps, SMSC 91C111 (on the baseboard)
|
||||
- SPI interface
|
||||
- JTAG interface
|
||||
|
||||
*/
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card
|
||||
*/
|
||||
/* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/**
|
||||
* The external clock reference is a 16.9344 MHz crystal
|
||||
*/
|
||||
#define S3C24XX_CLOCK_REFERENCE 16934400
|
||||
|
||||
/**
|
||||
* Define the main clock configuration to be used in register CLKDIVN
|
||||
*
|
||||
* We must limit the frequency of the connected SDRAMs with the clock ratio
|
||||
* setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz
|
||||
*/
|
||||
#define BOARD_SPECIFIC_CLKDIVN 0x05
|
||||
|
||||
/**
|
||||
* Define the MPLL configuration to be used in register MPLLCON
|
||||
*
|
||||
* We want the MPLL to run at 399.65 MHz
|
||||
*/
|
||||
#define BOARD_SPECIFIC_MPLL ((0x6e << 12) + (3 << 4) + 1)
|
||||
|
||||
/**
|
||||
* Define the UPLL configuration to be used in register UPLLCON
|
||||
*
|
||||
* We want the UPLL to run at 47.98 MHz
|
||||
*/
|
||||
#define BOARD_SPECIFIC_UPLL ((0x3c << 12) + (2 << 4) + 2)
|
||||
|
||||
/*
|
||||
* SDRAM configuration for Samsung K4M563233E
|
||||
* - 2M x 32Bit x 4 Banks Mobile SDRAM
|
||||
* - 90 pin FBGA
|
||||
* - CL2@100MHz
|
||||
*/
|
||||
/*
|
||||
* SDRAM uses 32bit width
|
||||
*/
|
||||
#define BOARD_SPECIFIC_BWSCON ((0x02 << 24) + (0x02 << 28))
|
||||
/*
|
||||
* 32MiB SDRAM in bank6
|
||||
* - MT = 11 (= sync dram type)
|
||||
* - Trcd = 00 (= CL2)
|
||||
* - SCAN = 01 (= 9 bit collumns)
|
||||
*/
|
||||
#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + 0x1)
|
||||
/*
|
||||
* 32MiB SDRAM in bank7
|
||||
* - MT = 11 (= sync dram type)
|
||||
* - Trcd = 00 (= CL2)
|
||||
* - SCAN = 01 (= 9 bit collumns)
|
||||
*/
|
||||
#define BOARD_SPECIFIC_BANKCON7 ((0x3 << 15) + (0x0 << 2) + 0x1)
|
||||
/*
|
||||
* SDRAM refresh settings
|
||||
* - REFEN = 1 (= refresh enabled)
|
||||
* - TREFMD = 0 (= auto refresh)
|
||||
* - Trp = 00 (= 2 RAS precharge clocks)
|
||||
* - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
|
||||
* - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
|
||||
*/
|
||||
#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
|
||||
/*
|
||||
* SDRAM banksize
|
||||
* - BURST_EN = 1 (= burst mode enabled)
|
||||
* - SCKE_EN = 1 (= SDRAM SCKE enabled)
|
||||
* - SCLK_EN = 1 (= clock active only during accesses)
|
||||
* - BK67MAP = 000 (= 32MiB)
|
||||
*/
|
||||
#define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (1 << 4) + 0)
|
||||
/*
|
||||
* SDRAM mode register bank6
|
||||
* CL = 010 (= 2 clocks)
|
||||
*/
|
||||
#define BOARD_SPECIFIC_MRSRB6 (0x2 << 4)
|
||||
/*
|
||||
* SDRAM mode register bank7
|
||||
* CL = 010 (= 2 clocks)
|
||||
*/
|
||||
#define BOARD_SPECIFIC_MRSRB7 (0x2 << 4)
|
||||
|
||||
/*
|
||||
* Flash access timings
|
||||
* Tacls = 0ns (but 20ns data setup time)
|
||||
* Twrph0 = 25ns (write) 35ns (read)
|
||||
* Twrph1 = 10ns (10ns data hold time)
|
||||
* Read cycle time = 50ns
|
||||
*
|
||||
* Assumed HCLK is 100MHz
|
||||
* Tacls = 1 (-> 20ns)
|
||||
* Twrph0 = 3 (-> 40ns)
|
||||
* Twrph1 = 1 (-> 20ns)
|
||||
* Cycle time = 80ns
|
||||
*/
|
||||
#define A9M2440_TACLS 1
|
||||
#define A9M2440_TWRPH0 3
|
||||
#define A9M2440_TWRPH1 1
|
||||
|
||||
/* needed in the generic NAND boot code only */
|
||||
#ifdef CONFIG_S3C24XX_NAND_BOOT
|
||||
# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
#!/bin/sh
|
||||
|
||||
if [ -z "$part" -o -z "$image" ]; then
|
||||
echo "define \$part and \$image"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [ \! -e "$part" ]; then
|
||||
echo "Partition $part does not exist"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [ $# = 1 ]; then
|
||||
image=$1
|
||||
fi
|
||||
|
||||
if [ x$ip = xdhcp ]; then
|
||||
dhcp
|
||||
fi
|
||||
|
||||
ping $eth0.serverip
|
||||
if [ $? -ne 0 ] ; then
|
||||
echo "update aborted"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
unprotect $part
|
||||
|
||||
echo
|
||||
echo "erasing partition $part"
|
||||
erase $part
|
||||
|
||||
echo
|
||||
echo "flashing $image to $part"
|
||||
echo
|
||||
tftp $image $part
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
#!/bin/sh
|
||||
|
||||
. /env/config
|
||||
|
||||
if [ x$1 = xnand ]; then
|
||||
root=nand
|
||||
kernel=nand
|
||||
fi
|
||||
|
||||
if [ x$1 = xnet ]; then
|
||||
root=net
|
||||
kernel=net
|
||||
fi
|
||||
|
||||
if [ x$ip = xdhcp ]; then
|
||||
bootargs="$bootargs ip=dhcp"
|
||||
else
|
||||
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
|
||||
fi
|
||||
|
||||
if [ x$root = xnand ]; then
|
||||
bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
|
||||
else
|
||||
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
|
||||
fi
|
||||
|
||||
bootargs="$bootargs mtdparts=\"NAND 64MiB 3,3V 8-bit:$nand_parts\""
|
||||
|
||||
if [ x$kernel = xnet ]; then
|
||||
if [ x$ip = xdhcp ]; then
|
||||
dhcp
|
||||
fi
|
||||
tftp $uimage uImage || exit 1
|
||||
bootm uImage
|
||||
else
|
||||
bootm /dev/nand0.kernel.bb
|
||||
fi
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
nand -a /dev/nand0.*
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
#!/bin/sh
|
||||
|
||||
PATH=/env/bin
|
||||
export PATH
|
||||
|
||||
. /env/config
|
||||
|
||||
if [ -e /dev/nand0 ]; then
|
||||
addpart /dev/nand0 $nand_parts
|
||||
|
||||
# Uh, oh, hush first expands wildcards and then starts executing
|
||||
# commands. What a bug!
|
||||
source /env/bin/hush_hack
|
||||
fi
|
||||
|
||||
if [ -z $eth0.ethaddr ]; then
|
||||
while [ -z $eth0.ethaddr ]; do
|
||||
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
|
||||
done
|
||||
echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
|
||||
fi
|
||||
|
||||
echo
|
||||
echo -n "Hit any key to stop autoboot: "
|
||||
timeout -a $autoboot_timeout
|
||||
if [ $? != 0 ]; then
|
||||
echo
|
||||
echo "type update_kernel [<imagename>] to update kernel into flash"
|
||||
echo "type update_root [<imagename>] to update rootfs into flash"
|
||||
echo
|
||||
exit
|
||||
fi
|
||||
|
||||
boot
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
#!/bin/sh
|
||||
|
||||
. /env/config
|
||||
|
||||
part=/dev/nand0.kernel.bb
|
||||
|
||||
if [ x$1 = x ]; then
|
||||
image=$uimage
|
||||
else
|
||||
image=$1
|
||||
fi
|
||||
|
||||
. /env/bin/_update $image
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#!/bin/sh
|
||||
|
||||
. /env/config
|
||||
|
||||
if [ x$1 = x ]; then
|
||||
image=$jffs2
|
||||
else
|
||||
image=$1
|
||||
fi
|
||||
|
||||
. /env/bin/_update $image
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
#!/bin/sh
|
||||
|
||||
# can be either 'net' or 'nand''
|
||||
kernel=net
|
||||
root=net
|
||||
|
||||
uimage=uImage-a9m2440
|
||||
jffs2=root-a9m2440.jffs2
|
||||
|
||||
autoboot_timeout=3
|
||||
|
||||
nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2440/root"
|
||||
bootargs="console=ttySAC0,38400"
|
||||
|
||||
nand_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
|
||||
rootpart_nand="/dev/mtdblock3"
|
||||
|
||||
# use 'dhcp' to do dhcp in uboot and in kernel
|
||||
#ip=dhcp
|
||||
|
||||
# or set your networking parameters here
|
||||
eth0.ipaddr=192.168.42.32
|
||||
eth0.netmask=255.255.0.0
|
||||
eth0.gateway=192.168.23.1
|
||||
eth0.serverip=192.168.23.2
|
||||
eth0.ethaddr=00:04:f3:00:06:35
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch/s3c24x0-iomap.h>
|
||||
|
||||
.section ".text_bare_init.board_init_lowlevel","ax"
|
||||
|
||||
.globl board_init_lowlevel
|
||||
board_init_lowlevel:
|
||||
|
||||
mov r10, lr /* save the link register */
|
||||
|
||||
bl s3c24x0_disable_wd
|
||||
|
||||
/* skip everything here if we are already running from SDRAM */
|
||||
cmp pc, #S3C24X0_SDRAM_BASE
|
||||
blo 1f
|
||||
cmp pc, #S3C24X0_SDRAM_END
|
||||
bhs 1f
|
||||
|
||||
mov pc, r10
|
||||
|
||||
/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
|
||||
1:
|
||||
bl s3c24x0_pll_init
|
||||
|
||||
bl s3c24x0_sdram_init
|
||||
|
||||
#ifdef CONFIG_S3C24XX_NAND_BOOT
|
||||
mov lr, r10 /* restore the link register */
|
||||
/* up to here we are running from the internal SRAM area */
|
||||
b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
|
||||
#else
|
||||
mov pc, r10
|
||||
#endif
|
||||
Loading…
Reference in New Issue