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Add support for Eukrea CPUIMX35 

this modules is based on Freescale's i.MX357 CPU, with 128MB of
mDDR, 256 MB NAND, and ethernet PHY.

Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Eric Benard 2010-06-10 09:43:02 +02:00 committed by Sascha Hauer
parent c985627227
commit f2fdfe875f
16 changed files with 1112 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Makefile
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@ -63,6 +63,7 @@ board-$(CONFIG_MACH_EDB9315) := edb93xx
board-$(CONFIG_MACH_EDB9315A) := edb93xx
board-$(CONFIG_MACH_EUKREA_CPUIMX25) := eukrea_cpuimx25
board-$(CONFIG_MACH_EUKREA_CPUIMX27) := eukrea_cpuimx27
board-$(CONFIG_MACH_EUKREA_CPUIMX35) := eukrea_cpuimx35
board-$(CONFIG_MACH_FREESCALE_MX25_3STACK) := freescale-mx25-3-stack
board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack
board-$(CONFIG_MACH_IMX21ADS) := imx21ads

254
arch/arm/configs/eukrea_cpuimx35_defconfig Normal file
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@ -0,0 +1,254 @@
#
# Automatically generated make config: don't edit
# barebox version: 2010.06.0
# Mon Jun 7 18:25:47 2010
#
# CONFIG_BOARD_LINKER_SCRIPT is not set
CONFIG_GENERIC_LINKER_SCRIPT=y
CONFIG_ARM=y
#
# System Type
#
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_AT91RM9200 is not set
# CONFIG_ARCH_EP93XX is not set
CONFIG_ARCH_IMX=y
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_S3C24xx is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_V6=y
CONFIG_CPU_32v6=y
#
# processor features
#
CONFIG_ARCH_HAS_L2X0=y
CONFIG_CACHE_L2X0=y
CONFIG_ARCH_TEXT_BASE=0x87f00000
CONFIG_BOARDINFO="Eukrea CPUIMX35"
CONFIG_ARCH_HAS_FEC_IMX=y
CONFIG_ARCH_IMX_INTERNAL_BOOT=y
#
# Freescale i.MX System-on-Chip
#
# CONFIG_ARCH_IMX1 is not set
# CONFIG_ARCH_IMX21 is not set
# CONFIG_ARCH_IMX25 is not set
# CONFIG_ARCH_IMX27 is not set
# CONFIG_ARCH_IMX31 is not set
CONFIG_ARCH_IMX35=y
CONFIG_MACH_EUKREA_CPUIMX35=y
# CONFIG_MACH_FREESCALE_MX35_3STACK is not set
# CONFIG_MACH_PCM043 is not set
#
# Board specific settings
#
#
# i.MX specific settings
#
# CONFIG_IMX_CLKO is not set
# CONFIG_AEABI is not set
#
# Arm specific settings
#
CONFIG_CMD_ARM_CPUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_GREGORIAN_CALENDER=y
CONFIG_HAS_KALLSYMS=y
CONFIG_HAS_MODULES=y
CONFIG_CMD_MEMORY=y
CONFIG_ENV_HANDLING=y
CONFIG_GENERIC_GPIO=y
#
# General Settings
#
CONFIG_LOCALVERSION_AUTO=y
#
# memory layout
#
CONFIG_HAVE_MMU=y
CONFIG_MMU=y
CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
CONFIG_TEXT_BASE=0x87f00000
CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
CONFIG_MEMORY_LAYOUT_DEFAULT=y
# CONFIG_MEMORY_LAYOUT_FIXED is not set
CONFIG_STACK_SIZE=0x8000
CONFIG_MALLOC_SIZE=0x800000
# CONFIG_BROKEN is not set
# CONFIG_EXPERIMENTAL is not set
CONFIG_MACH_HAS_LOWLEVEL_INIT=y
CONFIG_MACH_DO_LOWLEVEL_INIT=y
CONFIG_PROMPT="barebox:"
CONFIG_BAUDRATE=115200
CONFIG_LONGHELP=y
CONFIG_CBSIZE=1024
CONFIG_MAXARGS=16
CONFIG_SHELL_HUSH=y
# CONFIG_SHELL_SIMPLE is not set
CONFIG_GLOB=y
CONFIG_PROMPT_HUSH_PS2="> "
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_ERRNO_MESSAGES=y
CONFIG_TIMESTAMP=y
CONFIG_CONSOLE_FULL=y
CONFIG_CONSOLE_ACTIVATE_FIRST=y
# CONFIG_OF_FLAT_TREE is not set
# CONFIG_PARTITION is not set
# CONFIG_DEFAULT_ENVIRONMENT is not set
#
# Debugging
#
# CONFIG_DEBUG_INFO is not set
# CONFIG_ENABLE_FLASH_NOISE is not set
# CONFIG_ENABLE_PARTITION_NOISE is not set
# CONFIG_ENABLE_DEVICE_NOISE is not set
#
# Commands
#
#
# scripting
#
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TRUE=y
CONFIG_CMD_FALSE=y
#
# file commands
#
CONFIG_CMD_LS=y
CONFIG_CMD_RM=y
CONFIG_CMD_CAT=y
CONFIG_CMD_MKDIR=y
CONFIG_CMD_RMDIR=y
CONFIG_CMD_CP=y
CONFIG_CMD_PWD=y
CONFIG_CMD_CD=y
CONFIG_CMD_MOUNT=y
CONFIG_CMD_UMOUNT=y
#
# console
#
CONFIG_CMD_CLEAR=y
CONFIG_CMD_ECHO=y
CONFIG_CMD_ECHO_E=y
#
# memory
#
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_MTEST=y
# CONFIG_CMD_MTEST_ALTERNATIVE is not set
#
# flash
#
# CONFIG_CMD_FLASH is not set
#
# booting
#
CONFIG_CMD_BOOTM=y
# CONFIG_CMD_BOOTM_ZLIB is not set
# CONFIG_CMD_BOOTM_BZLIB is not set
# CONFIG_CMD_BOOTM_SHOW_TYPE is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_BOOTU=y
# CONFIG_CMD_LINUX16 is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_TEST=y
CONFIG_CMD_VERSION=y
CONFIG_CMD_HELP=y
CONFIG_CMD_DEVINFO=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
# CONFIG_NET_RARP is not set
# CONFIG_NET_NFS is not set
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
#
# Drivers
#
#
# serial drivers
#
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
#
# Network drivers
#
# CONFIG_DRIVER_NET_SMC911X is not set
# CONFIG_DRIVER_NET_SMC91111 is not set
CONFIG_DRIVER_NET_FEC_IMX=y
#
# SPI drivers
#
# CONFIG_SPI is not set
# CONFIG_I2C is not set
#
# flash drivers
#
# CONFIG_DRIVER_CFI is not set
CONFIG_NAND=y
CONFIG_NAND_IMX=y
# CONFIG_NAND_IMX_BOOT is not set
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_ATA is not set
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX_IPU=y
#
# Filesystem support
#
# CONFIG_FS_CRAMFS is not set
CONFIG_FS_RAMFS=y
CONFIG_FS_DEVFS=y
CONFIG_CRC32=y
CONFIG_CRC16=y
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
CONFIG_PROCESS_ESCAPE_SEQUENCE=y
CONFIG_LZO_DECOMPRESS=y

11
arch/arm/mach-imx/Kconfig
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@ -4,6 +4,7 @@ config ARCH_TEXT_BASE
hex
default 0x83f00000 if MACH_EUKREA_CPUIMX25
default 0xa0000000 if MACH_EUKREA_CPUIMX27
default 0x87f00000 if MACH_EUKREA_CPUIMX35
default 0x08f00000 if MACH_MX1ADS
default 0xc0000000 if MACH_IMX21ADS
default 0xa0000000 if MACH_IMX27ADS
@ -19,6 +20,7 @@ config ARCH_TEXT_BASE
config BOARDINFO
default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
default "Eukrea CPUIMX27" if MACH_EUKREA_CPUIMX27
default "Eukrea CPUIMX35" if MACH_EUKREA_CPUIMX35
default "Freescale i.MX21 ADS" if MACH_IMX21ADS
default "Freescale i.MX27 ADS" if MACH_IMX27ADS
default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
@ -223,6 +225,15 @@ choice
prompt "i.MX35 Board Type"
config MACH_EUKREA_CPUIMX35
bool "EUKREA CPUIMX35"
select HAVE_MMU
select MACH_HAS_LOWLEVEL_INIT
select ARCH_HAS_L2X0
help
Say Y here if you are using Eukrea's CPUIMX35 equipped
with a Freescale i.MX35 Processor
config MACH_FREESCALE_MX35_3STACK
bool "Freescale MX35 3stack"
select HAS_CFI

25
board/eukrea_cpuimx35/Makefile Normal file
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@ -0,0 +1,25 @@
#
# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
obj-y += lowlevel.o
obj-y += eukrea_cpuimx35.o
obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o

23
board/eukrea_cpuimx35/config.h Normal file
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@ -0,0 +1,23 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MX35_HCLK_FREQ 24000000
#endif /* __CONFIG_H */

36
board/eukrea_cpuimx35/env/bin/_update vendored Normal file
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@ -0,0 +1,36 @@
#!/bin/sh
if [ -z "$part" -o -z "$image" ]; then
echo "define \$part and \$image"
exit 1
fi
if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
if [ $# = 1 ]; then
image=$1
fi
if [ x$ip = xdhcp ]; then
dhcp
fi
ping $eth0.serverip
if [ $? -ne 0 ] ; then
echo "update aborted"
exit 1
fi
unprotect $part
echo
echo "erasing partition $part"
erase $part
echo
echo "flashing $image to $part"
echo
tftp $image $part

52
board/eukrea_cpuimx35/env/bin/boot vendored Normal file
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@ -0,0 +1,52 @@
#!/bin/sh
. /env/config
if [ x$1 = xjffS2 ]; then
root=jffs2
kernel=nand
fi
if [ x$1 = xubifs ]; then
root=ubifs
kernel=nand
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
if [ x$ip = xoff ]; then
bootargs="$bootargs ip=off"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
fi
if [ x$root = xjffs2 ]; then
bootargs="$bootargs root=/dev/mtdblock$rootpartnum_nand rootfstype=jffs2"
fi
if [ x$root = xubifs ]; then
bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum_nand rootfstype=ubifs"
fi
if [ x$root = xnet ]; then
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
fi
bootargs="$bootargs mtdparts=mxc_nand:$nand_parts"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage || exit 1
bootm uImage
else
bootm /dev/nand0.kernel.bb
fi

1
board/eukrea_cpuimx35/env/bin/hush_hack vendored Normal file
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@ -0,0 +1 @@
nand -a /dev/nand0.*

41
board/eukrea_cpuimx35/env/bin/init vendored Normal file
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@ -0,0 +1,41 @@
#!/bin/sh
PATH=/env/bin
export PATH
. /env/config
if [ -e /dev/nand0 ]; then
addpart /dev/nand0 $nand_parts
# Uh, oh, hush first expands wildcards and then starts executing
# commands. What a bug!
source /env/bin/hush_hack
fi
if [ -f /env/logo.bmp ]; then
bmp /env/logo.bmp
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
bmp /logo.bmp
fi
if [ -z $eth0.ethaddr ]; then
while [ -z $eth0.ethaddr ]; do
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
done
echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
saveenv
fi
echo
echo -n "Hit any key to stop autoboot: "
timeout -a $autoboot_timeout
if [ $? != 0 ]; then
echo
echo "type update_kernel [<imagename>] to update kernel into flash"
echo "type update_root [<imagename>] to update rootfs into flash"
echo
exit
fi
boot

8
board/eukrea_cpuimx35/env/bin/update_kernel vendored Normal file
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@ -0,0 +1,8 @@
#!/bin/sh
. /env/config
image=$uimage
part=/dev/nand0.kernel.bb
. /env/bin/_update $1

8
board/eukrea_cpuimx35/env/bin/update_root vendored Normal file
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@ -0,0 +1,8 @@
#!/bin/sh
. /env/config
image=$rootfs
part=/dev/nand0.root.bb
. /env/bin/_update $1

27
board/eukrea_cpuimx35/env/config vendored Normal file
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@ -0,0 +1,27 @@
#!/bin/sh
# can be either 'net' or 'nand''
kernel=nand
root=ubifs
basedir=cpuimx35
uimage=$basedir/uImage
rootfs=$basedir/rootfs
autoboot_timeout=1
nfsroot=""
bootargs="console=ttymxc0,115200"
nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)"
rootpartnum_nand=3
ubiroot="eukrea-cpuimx35-rootfs"
# use 'dhcp' to do dhcp in barebox and in kernel
ip=off
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d

343
board/eukrea_cpuimx35/eukrea_cpuimx35.c Normal file
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@ -0,0 +1,343 @@
/*
* Copyright (C) 2007 Sascha Hauer, Pengutronix
* 2009 Marc Kleine-Budde, Pengutronix
* (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Derived from:
*
* * mx35_3stack.c - board file for uboot-v1
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*
*/
#include <common.h>
#include <command.h>
#include <environment.h>
#include <errno.h>
#include <fcntl.h>
#include <fec.h>
#include <fs.h>
#include <init.h>
#include <nand.h>
#include <net.h>
#include <partition.h>
#include <asm/armlinux.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mmu.h>
#include <mach/gpio.h>
#include <mach/imx-nand.h>
#include <mach/imx-regs.h>
#include <mach/iomux-mx35.h>
#include <mach/iomux-v3.h>
#include <mach/pmic.h>
#include <mach/imx-ipu-fb.h>
#include <mach/imx-pll.h>
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 0x1F,
};
static struct device_d fec_dev = {
.name = "fec_imx",
.map_base = IMX_FEC_BASE,
.platform_data = &fec_info,
};
static struct memory_platform_data sdram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 128 * 1024 * 1024,
.platform_data = &sdram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct device_d nand_dev = {
.name = "imx_nand",
.map_base = IMX_NFC_BASE,
.platform_data = &nand_info,
};
static struct fb_videomode imxfb_mode = {
.name = "CMO_QVGA",
.refresh = 60,
.xres = 320,
.yres = 240,
.pixclock = KHZ2PICOS(7000),
.left_margin = 68,
.right_margin = 20,
.upper_margin = 15,
.lower_margin = 4,
.hsync_len = 30,
.vsync_len = 3,
.sync = FB_SYNC_OE_ACT_HIGH,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
};
static struct imx_ipu_fb_platform_data ipu_fb_data = {
.mode = &imxfb_mode,
.bpp = 16,
};
static struct device_d imxfb_dev = {
.name = "imx-ipu-fb",
.map_base = 0x53fc0000,
.size = 0x1000,
.platform_data = &ipu_fb_data,
};
#ifdef CONFIG_MMU
static int eukrea_cpuimx35_mmu_init(void)
{
mmu_init();
arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
#if TEXT_BASE & (0x100000 - 1)
#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
#else
arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
#endif
mmu_enable();
#ifdef CONFIG_CACHE_L2X0
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
#endif
return 0;
}
postcore_initcall(eukrea_cpuimx35_mmu_init);
#endif
static int eukrea_cpuimx35_devices_init(void)
{
register_device(&nand_dev);
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
register_device(&fec_dev);
register_device(&sdram_dev);
register_device(&imxfb_dev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);
return 0;
}
device_initcall(eukrea_cpuimx35_devices_init);
static int eukrea_cpuimx35_enable_display(void)
{
gpio_direction_output(1, 1);
gpio_direction_output(0, 0);
return 0;
}
late_initcall(eukrea_cpuimx35_enable_display);
static struct device_d eukrea_cpuimx35_serial_device = {
.name = "imx_serial",
.map_base = IMX_UART1_BASE,
.size = 4096,
};
static struct pad_desc eukrea_cpuimx35_pads[] = {
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
MX35_PAD_FEC_RX_DV__FEC_RX_DV,
MX35_PAD_FEC_COL__FEC_COL,
MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
MX35_PAD_FEC_TX_EN__FEC_TX_EN,
MX35_PAD_FEC_MDC__FEC_MDC,
MX35_PAD_FEC_MDIO__FEC_MDIO,
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
MX35_PAD_FEC_CRS__FEC_CRS,
MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
MX35_PAD_RXD1__UART1_RXD_MUX,
MX35_PAD_TXD1__UART1_TXD_MUX,
MX35_PAD_RTS1__UART1_RTS,
MX35_PAD_CTS1__UART1_CTS,
};
static int eukrea_cpuimx35_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
ARRAY_SIZE(eukrea_cpuimx35_pads));
register_device(&eukrea_cpuimx35_serial_device);
return 0;
}
console_initcall(eukrea_cpuimx35_console_init);
static int eukrea_cpuimx35_core_init(void)
{
u32 reg;
/* enable clock for I2C1 and FEC */
reg = readl(IMX_CCM_BASE + CCM_CGR1);
reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, IMX_AIPS1_BASE);
writel(0x77777777, IMX_AIPS1_BASE + 0x4);
writel(0x77777777, IMX_AIPS2_BASE);
writel(0x77777777, IMX_AIPS2_BASE + 0x4);
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
writel(0x0, IMX_AIPS1_BASE + 0x40);
writel(0x0, IMX_AIPS1_BASE + 0x44);
writel(0x0, IMX_AIPS1_BASE + 0x48);
writel(0x0, IMX_AIPS1_BASE + 0x4C);
reg = readl(IMX_AIPS1_BASE + 0x50);
reg &= 0x00FFFFFF;
writel(reg, IMX_AIPS1_BASE + 0x50);
writel(0x0, IMX_AIPS2_BASE + 0x40);
writel(0x0, IMX_AIPS2_BASE + 0x44);
writel(0x0, IMX_AIPS2_BASE + 0x48);
writel(0x0, IMX_AIPS2_BASE + 0x4C);
reg = readl(IMX_AIPS2_BASE + 0x50);
reg &= 0x00FFFFFF;
writel(reg, IMX_AIPS2_BASE + 0x50);
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
#define MAX_PARAM1 0x00302154
writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
/* SGPCR - always park on last master */
writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
/* MGPCR - restore default values */
writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
/*
* M3IF Control Register (M3IFCTL)
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
* MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
* MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
* MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
* MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
* ------------
* 0x00000040
*/
writel(0x40, IMX_M3IF_BASE);
return 0;
}
core_initcall(eukrea_cpuimx35_core_init);
#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
static int do_cpufreq(struct command *cmdtp, int argc, char *argv[])
{
unsigned long freq;
if (argc != 2)
return COMMAND_ERROR_USAGE;
freq = simple_strtoul(argv[1], NULL, 0);
switch (freq) {
case 399:
writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
break;
case 532:
writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
}
printf("Switched CPU frequency to %dMHz\n", freq);
return 0;
}
static const __maybe_unused char cmd_cpufreq_help[] =
"Usage: cpufreq 399|532\n"
"\n"
"Set CPU frequency to <freq> MHz\n";
BAREBOX_CMD_START(cpufreq)
.cmd = do_cpufreq,
.usage = "adjust CPU frequency",
BAREBOX_CMD_HELP(cmd_cpufreq_help)
BAREBOX_CMD_END

4
board/eukrea_cpuimx35/eukrea_cpuimx35.dox Normal file
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/** @page eukrea_cpuimx35 Eukrea's CPUIMX35
*/

60
board/eukrea_cpuimx35/flash_header.c Normal file
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#include <common.h>
#include <mach/imx-flash-header.h>
extern unsigned long _stext;
void __naked __flash_header_start go(void)
{
__asm__ __volatile__("b exception_vectors\n");
}
struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = {
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
{ .ptr_type = 1, .addr = 0x80000400, .val = 0x12345678, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
{ .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82220080, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82228080, },
{ .ptr_type = 4, .addr = 0xB8001020, .val = 0x80000028, },
{ .ptr_type = 4, .addr = 0xB8001024, .val = 0x80000028, },
{ .ptr_type = 4, .addr = 0xB8001028, .val = 0x80000028, },
{ .ptr_type = 4, .addr = 0xB800102c, .val = 0x80000028, },
{ .ptr_type = 4, .addr = 0xB8001030, .val = 0x80000028, },
};
#define APP_DEST 0x80000000
struct imx_flash_header __flash_header_0x400 flash_header = {
.app_code_jump_vector = APP_DEST + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = APP_DEST,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof (dcd_entry),
};
unsigned long __image_len_0x400 barebox_len = 0x40000;

218
board/eukrea_cpuimx35/lowlevel.c Normal file
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/*
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <init.h>
#include <mach/imx-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
#include <asm/io.h>
#include <mach/imx-nand.h>
#include <asm/barebox-arm.h>
#include <asm-generic/memory_layout.h>
#include <asm/system.h>
/* Assuming 24MHz input clock */
#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(IMX_CCM_BASE + CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, IMX_CCM_BASE + CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
board_init_lowlevel_return();
}
#endif
void __bare_init __naked board_init_lowlevel(void)
{
uint32_t r, s;
unsigned long ccm_base = IMX_CCM_BASE;
unsigned long iomuxc_base = IMX_IOMUXC_BASE;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
#endif
r = get_cr();
r |= CR_Z; /* Flow prediction (Z) */
r |= CR_U; /* unaligned accesses */
r |= CR_FI; /* Low Int Latency */
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s));
s |= 0x7;
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
set_cr(r);
r = 0;
__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
/*
* Branch predicition is now enabled. Flush the BTAC to ensure a valid
* starting point. Don't flush BTAC while it is disabled to avoid
* ARM1136 erratum 408023.
*/
__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
/* invalidate I cache and D cache */
__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
/* invalidate TLBs */
__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
/* Drain the write buffer */
__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
/* Also setup the Peripheral Port Remap register inside the core */
r = 0x40000015; /* start from AIPS 2GB region */
__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
/*
* End of ARM1136 init
*/
writel(0x003F4208, ccm_base + CCM_CCMR);
/* Set MPLL , arm clock and ahb clock*/
writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL);
writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
writel(0x00001000, ccm_base + CCM_PDR0);
r = readl(ccm_base + CCM_CGR0);
r |= 0x00300000;
writel(r, ccm_base + CCM_CGR0);
r = readl(ccm_base + CCM_CGR1);
r |= 0x00000C00;
r |= 0x00000003;
writel(r, ccm_base + CCM_CGR1);
r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
r |= 0x1000;
writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0x80000000 && r < 0x90000000)
board_init_lowlevel_return();
/* Set DDR Type to SDRAM, drive strength workaround *
* 0x00000000 MDDR *
* 0x00000800 3,3V SDRAM */
r = 0x00000800;
writel(r, iomuxc_base + 0x794);
writel(r, iomuxc_base + 0x798);
writel(r, iomuxc_base + 0x79c);
writel(r, iomuxc_base + 0x7a0);
writel(r, iomuxc_base + 0x7a4);
/* MDDR init, enable mDDR*/
writel(0x00000304, ESDMISC); /* was 0x00000004 */
/* set timing paramters */
writel(0x00255417, ESDCFG0);
/* select Precharge-All mode */
writel(0x92220000, ESDCTL0);
/* Precharge-All */
writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
/* select Load-Mode-Register mode */
writel(0xB8001000, ESDCTL0);
/* Load reg EMR2 */
writeb(0xda, 0x84000000);
/* Load reg EMR3 */
writeb(0xda, 0x86000000);
/* Load reg EMR1 -- enable DLL */
writeb(0xda, 0x82000400);
/* Load reg MR -- reset DLL */
writeb(0xda, 0x80000333);
/* select Precharge-All mode */
writel(0x92220000, ESDCTL0);
/* Precharge-All */
writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
/* select Manual-Refresh mode */
writel(0xA2220000, ESDCTL0);
/* Manual-Refresh 2 times */
writel(0x87654321, IMX_SDRAM_CS0);
writel(0x87654321, IMX_SDRAM_CS0);
/* select Load-Mode-Register mode */
writel(0xB2220000, ESDCTL0);
/* Load reg MR -- CL3, BL8, end DLL reset */
writeb(0xda, 0x80000233);
/* Load reg EMR1 -- OCD default */
writeb(0xda, 0x82000780);
/* Load reg EMR1 -- OCD exit */
writeb(0xda, 0x82000400);
/* select normal-operation mode
* DSIZ32-bit, BL8, COL10-bit, ROW13-bit
* disable PWT & PRCT
* disable Auto-Refresh */
writel(0x82220080, ESDCTL0);
/* enable Auto-Refresh */
writel(0x82228080, ESDCTL0);
/* enable Auto-Refresh */
writel(0x00002000, ESDCTL1);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
#else
board_init_lowlevel_return();
#endif
}