MIPS: cpuinfo: import CPU message from Linux 3.4
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -23,11 +23,34 @@
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#include <common.h>
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#include <command.h>
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#include <asm/mipsregs.h>
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#include <asm/cpu-info.h>
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static char *way_string[] = { NULL, "direct mapped", "2-way",
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"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
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};
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static int do_cpuinfo(int argc, char *argv[])
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{
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printf("CP0_PRID = 0x%08x\n", read_c0_prid());
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printf("CP0_CONFIG = 0x%08x\n", read_c0_config());
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unsigned int icache_size, dcache_size;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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printk(KERN_INFO "CPU revision is: %08x (%s)\n",
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current_cpu_data.processor_id, __cpu_name);
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icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
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dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
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printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
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icache_size >> 10,
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c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
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way_string[c->icache.ways], c->icache.linesz);
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printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
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dcache_size >> 10, way_string[c->dcache.ways],
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(c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
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(c->dcache.flags & MIPS_CACHE_ALIASES) ?
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"cache aliases" : "no aliases",
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c->dcache.linesz);
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return 0;
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}
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