ARCH: ARM: Add support for phytec-phycore-imx6ul
Add support for the phycore i.MX6 UltraLite. - 512MB RAM - 512MB NAND - 10/100 Mbit Ethernet Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Christian Hemp
Sascha Hauer
parent
3807409640
commit
f4d4b659e4
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@ -2,3 +2,4 @@ obj-y += board.o
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lwl-y += lowlevel.o
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bbenv-y += defaultenv-physom-imx6
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bbenv-y += defaultenv-physom-imx6-phycore
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bbenv-y += defaultenv-physom-imx6ul-phycore
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@ -30,6 +30,9 @@
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#include <of.h>
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#include <mach/bbu.h>
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#include <platform_data/eth-fec.h>
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#include <mfd/imx6q-iomuxc-gpr.h>
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#include <linux/clk.h>
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#include <linux/micrel_phy.h>
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#include <globalvar.h>
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@ -86,6 +89,56 @@ static unsigned int get_module_rev(void)
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return 16 - val;
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}
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int ksz8081_phy_fixup(struct phy_device *phydev)
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{
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phy_write(phydev, 0x1f, 0x8190);
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phy_write(phydev, 0x16, 0x202);
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return 0;
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}
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static int imx6ul_setup_fec(void)
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{
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void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000;
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uint32_t val;
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struct clk *clk;
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phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
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ksz8081_phy_fixup);
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clk = clk_lookup("enet_ptp");
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if (IS_ERR(clk))
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goto err;
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clk_enable(clk);
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clk = clk_lookup("enet_ref");
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if (IS_ERR(clk))
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goto err;
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clk_enable(clk);
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clk = clk_lookup("enet_ref_125m");
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if (IS_ERR(clk))
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goto err;
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clk_enable(clk);
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val = readl(gprbase + IOMUXC_GPR1);
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/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
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val &= ~(1 << 13);
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val |= (1 << 17);
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/* Use 50M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], set gpr1[18]*/
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val &= ~(1 << 14);
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val |= (1 << 18);
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writel(val, gprbase + IOMUXC_GPR1);
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return 0;
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err:
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pr_err("Setting up DFEC\n");
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return -EIO;
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}
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static int physom_imx6_devices_init(void)
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{
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int ret;
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@ -121,6 +174,11 @@ static int physom_imx6_devices_init(void)
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default_environment_path = "/chosen/environment-spinor";
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default_envdev = "SPI NOR flash";
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} else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
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barebox_set_hostname("phyCORE-i.MX6UL");
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default_environment_path = "/chosen/environment-nand";
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default_envdev = "NAND flash";
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imx6ul_setup_fec();
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} else
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return 0;
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@ -171,6 +229,8 @@ static int physom_imx6_devices_init(void)
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|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
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|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
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defaultenv_append_directory(defaultenv_physom_imx6_phycore);
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} else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
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defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
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}
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return 0;
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@ -0,0 +1,8 @@
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#!/bin/sh
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[ ! -e /dev/nand0.root.ubi ] && ubiattach /dev/nand0.root
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global.bootm.image="/dev/nand0.root.ubi.kernel"
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global.bootm.oftree="/dev/nand0.root.ubi.oftree"
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global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw"
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@ -0,0 +1,9 @@
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#!/bin/sh
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# automount tftp server based on $eth0.serverip
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mkdir -p /mnt/tftp
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automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp'
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mkdir -p /mnt/mmc
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automount -d /mnt/mmc 'mmc0.probe=1 && [ -e /dev/mmc0.0 ] && mount /dev/mmc0.0 /mnt/mmc'
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@ -0,0 +1,9 @@
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#define SETUP_MDCFG0 \
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wm 32 0x021B000C 0x676B52F3
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#define SETUP_MDASP_MDCTL \
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wm 32 0x021B0040 0x0000004F; \
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wm 32 0x021B0000 0x84180000
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#include "flash-header-phytec-pcl063.h"
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@ -0,0 +1,70 @@
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loadaddr 0x80000000
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soc imx6
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dcdofs 0x400
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wm 32 0x020c4068 0xffffffff
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wm 32 0x020c406c 0xffffffff
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wm 32 0x020c4070 0xffffffff
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wm 32 0x020c4074 0xffffffff
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wm 32 0x020c4078 0xffffffff
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wm 32 0x020c407c 0xffffffff
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wm 32 0x020c4080 0xffffffff
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wm 32 0x020E04B4 0x000C0000
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wm 32 0x020E04AC 0x00000000
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wm 32 0x020E027C 0x00000030
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wm 32 0x020E0250 0x00000030
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wm 32 0x020E024C 0x00000030
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wm 32 0x020E0490 0x00000030
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wm 32 0x020E0288 0x00000030
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wm 32 0x020E0270 0x00000000
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wm 32 0x020E0260 0x00000030
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wm 32 0x020E0264 0x00000030
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wm 32 0x020E04A0 0x00000030
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wm 32 0x020E0494 0x00020000
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wm 32 0x020E0280 0x00000030
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wm 32 0x020E0284 0x00000030
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wm 32 0x020E04B0 0x00020000
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wm 32 0x020E0498 0x00000030
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wm 32 0x020E04A4 0x00000030
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wm 32 0x020E0244 0x00000030
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wm 32 0x020E0248 0x00000030
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wm 32 0x021B001C 0x00008000
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wm 32 0x021B0800 0xA1390003
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wm 32 0x021B080C 0x00000000
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wm 32 0x021B083C 0x41480148
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wm 32 0x021B0848 0x40403E42
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wm 32 0x021B0850 0x40405852
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wm 32 0x021B081C 0x33333333
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wm 32 0x021B0820 0x33333333
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wm 32 0x021B082C 0xf3333333
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wm 32 0x021B0830 0xf3333333
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wm 32 0x021B08C0 0x00922012
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wm 32 0x021B0858 0x00000F00
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wm 32 0x021B08b8 0x00000800
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wm 32 0x021B0004 0x0002002D
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wm 32 0x021B0008 0x1B333030
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SETUP_MDCFG0
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wm 32 0x021B0010 0xB66D0B63
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wm 32 0x021B0014 0x01FF00DB
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wm 32 0x021B0018 0x00211740
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wm 32 0x021B001C 0x00008000
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wm 32 0x021B002C 0x000026D2
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wm 32 0x021B0030 0x006B1023
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SETUP_MDASP_MDCTL
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wm 32 0x021b0890 0x00400A38
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wm 32 0x021B001C 0x02008032
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wm 32 0x021B001C 0x00008033
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wm 32 0x021B001C 0x00048031
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wm 32 0x021B001C 0x15208030
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wm 32 0x021B001C 0x04008040
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wm 32 0x021B0020 0x00007800
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wm 32 0x021B0818 0x00000227
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wm 32 0x021B0004 0x0002556D
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wm 32 0x021B0404 0x00011006
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wm 32 0x021B001C 0x00000000
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@ -51,17 +51,28 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
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bool do_early_uart_config,
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void *fdt_blob_fixed_offset)
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{
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int cpu_type = __imx6_cpu_type();
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void *fdt;
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imx6_cpu_lowlevel_init();
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arm_setup_stack(0x00920000 - 8);
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if (cpu_type == IMX6_CPUTYPE_IMX6UL) {
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arm_cpu_lowlevel_init();
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/* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */
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arm_setup_stack(0x00910000 - 8);
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} else {
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imx6_cpu_lowlevel_init();
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/* OCRAM Free Area is 0x00907000 to 0x00938000 (196KB) */
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arm_setup_stack(0x00920000 - 8);
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}
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if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL))
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setup_uart();
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fdt = fdt_blob_fixed_offset - get_runtime_offset();
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barebox_arm_entry(0x10000000, size, fdt);
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if (cpu_type == IMX6_CPUTYPE_IMX6UL)
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barebox_arm_entry(0x80000000, size, fdt);
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else
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barebox_arm_entry(0x10000000, size, fdt);
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}
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#define PHYTEC_ENTRY(name, fdt_name, memory_size, do_early_uart_config) \
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@ -98,3 +109,5 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_so
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PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
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PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false);
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@ -51,7 +51,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
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imx6q-phytec-phycore-som-nand.dtb.o \
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imx6q-phytec-phycore-som-emmc.dtb.o \
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imx6dl-phytec-phycore-som-nand.dtb.o \
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imx6dl-phytec-phycore-som-emmc.dtb.o
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imx6dl-phytec-phycore-som-emmc.dtb.o \
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imx6ul-phytec-phycore-som.dtb.o
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pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
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pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
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@ -0,0 +1,185 @@
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/*
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include <arm/imx6ul.dtsi>
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/ {
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model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
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compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
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chosen {
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linux,stdout-path = &uart1;
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environment-nand {
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compatible = "barebox,environment";
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device-path = &gpmi, "partname:barebox-environment";
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status = "disabled";
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};
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environment-sd1 {
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compatible = "barebox,environment";
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device-path = &usdhc1, "partname:barebox-environment";
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status = "disabled";
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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fsl,no-blockmark-swap;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "barebox";
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reg = <0x0 0x400000>;
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};
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partition@400000 {
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label = "barebox-environment";
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reg = <0x400000 0x100000>;
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};
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partition@500000 {
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label = "root";
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reg = <0x500000 0x0>;
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 =<&pinctrl_i2c1>;
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clock-frequency = <100000>;
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status = "okay";
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eeprom@52 {
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compatible = "cat,24c32";
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reg = <0x52>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "barebox";
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reg = <0x0 0xe0000>;
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};
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partition@e0000 {
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label = "barebox-environment";
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reg = <0xe0000 0x20000>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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imx6ul-phytec-phycore-som {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
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MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
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MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
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MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
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MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
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MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
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MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
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MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
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MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
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MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
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MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
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MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
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MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
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MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
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MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
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>;
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};
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pinctrl_i2c1: i2cgrp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
|
||||
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -262,6 +262,7 @@ config MACH_FREESCALE_MX53_VMX53
|
|||
config MACH_PHYTEC_SOM_IMX6
|
||||
bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6"
|
||||
select ARCH_IMX6
|
||||
select ARCH_IMX6UL
|
||||
|
||||
config MACH_DFI_FS700_M60
|
||||
bool "DFI i.MX6 FS700 M60 Q7 Board"
|
||||
|
|
|
|||
|
|
@ -394,6 +394,11 @@ CFG_start_phytec_phycore_imx6dl_som_emmc_1gib.pblx.imximg = $(board)/phytec-som-
|
|||
FILE_barebox-phytec-phycore-imx6dl-som-emmc-1gib.img = start_phytec_phycore_imx6dl_som_emmc_1gib.pblx.imximg
|
||||
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6dl-som-emmc-1gib.img
|
||||
|
||||
pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ul_som_512mb
|
||||
CFG_start_phytec_phycore_imx6ul_som_512mb.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
|
||||
FILE_barebox-phytec-phycore-imx6ul-512mb.img = start_phytec_phycore_imx6ul_som_512mb.pblx.imximg
|
||||
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ul-512mb.img
|
||||
|
||||
pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64
|
||||
CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
|
||||
FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg
|
||||
|
|
|
|||
Loading…
Reference in New Issue