9
0
Fork 0

ARM: OMAP: Add SoC prefix to running_in_* functions

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2013-11-21 13:55:38 +01:00
parent 6e2a60bb4f
commit f6b399ef9b
12 changed files with 30 additions and 24 deletions

View File

@ -168,7 +168,7 @@ static void sdrc_init(void)
*/
static int beagle_board_init(void)
{
int in_sdram = running_in_sdram();
int in_sdram = omap3_running_in_sdram();
if (!in_sdram)
omap3_core_init();

View File

@ -121,7 +121,7 @@ static int beaglebone_board_init(void)
__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
if (running_in_sdram())
if (am33xx_running_in_sdram())
return 0;
/* Setup the PLLs and the clocks for the peripherals */

View File

@ -536,7 +536,7 @@ static void mux_config(void)
*/
static int sdp343x_board_init(void)
{
int in_sdram = running_in_sdram();
int in_sdram = omap3_running_in_sdram();
if (!in_sdram)
omap3_core_init();

View File

@ -148,7 +148,7 @@ static void mux_config(void)
*/
static int omap3_evm_board_init(void)
{
int in_sdram = running_in_sdram();
int in_sdram = omap3_running_in_sdram();
omap3_core_init();

View File

@ -65,7 +65,7 @@ static int pcm051_board_init(void)
writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
if (running_in_sdram())
if (am33xx_running_in_sdram())
return 0;
pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);

View File

@ -239,7 +239,7 @@ static void pcaal1_mux_config(void)
*/
static int pcaal1_board_init(void)
{
int in_sdram = running_in_sdram();
int in_sdram = omap3_running_in_sdram();
if (!in_sdram)
omap3_core_init();

View File

@ -68,7 +68,7 @@ u32 am33xx_get_cpu_rev(void)
*
* @return base address
*/
u32 get_base(void)
static u32 get_base(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
@ -84,7 +84,7 @@ u32 get_base(void)
*
* @return 1 if we are running in XIP mode, else return 0
*/
u32 running_in_flash(void)
u32 am33xx_running_in_flash(void)
{
if (get_base() < 4)
return 1; /* in flash */
@ -98,7 +98,7 @@ u32 running_in_flash(void)
*
* @return 1 if we are running in SRAM, else return 0
*/
u32 running_in_sram(void)
u32 am33xx_running_in_sram(void)
{
if (get_base() == 4)
return 1; /* in SRAM */
@ -113,7 +113,7 @@ u32 running_in_sram(void)
*
* @return 1 if we are running from SDRAM, else return 0
*/
u32 running_in_sdram(void)
u32 am33xx_running_in_sdram(void)
{
if (get_base() > 4)
return 1; /* in sdram */

View File

@ -22,4 +22,8 @@ static inline void am33xx_save_bootinfo(uint32_t *info)
omap_save_bootinfo(info);
}
u32 am33xx_running_in_flash(void);
u32 am33xx_running_in_sram(void);
u32 am33xx_running_in_sdram(void);
#endif /* __MACH_AM33XX_GENERIC_H */

View File

@ -1,6 +1,7 @@
#ifndef __MACH_OMAP3_GENERIC_H
#define __MACH_OMAP3_GENERIC_H
#include <sizes.h>
#include <mach/generic.h>
#include <mach/omap3-silicon.h>
@ -18,4 +19,8 @@ static inline void omap3_save_bootinfo(uint32_t *info)
omap_save_bootinfo(info);
}
u32 omap3_running_in_flash(void);
u32 omap3_running_in_sram(void);
u32 omap3_running_in_sdram(void);
#endif /* __MACH_OMAP3_GENERIC_H */

View File

@ -91,10 +91,6 @@ u32 get_cpu_rev(void);
u32 get_sdr_cs_size(u32 offset);
u32 get_sdr_cs1_base(void);
inline u32 get_sysboot_value(void);
u32 get_base(void);
u32 running_in_flash(void);
u32 running_in_sram(void);
u32 running_in_sdram(void);
u32 get_boot_type(void);
u32 get_device_type(void);

View File

@ -33,6 +33,7 @@
#include <common.h>
#include <io.h>
#include <mach/omap3-silicon.h>
#include <mach/omap3-generic.h>
#include <mach/clocks.h>
#include <mach/omap3-clock.h>
#include <mach/timers.h>
@ -170,7 +171,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
if (running_in_sram()) {
if (omap3_running_in_sram()) {
sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
@ -209,7 +210,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
/* Lock Mode */
sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
} else if (running_in_flash()) {
} else if (omap3_running_in_flash()) {
/***Oopps.. Wrong .config!! *****/
hang();
}
@ -403,7 +404,7 @@ static void init_core_dpll_36x(u32 cpu_rev, u32 clk_sel)
dp += clk_sel;
if (running_in_sram()) {
if (omap3_running_in_sram()) {
sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
@ -435,7 +436,7 @@ static void init_core_dpll_36x(u32 cpu_rev, u32 clk_sel)
/* Lock Mode */
sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
} else if (running_in_flash()) {
} else if (omap3_running_in_flash()) {
/***Oopps.. Wrong .config!! *****/
hang();
}

View File

@ -213,7 +213,7 @@ inline u32 get_sysboot_value(void)
*
* @return base address
*/
u32 get_base(void)
static u32 get_base(void)
{
u32 val;
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
@ -229,7 +229,7 @@ u32 get_base(void)
*
* @return 1 if we are running in XIP mode, else return 0
*/
u32 running_in_flash(void)
u32 omap3_running_in_flash(void)
{
if (get_base() < 4)
return 1; /* in flash */
@ -243,7 +243,7 @@ u32 running_in_flash(void)
*
* @return 1 if we are running in SRAM, else return 0
*/
u32 running_in_sram(void)
u32 omap3_running_in_sram(void)
{
if (get_base() == 4)
return 1; /* in SRAM */
@ -258,13 +258,13 @@ u32 running_in_sram(void)
*
* @return 1 if we are running from SDRAM, else return 0
*/
u32 running_in_sdram(void)
u32 omap3_running_in_sdram(void)
{
if (get_base() > 4)
return 1; /* in sdram */
return 0; /* running in SRAM or FLASH */
}
EXPORT_SYMBOL(running_in_sdram);
EXPORT_SYMBOL(omap3_running_in_sdram);
/**
* @brief Is this an XIP type device or a stream one
@ -408,7 +408,7 @@ void setup_auxcr(void);
static void try_unlock_memory(void)
{
int mode;
int in_sdram = running_in_sdram();
int in_sdram = omap3_running_in_sdram();
/* if GP device unlock device SRAM for general use */
/* secure code breaks for Secure/Emulation device - HS/E/T */