ARM: OMAP: Add SoC prefix to running_in_* functions
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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6e2a60bb4f
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@ -168,7 +168,7 @@ static void sdrc_init(void)
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*/
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*/
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static int beagle_board_init(void)
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static int beagle_board_init(void)
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{
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{
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int in_sdram = running_in_sdram();
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int in_sdram = omap3_running_in_sdram();
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if (!in_sdram)
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if (!in_sdram)
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omap3_core_init();
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omap3_core_init();
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@ -121,7 +121,7 @@ static int beaglebone_board_init(void)
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__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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if (running_in_sdram())
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if (am33xx_running_in_sdram())
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return 0;
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return 0;
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/* Setup the PLLs and the clocks for the peripherals */
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/* Setup the PLLs and the clocks for the peripherals */
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@ -536,7 +536,7 @@ static void mux_config(void)
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*/
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*/
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static int sdp343x_board_init(void)
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static int sdp343x_board_init(void)
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{
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{
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int in_sdram = running_in_sdram();
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int in_sdram = omap3_running_in_sdram();
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if (!in_sdram)
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if (!in_sdram)
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omap3_core_init();
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omap3_core_init();
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@ -148,7 +148,7 @@ static void mux_config(void)
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*/
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*/
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static int omap3_evm_board_init(void)
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static int omap3_evm_board_init(void)
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{
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{
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int in_sdram = running_in_sdram();
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int in_sdram = omap3_running_in_sdram();
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omap3_core_init();
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omap3_core_init();
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@ -65,7 +65,7 @@ static int pcm051_board_init(void)
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writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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if (running_in_sdram())
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if (am33xx_running_in_sdram())
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return 0;
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return 0;
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pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
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pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
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@ -239,7 +239,7 @@ static void pcaal1_mux_config(void)
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*/
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*/
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static int pcaal1_board_init(void)
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static int pcaal1_board_init(void)
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{
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{
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int in_sdram = running_in_sdram();
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int in_sdram = omap3_running_in_sdram();
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if (!in_sdram)
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if (!in_sdram)
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omap3_core_init();
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omap3_core_init();
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@ -68,7 +68,7 @@ u32 am33xx_get_cpu_rev(void)
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*
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*
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* @return base address
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* @return base address
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*/
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*/
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u32 get_base(void)
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static u32 get_base(void)
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{
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{
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u32 val;
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u32 val;
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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@ -84,7 +84,7 @@ u32 get_base(void)
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*
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*
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* @return 1 if we are running in XIP mode, else return 0
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* @return 1 if we are running in XIP mode, else return 0
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*/
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*/
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u32 running_in_flash(void)
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u32 am33xx_running_in_flash(void)
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{
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{
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if (get_base() < 4)
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if (get_base() < 4)
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return 1; /* in flash */
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return 1; /* in flash */
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@ -98,7 +98,7 @@ u32 running_in_flash(void)
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*
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*
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* @return 1 if we are running in SRAM, else return 0
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* @return 1 if we are running in SRAM, else return 0
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*/
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*/
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u32 running_in_sram(void)
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u32 am33xx_running_in_sram(void)
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{
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{
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if (get_base() == 4)
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if (get_base() == 4)
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return 1; /* in SRAM */
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return 1; /* in SRAM */
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@ -113,7 +113,7 @@ u32 running_in_sram(void)
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*
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*
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* @return 1 if we are running from SDRAM, else return 0
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* @return 1 if we are running from SDRAM, else return 0
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*/
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*/
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u32 running_in_sdram(void)
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u32 am33xx_running_in_sdram(void)
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{
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{
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if (get_base() > 4)
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if (get_base() > 4)
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return 1; /* in sdram */
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return 1; /* in sdram */
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@ -22,4 +22,8 @@ static inline void am33xx_save_bootinfo(uint32_t *info)
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omap_save_bootinfo(info);
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omap_save_bootinfo(info);
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}
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}
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u32 am33xx_running_in_flash(void);
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u32 am33xx_running_in_sram(void);
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u32 am33xx_running_in_sdram(void);
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#endif /* __MACH_AM33XX_GENERIC_H */
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#endif /* __MACH_AM33XX_GENERIC_H */
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@ -1,6 +1,7 @@
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#ifndef __MACH_OMAP3_GENERIC_H
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#ifndef __MACH_OMAP3_GENERIC_H
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#define __MACH_OMAP3_GENERIC_H
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#define __MACH_OMAP3_GENERIC_H
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#include <sizes.h>
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#include <mach/generic.h>
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#include <mach/generic.h>
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#include <mach/omap3-silicon.h>
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#include <mach/omap3-silicon.h>
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@ -18,4 +19,8 @@ static inline void omap3_save_bootinfo(uint32_t *info)
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omap_save_bootinfo(info);
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omap_save_bootinfo(info);
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}
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}
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u32 omap3_running_in_flash(void);
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u32 omap3_running_in_sram(void);
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u32 omap3_running_in_sdram(void);
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#endif /* __MACH_OMAP3_GENERIC_H */
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#endif /* __MACH_OMAP3_GENERIC_H */
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@ -91,10 +91,6 @@ u32 get_cpu_rev(void);
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u32 get_sdr_cs_size(u32 offset);
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u32 get_sdr_cs_size(u32 offset);
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u32 get_sdr_cs1_base(void);
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u32 get_sdr_cs1_base(void);
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inline u32 get_sysboot_value(void);
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inline u32 get_sysboot_value(void);
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u32 get_base(void);
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u32 running_in_flash(void);
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u32 running_in_sram(void);
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u32 running_in_sdram(void);
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u32 get_boot_type(void);
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u32 get_boot_type(void);
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u32 get_device_type(void);
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u32 get_device_type(void);
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@ -33,6 +33,7 @@
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#include <common.h>
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#include <common.h>
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#include <io.h>
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#include <io.h>
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#include <mach/omap3-silicon.h>
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#include <mach/omap3-silicon.h>
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#include <mach/omap3-generic.h>
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#include <mach/clocks.h>
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#include <mach/clocks.h>
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#include <mach/omap3-clock.h>
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#include <mach/omap3-clock.h>
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#include <mach/timers.h>
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#include <mach/timers.h>
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@ -170,7 +171,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
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dp += clk_sel;
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dp += clk_sel;
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if (running_in_sram()) {
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if (omap3_running_in_sram()) {
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sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
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sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
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wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
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wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
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@ -209,7 +210,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel)
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/* Lock Mode */
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/* Lock Mode */
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sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
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sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
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wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
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wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
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} else if (running_in_flash()) {
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} else if (omap3_running_in_flash()) {
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/***Oopps.. Wrong .config!! *****/
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/***Oopps.. Wrong .config!! *****/
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hang();
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hang();
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}
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}
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@ -403,7 +404,7 @@ static void init_core_dpll_36x(u32 cpu_rev, u32 clk_sel)
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dp += clk_sel;
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dp += clk_sel;
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if (running_in_sram()) {
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if (omap3_running_in_sram()) {
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sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
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sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_FAST_RELOCK_BYPASS);
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wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
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wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
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@ -435,7 +436,7 @@ static void init_core_dpll_36x(u32 cpu_rev, u32 clk_sel)
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/* Lock Mode */
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/* Lock Mode */
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sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
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sr32(OMAP3_CM_REG(CLKEN_PLL), 0, 3, PLL_LOCK);
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wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
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wait_on_value((0x1 << 0), 1, OMAP3_CM_REG(IDLEST_CKGEN), LDELAY);
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} else if (running_in_flash()) {
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} else if (omap3_running_in_flash()) {
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/***Oopps.. Wrong .config!! *****/
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/***Oopps.. Wrong .config!! *****/
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hang();
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hang();
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}
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}
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@ -213,7 +213,7 @@ inline u32 get_sysboot_value(void)
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*
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*
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* @return base address
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* @return base address
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*/
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*/
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u32 get_base(void)
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static u32 get_base(void)
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{
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{
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u32 val;
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u32 val;
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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@ -229,7 +229,7 @@ u32 get_base(void)
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*
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*
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* @return 1 if we are running in XIP mode, else return 0
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* @return 1 if we are running in XIP mode, else return 0
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*/
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*/
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u32 running_in_flash(void)
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u32 omap3_running_in_flash(void)
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{
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{
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if (get_base() < 4)
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if (get_base() < 4)
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return 1; /* in flash */
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return 1; /* in flash */
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@ -243,7 +243,7 @@ u32 running_in_flash(void)
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*
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*
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* @return 1 if we are running in SRAM, else return 0
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* @return 1 if we are running in SRAM, else return 0
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*/
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*/
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u32 running_in_sram(void)
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u32 omap3_running_in_sram(void)
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{
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{
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if (get_base() == 4)
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if (get_base() == 4)
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return 1; /* in SRAM */
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return 1; /* in SRAM */
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@ -258,13 +258,13 @@ u32 running_in_sram(void)
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*
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*
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* @return 1 if we are running from SDRAM, else return 0
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* @return 1 if we are running from SDRAM, else return 0
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*/
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*/
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u32 running_in_sdram(void)
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u32 omap3_running_in_sdram(void)
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{
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{
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if (get_base() > 4)
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if (get_base() > 4)
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return 1; /* in sdram */
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return 1; /* in sdram */
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return 0; /* running in SRAM or FLASH */
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return 0; /* running in SRAM or FLASH */
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}
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}
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EXPORT_SYMBOL(running_in_sdram);
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EXPORT_SYMBOL(omap3_running_in_sdram);
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/**
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/**
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* @brief Is this an XIP type device or a stream one
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* @brief Is this an XIP type device or a stream one
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@ -408,7 +408,7 @@ void setup_auxcr(void);
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static void try_unlock_memory(void)
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static void try_unlock_memory(void)
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{
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{
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int mode;
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int mode;
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int in_sdram = running_in_sdram();
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int in_sdram = omap3_running_in_sdram();
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/* if GP device unlock device SRAM for general use */
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/* if GP device unlock device SRAM for general use */
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/* secure code breaks for Secure/Emulation device - HS/E/T */
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/* secure code breaks for Secure/Emulation device - HS/E/T */
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