mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC
Add support for 8bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -252,6 +252,17 @@ static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
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.oobfree = { {1, 4}, {6, 26}, {64, 32} }
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};
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static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
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.eccbytes = 64,
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.eccpos = {
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32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63},
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/* Bootrom looks in bytes 0 & 5 for bad blocks */
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.oobfree = { {1, 4}, {6, 26} }
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};
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#define NDTR0_tCH(c) (min((c), 7) << 19)
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#define NDTR0_tCS(c) (min((c), 7) << 16)
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#define NDTR0_tWH(c) (min((c), 7) << 11)
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@ -928,6 +939,31 @@ static int pxa_ecc_strength4(struct mrvl_nand_host *host,
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return -ENODEV;
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}
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static int pxa_ecc_strength8(struct mrvl_nand_host *host,
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struct nand_ecc_ctrl *ecc, int ecc_stepsize, int page_size)
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{
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if (!(host->hwflags & HWFLAGS_ECC_BCH))
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return -ENODEV;
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/*
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* Required ECC: 8-bit correction per 512 bytes
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* Select: 16-bit correction per 1024 bytes
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*/
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if (ecc_stepsize == 512 && page_size == 4096) {
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host->chunk_size = 1024;
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host->spare_size = 0;
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host->ecc_size = 32;
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host->ecc_bch = 1;
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ecc->mode = NAND_ECC_HW;
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ecc->size = 1024;
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ecc->layout = &ecc_layout_4KB_bch8bit;
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ecc->strength = 16;
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return 0;
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}
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return -ENODEV;
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}
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static int pxa_ecc_init(struct mrvl_nand_host *host,
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struct nand_ecc_ctrl *ecc,
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int strength, int ecc_stepsize, int page_size)
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@ -941,6 +977,9 @@ static int pxa_ecc_init(struct mrvl_nand_host *host,
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case 4:
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ret = pxa_ecc_strength4(host, ecc, ecc_stepsize, page_size);
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break;
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case 8:
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ret = pxa_ecc_strength8(host, ecc, ecc_stepsize, page_size);
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break;
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default:
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ret = -ENODEV;
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break;
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