i.MX remove wdog registers from header files
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
ca5bfba40e
commit
f81edffe0e
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@ -100,20 +100,35 @@ static int clocksource_init (void)
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core_initcall(clocksource_init);
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/*
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* Watchdog Registers
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*/
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#ifdef CONFIG_ARCH_IMX1
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#define WDOG_WCR 0x00 /* Watchdog Control Register */
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#define WDOG_WSR 0x04 /* Watchdog Service Register */
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#define WDOG_WSTR 0x08 /* Watchdog Status Register */
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#define WDOG_WCR_WDE (1 << 0)
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#else
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#define WDOG_WCR 0x00 /* Watchdog Control Register */
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#define WDOG_WSR 0x02 /* Watchdog Service Register */
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#define WDOG_WSTR 0x04 /* Watchdog Status Register */
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#define WDOG_WCR_WDE (1 << 2)
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#endif
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/*
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* Reset the cpu by setting up the watchdog timer and let it time out
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*/
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void __noreturn reset_cpu (unsigned long ignored)
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{
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/* Disable watchdog and set Time-Out field to 0 */
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WCR = 0x0000;
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writew(0x0, IMX_WDT_BASE + WDOG_WCR);
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/* Write Service Sequence */
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WSR = 0x5555;
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WSR = 0xAAAA;
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writew(0x5555, IMX_WDT_BASE + WDOG_WSR);
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writew(0xaaaa, IMX_WDT_BASE + WDOG_WSR);
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/* Enable watchdog */
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WCR = WCR_WDE;
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writew(WDOG_WCR_WDE, IMX_WDT_BASE + WDOG_WCR);
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while (1);
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/*NOTREACHED*/
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@ -40,14 +40,6 @@
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#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
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#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
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/* Watchdog Registers*/
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#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
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#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x01
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/* SYSCTRL Registers */
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#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
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#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
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@ -72,14 +72,6 @@
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#define CS5L __REG(IMX_EIM_BASE + 0x2C) /* Chip Select 5 Lower Register */
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#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
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/* Watchdog Registers*/
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#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
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#define WRSR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Reset Status Register */
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x04
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/* PLL registers */
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#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
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#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
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@ -82,14 +82,6 @@
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#include "esdctl.h"
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/* Watchdog Registers*/
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#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
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#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x04
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/* PLL registers */
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#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
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#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
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@ -119,16 +119,6 @@
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#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
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#endif
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/*
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* Watchdog Registers
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*/
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#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
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#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x04
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/*
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* Clock Controller Module (CCM)
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*/
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@ -135,15 +135,5 @@
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#define TSTAT_CAPT (1<<1) /* Capture event */
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#define TSTAT_COMP (1) /* Compare event */
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/*
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* Watchdog Registers
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*/
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#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
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#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x04
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#endif /* __ASM_ARCH_MX35_REGS_H */
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@ -24,13 +24,6 @@
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#define TSTAT_CAPT (1<<1) /* Capture event */
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#define TSTAT_COMP (1) /* Compare event */
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#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
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#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x04
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#define MX51_IROM_BASE_ADDR 0x0
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/*
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