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ARM: tegra30: ramp vdd_core to 1,2V 

This isn't much different from the default 1,16V
and I haven't seen this make a difference on any
board, but it seems to be required for some T30 SKUs.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach 2014-05-07 22:05:30 +02:00 committed by Sascha Hauer
parent acbecd1987
commit fb6e4db3ce
2 changed files with 19 additions and 0 deletions
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1
arch/arm/boards/nvidia-beaver/entry.c
View File

@ -30,6 +30,7 @@ ENTRY_FUNCTION(start_nvidia_beaver, r0, r1, r2)
tegra_cpu_lowlevel_setup();
tegra_dvc_init();
tegra30_tps62366a_ramp_vddcore();
tegra30_tps65911_cpu_rail_enable();
fdt = (uint32_t)__dtb_tegra30_beaver_start - get_runtime_offset();

18
arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
View File

@ -70,3 +70,21 @@ void tegra30_tps65911_cpu_rail_enable(void)
tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES);
tegra_ll_delay_usec(10 * 1000);
}
static inline __attribute__((always_inline))
void tegra30_tps62366a_ramp_vddcore(void)
{
tegra_dvc_write_addr(0xc0, 2);
/* set VDDcore to 1,2V */
tegra_dvc_write_data(0x4601, TEGRA_I2C_SEND_2_BYTES);
tegra_ll_delay_usec(1000);
}
static inline __attribute__((always_inline))
void tegra30_tps62361b_ramp_vddcore(void)
{
tegra_dvc_write_addr(0xc0, 2);
/* set VDDcore to 1,2V */
tegra_dvc_write_data(0x4603, TEGRA_I2C_SEND_2_BYTES);
tegra_ll_delay_usec(1000);
}