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edb9302(a): Tweak PLL settings 

Previous code ran the edb9302(a) boards with the PLL same settings as the
edb9301, at 166MHz core and 66MHz system bus clock. In difference to the edb9301
board the edb9302(a) is equipped with an EP9302 processor, which can be clocked
at higher rates than the EP9301. Therefore we can configure the edb9302(a) with
the same PLL settings as the other non-edb9301 boards, namely at 200MHz for
the core and 100MHz for the system bus clock.

Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Matthias Kaehlcke 2010-02-11 21:10:04 +01:00 committed by Sascha Hauer
parent c5b99bce5d
commit fbff75575d
2 changed files with 7 additions and 6 deletions
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6
board/edb93xx/pll_cfg.h
View File

@ -25,8 +25,7 @@
#include <config.h>
#include <mach/ep93xx-regs.h>
#if defined(CONFIG_MACH_EDB9301) || defined(CONFIG_MACH_EDB9302) || \
defined(CONFIG_MACH_EDB9302A)
#if defined(CONFIG_MACH_EDB9301)
/*
* fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
* pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
@ -39,7 +38,8 @@
3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
SYSCON_CLKSET1_NBYP1 | \
1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
#elif defined(CONFIG_MACH_EDB9307) || defined(CONFIG_MACH_EDB9307A) ||\
#elif defined(CONFIG_MACH_EDB9302) || defined(CONFIG_MACH_EDB9302A) || \
defined(CONFIG_MACH_EDB9307) || defined(CONFIG_MACH_EDB9307A) || \
defined CONFIG_MACH_EDB9312 || defined(CONFIG_MACH_EDB9315) ||\
defined(CONFIG_MACH_EDB9315A)
/*

7
board/edb93xx/sdram_cfg.h
View File

@ -43,12 +43,13 @@
* CLK cycle time min:
* @ CAS latency = 3: 7.5ns
* @ CAS latency = 2: 10ns
* We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
* so it's safe to use CAS latency = 2
* We're running at 66MHz (EDB9301) / 100Mhz (EDB9302(a)) external
* bus speed (HCLK), with a cycle time of 15ns / 10ns, so it's safe
* to use CAS latency = 2
*
* RAS-to-CAS delay min:
* 20ns
* At 15ns cycle time, we use RAS-to-CAS delay = 2
* At 15ns/10ns cycle time, we use RAS-to-CAS delay = 2
*
* SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
* as four blocks of 8MB size, instead of eight blocks of 4MB size: